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| regarding the change of names mentioned in the document, such as hitachi electric and hitachi xx, to renesas technology corp. the semiconductor operations of mitsubishi electric and hitachi were transferred to renesas technology corporation on april 1st 2003. these operations include microcomputer, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although hitachi, hitachi, ltd., hitachi semiconductors, and other hitachi brand names are mentioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. renesas technology home page: http://www.renesas.com renesas technology corp. customer support dept. april 1, 2003 to all our customers
cautions keep safety first in your circuit designs! 1. renesas technology corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas technology corporation or a third party. 2. renesas technology corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by renesas technology corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact renesas technology corporation or an authorized renesas technology corporation product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corporation by various means, including the renesas technology corporation semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact renesas technology corporation or an authorized renesas technology corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corporation is n ecessary to reprint or reproduce in whole or in part these materials. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8. please contact renesas technology corporation for further details on these materials or the products contained therein. hitachi 16-bit single-chip microcomputer h8s/2140b series h8s/2161b hd64f2161bv, hd6432161bv, hd6432161bvw h8s/2160b hd64f2160bv, hd6432160bv, hd6432160bvw h8s/2141b f-ztat tm hd64f2141bv h8s/2140b f-ztat tm hd64f2140bv h8s/2145b f-ztat tm hd64f2145bv h8s/2148b f-ztat tm hd64f2148bv, hd64f2148b hardware manual ade-602-274a rev. 2.0 08/01/02 hitachi, ltd. rev. 2.0, 08/02, page ii of xxxviii cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachis or any third partys patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third partys rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachis sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachis sales office for any questions regarding this document or hitachi semiconductor products. rev. 2.0, 08/02, page iii of xxxviii general precautions on handling of product 1. treatment of nc pins note: do not connect anything to the nc pins. the nc (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. if something is connected to the nc pins, the operation of the lsi is not guaranteed. 2. treatment of unused input pins note: fix all unused input pins to high or low level. generally, the input pins of cmos products are high-impedance input pins. if unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a pass- through current flows internally, and a malfunction may occur. 3. processing before initialization note: when power is first supplied, the products state is undefined. the states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. during the period where the states are undefined, the register settings and the output state of each pin are also undefined. design your system so that it does not malfunction because of processing while it is in this undefined state. for those products which have a reset function, reset the lsi immediately after the power supply has been turned on. 4. prohibition of access to undefined or reserved addresses note: access to undefined or reserved addresses is prohibited. the undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. do not access these registers; the systems operation is not guaranteed if they are accessed. rev. 2.0, 08/02, page iv of xxxviii configuration of this manual this manual comprises the following items: 1. general precautions on handling of product 2. configuration of this manual 3. preface 4. contents 5. overview 6. description of functional modules ? cpu and system-control modules ? on-chip peripheral modules the configuration of the functional description of each module differs according to the module. however, the generic style includes the following items: i) feature ii) input/output pin iii) register description iv) operation v) usage note when designing an application system that includes this lsi, take notes into account. each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. list of registers 8. electrical characteristics 9. appendix 10. main revisions and additions in this edition (only for revised versions) the list of revisions is a summary of points that have been revised or added to earlier versions. this does not include all of the revised contents. for details, see the actual locations in this manual. 11. index rev. 2.0, 08/02, page v of xxxviii preface the h8s/2140b series are microcomputers (mcus) made up of the h8s/2000 cpu employing hitachis original architecture as their cores, and the peripheral functions required to configure a system. the h8s/2000 cpu has an internal 32-bit configuration, sixteen 16-bit general registers, and a simple and optimized instruction set for high-speed operation. the h8s/2000 cpu can handle a 16-mbyte linear address space. this lsi is equipped with a data transfer controller (dtc) as a bus master, rom, ram, an 8-bit pwm timer (pwm), a 14-bit pwm timer (pwmx), a 16-bit free-running timer (frt), an 8-bit timer (tmr), timer connection, a watchdog timer (wdt), a serial communication interface (sci), a keyboard buffer controller, a host interface x-bus interface (xbs), a host interface lpc interface (lpc), an 8-bit d/a converter, a 10-bit a/d converter, and i/o ports as on-chip peripheral modules required for system configuration. an i 2 c bus interface (iic) can also be included as an optional interface. a high-functionality bus controller is also provided, enabling fast and easy connection of dram and other kinds of memory. a flash memory (f-ztat tm *) version is available for this lsi's rom. this provides flexibility as it can be reprogrammed in no time to cope with all situations from the early stages of mass production to full-scale mass production. this is particularly applicable to application devices with specifications that will most probably change. note: * f-ztat tm is a trademark of hitachi, ltd. target users: this manual was written for users who will be using the h8s/2140b series in the design of application systems. target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. objective: this manual was written to explain the hardware functions and electrical characteristics of the h8s/2140b series to the target users. refer to the h8s/2600 series, h8s/2000 series programming manual for a detailed description of the instruction set. notes on reading this manual: in order to understand the overall functions of the chip read the manual according to the contents. this manual can be roughly categorized into parts on the cpu, system control functions, peripheral functions and electrical characteristics. in order to understand the details of the cpu's functions rev. 2.0, 08/02, page vi of xxxviii read the h8s/2600 series, h8s/2000 series programming manual. in order to understand the details of a register when its name is known read the index that is the final part of the manual to find the page number of the entry on the register. the addresses, bits, and initial values of the registers are summarized in section 27, list of registers. rules: register name: the following notation is used for cases when the same or a similar function, e.g. serial communication interface, is implemented on more than one channel: xxx_n (xxx is the register name and n is the channel number) bit order: the msb is on the left and the lsb is on the right. number notation: binary is bxxxx, hexadecimal is hxxxx, decimal is xxxx. signal notation: an overbar is added to a low-active signal: [[[[ related manuals: the latest versions of all related manuals are available from our web site. please ensure you have the latest versions of all documents you require. http://www.hitachisemiconductor.com/ h8s/2140b series manuals: manual title ade no. h8s/2140b series hardware manual this manual h8s/2600 series, h8s/2000 series programming manual ade-602-083 user's manuals for development tools: manual title ade no. h8s, h8/300 series c/c++ compiler, assembler, optimizing linkage editor user's manual ade-702-247 h8s, h8/300 series simulator/debugger user's manual ade-702-282 h8s, h8/300 series hitachi embedded workshop, hitachi debugging interface tutorial ade-702-231 hitachi embedded workshop user's manual ade-702-201 rev. 2.0, 08/02, page vii of xxxviii contents section 1 overview ...........................................................................................1 1.1 features .................................................................................................................... .........1 1.2 block diagram ............................................................................................................... ...3 1.3 pin arrangement and functions ........................................................................................5 1.3.1 pin arrangement ..................................................................................................5 1.3.2 pin functions in each operating mode................................................................7 1.3.3 pin functions........................................................................................................18 section 2 cpu ...................................................................................................27 2.1 features .................................................................................................................... .........27 2.1.1 differences between h8s/2600 cpu and h8s/2000 cpu...................................28 2.1.2 differences from h8/300 cpu.............................................................................28 2.1.3 differences from h8/300h cpu ..........................................................................29 2.2 cpu operating modes ......................................................................................................30 2.2.1 normal mode .......................................................................................................30 2.2.2 advanced mode ...................................................................................................31 2.3 address space ............................................................................................................... ....33 2.4 register configuration ...................................................................................................... 34 2.4.1 general registers .................................................................................................35 2.4.2 program counter (pc)..........................................................................................36 2.4.3 extended control register (exr)........................................................................36 2.4.4 condition-code register (ccr) ..........................................................................36 2.4.5 initial register values ..........................................................................................38 2.5 data formats ................................................................................................................ .....38 2.5.1 general register data formats ............................................................................38 2.5.2 memory data formats .........................................................................................40 2.6 instruction set ............................................................................................................. ......41 2.6.1 table of instructions classified by function........................................................42 2.6.2 basic instruction formats.....................................................................................51 2.7 addressing modes and effective address calculation .....................................................52 2.7.1 register directrn .............................................................................................53 2.7.2 register indirect@ern ....................................................................................53 2.7.3 register indirect with displacement@(d:16, ern) or @(d:32, ern) ..............53 2.7.4 register indirect with post-increment or pre-decrement@ern+ or @-ern ..53 2.7.5 absolute address@aa:8, @aa:16, @aa:24, or @aa:32 ....................................53 2.7.6 immediate#xx:8, #xx:16, or #xx:32 .................................................................54 2.7.7 program-counter relative@(d:8, pc) or @(d:16, pc) ....................................54 2.7.8 memory indirect@@aa:8.................................................................................55 2.7.9 effective address calculation..............................................................................56 rev. 2.0, 08/02, page viii of xxxviii 2.8 processing states ........................................................................................................... ....58 2.9 usage notes................................................................................................................. ......60 2.9.1 note on tas instruction usage ...........................................................................60 2.9.2 note on stm/ldm instruction usage.................................................................60 2.9.3 note on bit manipulation instructions.................................................................60 2.9.4 eepmov instruction ...........................................................................................62 section 3 mcu operating modes..................................................................... 63 3.1 mcu operating mode selection.......................................................................................63 3.2 register descriptions ....................................................................................................... .63 3.2.1 mode control register (mdcr)..........................................................................64 3.2.2 system control register (syscr) ......................................................................65 3.2.3 serial timer control register (stcr).................................................................67 3.3 operating mode descriptions ...........................................................................................69 3.3.1 mode 1 .................................................................................................................69 3.3.2 mode 2 .................................................................................................................69 3.3.3 mode 3 .................................................................................................................69 3.3.4 pin functions in each operating mode ...............................................................69 3.4 address map in each operating mode .............................................................................71 section 4 exception handling........................................................................... 79 4.1 exception handling types and priority ............................................................................79 4.2 exception sources and exception vector table ...............................................................80 4.3 reset....................................................................................................................... ...........81 4.3.1 reset exception handling....................................................................................81 4.3.2 interrupts after reset ............................................................................................82 4.3.3 on-chip peripheral modules after reset is cancelled .........................................82 4.4 interrupt exception handling............................................................................................82 4.5 trap instruction exception handling ................................................................................82 4.6 stack status after exception handling ..............................................................................83 4.7 usage note .................................................................................................................. ......84 section 5 interrupt controller ........................................................................... 85 5.1 features .................................................................................................................... .........85 5.2 input/output pins ........................................................................................................... ...87 5.3 register descriptions ....................................................................................................... .87 5.3.1 interrupt control registers a to c (icra to icrc)............................................88 5.3.2 address break control register (abrkcr).......................................................89 5.3.3 break address registers a to c (bara to barc) ............................................89 5.3.4 irq sense control registers (iscrh, iscrl) ...................................................90 5.3.5 irq enable register (ier) ..................................................................................91 5.3.6 irq status register (isr) ....................................................................................92 rev. 2.0, 08/02, page ix of xxxviii 5.3.7 keyboard matrix interrupt mask registers (kmimra, kmimr) wake-up event interrupt mask register (wuemrb)........................................92 5.4 interrupt sources ........................................................................................................... ....94 5.4.1 external interrupts................................................................................................94 5.4.2 internal interrupts.................................................................................................96 5.5 interrupt exception handling vector table ......................................................................96 5.6 interrupt control modes and interrupt operation .............................................................99 5.6.1 interrupt control mode 0 .....................................................................................99 5.6.2 interrupt control mode 1 .....................................................................................101 5.6.3 interrupt exception handling sequence...............................................................103 5.6.4 interrupt response times.....................................................................................105 5.6.5 dtc activation by interrupt ................................................................................106 5.7 address break ............................................................................................................... ....107 5.7.1 features ................................................................................................................10 7 5.7.2 block diagram .....................................................................................................108 5.7.3 operation..............................................................................................................108 5.7.4 usage notes..........................................................................................................109 5.8 usage notes................................................................................................................. ......111 5.8.1 conflict between interrupt generation and disabling..........................................111 5.8.2 instructions that disable interrupts ......................................................................111 5.8.3 interrupts during execution of eepmov instruction ..........................................112 5.8.4 setting on product incorporating dtc.................................................................112 5.8.5 irq status register (isr) ....................................................................................112 section 6 bus controller....................................................................................113 6.1 features .................................................................................................................... .........113 6.2 input/output pins ........................................................................................................... ...114 6.3 register descriptions....................................................................................................... ..114 6.3.1 bus control register (bcr).................................................................................115 6.3.2 wait state control register (wscr)...................................................................116 6.4 bus control ................................................................................................................. ......117 6.4.1 bus specifications ................................................................................................117 6.4.2 advanced mode ...................................................................................................118 6.4.3 normal mode .......................................................................................................118 6.4.4 i/o select signals .................................................................................................119 6.5 basic bus interface......................................................................................................... ...120 6.5.1 data size and data alignment .............................................................................120 6.5.2 valid strobes ........................................................................................................121 6.5.3 basic operation timing .......................................................................................122 6.5.4 wait control.........................................................................................................130 6.6 burst rom interface ......................................................................................................... 131 6.6.1 basic operation timing .......................................................................................131 6.6.2 wait control.........................................................................................................132 rev. 2.0, 08/02, page x of xxxviii 6.7 idle cycle .................................................................................................................. ........133 6.8 bus arbitration............................................................................................................. .....134 6.8.1 priority of bus masters ........................................................................................134 6.8.2 bus transfer timing ............................................................................................134 section 7 data transfer controller (dtc)........................................................ 135 7.1 features .................................................................................................................... .........135 7.2 register descriptions ....................................................................................................... .136 7.2.1 dtc mode register a (mra).............................................................................137 7.2.2 dtc mode register b (mrb) .............................................................................138 7.2.3 dtc source address register (sar) ..................................................................138 7.2.4 dtc destination address register (dar) ..........................................................138 7.2.5 dtc transfer count register a (cra)...............................................................138 7.2.6 dtc transfer count register b (crb) ...............................................................139 7.2.7 dtc enable registers (dtcer) .........................................................................139 7.2.8 dtc vector register (dtvecr) ........................................................................140 7.3 activation sources .......................................................................................................... ..140 7.4 location of register information and dtc vector table.................................................141 7.5 operation................................................................................................................... ........144 7.5.1 normal mode .......................................................................................................145 7.5.2 repeat mode ........................................................................................................145 7.5.3 block transfer mode ...........................................................................................146 7.5.4 chain transfer......................................................................................................147 7.5.5 interrupts ..............................................................................................................14 8 7.5.6 operation timing .................................................................................................149 7.5.7 number of dtc execution states........................................................................150 7.6 procedures for using dtc ................................................................................................151 7.6.1 activation by interrupt .........................................................................................151 7.6.2 activation by software ........................................................................................151 7.7 examples of use of dtc ..................................................................................................152 7.7.1 normal mode .......................................................................................................152 7.7.2 software activation .............................................................................................153 7.8 usage notes................................................................................................................. ......154 7.8.1 module stop mode setting ..................................................................................154 7.8.2 on-chip ram......................................................................................................154 7.8.3 dtce bit setting .................................................................................................154 7.8.4 setting required on entering subactive mode or watch mode ..........................154 7.8.5 dtc activation by interrupt sources of sci, iic, lpc, or a/d converter ........154 section 8 i/o ports ............................................................................................ 155 8.1 overview .................................................................................................................... .......155 8.2 port 1 ...................................................................................................................... ...........160 8.2.1 port 1 data direction register (p1ddr) .............................................................160 rev. 2.0, 08/02, page xi of xxxviii 8.2.2 port 1 data register (p1dr) ................................................................................161 8.2.3 port 1 pull-up mos control register (p1pcr) ..................................................161 8.2.4 pin functions........................................................................................................162 8.2.5 port 1 input pull-up mos....................................................................................162 8.3 port 2 ...................................................................................................................... ...........163 8.3.1 port 2 data direction register (p2ddr) .............................................................163 8.3.2 port 2 data register (p2dr) ................................................................................164 8.3.3 port 2 pull-up mos control register (p2pcr) ..................................................164 8.3.4 pin functions........................................................................................................165 8.3.5 port 2 input pull-up mos....................................................................................166 8.4 port 3 ...................................................................................................................... ...........167 8.4.1 port 3 data direction register (p3ddr) .............................................................167 8.4.2 port 3 data register (p3dr) ................................................................................167 8.4.3 port 3 pull-up mos control register (p3pcr) ..................................................168 8.4.4 pin functions........................................................................................................168 8.4.5 port 3 input pull-up mos....................................................................................169 8.5 port 4 ...................................................................................................................... ...........169 8.5.1 port 4 data direction register (p4ddr) .............................................................170 8.5.2 port 4 data register (p4dr) ................................................................................170 8.5.3 pin functions........................................................................................................171 8.6 port 5 ...................................................................................................................... ...........174 8.6.1 port 5 data direction register (p5ddr) .............................................................174 8.6.2 port 5 data register (p5dr) ................................................................................175 8.6.3 pin functions........................................................................................................175 8.7 port 6 ...................................................................................................................... ...........176 8.7.1 port 6 data direction register (p6ddr) .............................................................176 8.7.2 port 6 data register (p6dr) ................................................................................177 8.7.3 port 6 pull-up mos control register (kmpcr) ................................................177 8.7.4 pin functions........................................................................................................177 8.7.5 port 6 input pull-up mos....................................................................................180 8.8 port 7 ...................................................................................................................... ...........180 8.8.1 port 7 input data register (p7pin)......................................................................181 8.8.2 pin functions........................................................................................................181 8.9 port 8 ...................................................................................................................... ...........182 8.9.1 port 8 data direction register (p8ddr) .............................................................182 8.9.2 port 8 data register (p8dr) ................................................................................183 8.9.3 pin functions........................................................................................................183 8.10 port 9 ..................................................................................................................... ............186 8.10.1 port 9 data direction register (p9ddr) .............................................................187 8.10.2 port 9 data register (p9dr) ................................................................................188 8.10.3 pin functions........................................................................................................188 8.11 port a ..................................................................................................................... ...........191 8.11.1 port a data direction register (paddr) ...........................................................192 rev. 2.0, 08/02, page xii of xxxviii 8.11.2 port a output data register (paodr) ...............................................................192 8.11.3 port a input data register (papin)....................................................................193 8.11.4 pin functions........................................................................................................193 8.11.5 port a input pull-up mos...................................................................................197 8.12 port b ..................................................................................................................... ...........198 8.12.1 port b data direction register (pbddr)............................................................198 8.12.2 port b output data register (pbodr)................................................................199 8.12.3 port b input data register (pbpin) ....................................................................199 8.12.4 pin functions........................................................................................................200 8.12.5 port b input pull-up mos...................................................................................202 8.13 additional overview for h8s/2160b and h8s/2161b .....................................................203 8.14 ports c, d ................................................................................................................. .........204 8.14.1 port c and port d data direction registers (pcddr, pdddr).........................205 8.14.2 port c and port d output data registers (pcodr, pdodr).............................206 8.14.3 port c and port d input data registers (pcpin, pdpin) ...................................207 8.14.4 port c and port d nch-od control register (pcnocr, pdnocr)..................208 8.14.5 pin functions........................................................................................................208 8.14.6 input pull-up mos in ports c and d...................................................................209 8.15 ports e, f................................................................................................................. ..........209 8.15.1 port e and port f data direction registers (peddr, pfddr) ..........................210 8.15.2 port e and port f output data registers (peodr, pfodr) ..............................211 8.15.3 port e and port f input data registers (pepin, pfpin) .....................................212 8.15.4 port e and port f nch-od control register (penocr, pfnocr) ...................213 8.15.5 pin functions........................................................................................................213 8.15.6 input pull-up mos in ports e and f ...................................................................214 8.16 port g ..................................................................................................................... ...........214 8.16.1 port g data direction register (pgddr) ...........................................................214 8.16.2 port g output data register (pgodr) ...............................................................215 8.16.3 port g input data register (pgpin)....................................................................215 8.16.4 port g nch-od control register (pgnocr) .....................................................216 8.16.5 pin functions........................................................................................................216 section 9 8-bit pwm timer (pwm) ................................................................ 217 9.1 features .................................................................................................................... .........217 9.2 input/output pin............................................................................................................ ....219 9.3 register descriptions ....................................................................................................... .219 9.3.1 pwm register select (pwsl) .............................................................................220 9.3.2 pwm data registers (pwdr0 to pwdr15) ......................................................222 9.3.3 pwm data polarity registers a and b (pwdpra, pwdprb)..........................222 9.3.4 pwm output enable registers a and b (pwoera, pwoerb) .......................223 9.3.5 peripheral clock select register (pcsr).............................................................224 9.4 operation................................................................................................................... ........225 9.5 usage note .................................................................................................................. ......226 rev. 2.0, 08/02, page xiii of xxxviii 9.5.1 module stop mode setting...................................................................................226 section 10 14-bit pwm timer (pwmx)..........................................................227 10.1 features ................................................................................................................... ..........227 10.2 input/output pins .......................................................................................................... ....228 10.3 register descriptions...................................................................................................... ...228 10.3.1 pwm (d/a) counters h and l (dacnth, dacntl) ......................................228 10.3.2 pwm (d/a) data registers a and b (dadra, dadrb)..................................230 10.3.3 pwm (d/a) control register (dacr)................................................................232 10.4 bus master interface ....................................................................................................... ..233 10.5 operation.................................................................................................................. .........234 10.6 usage note ................................................................................................................. .......240 10.6.1 module stop mode setting...................................................................................240 section 11 16-bit free-running timer (frt) ..................................................241 11.1 features ................................................................................................................... ..........241 11.2 input/output pins .......................................................................................................... ....243 11.3 register descriptions...................................................................................................... ...243 11.3.1 free-running counter (frc)...............................................................................244 11.3.2 output compare registers a and b (ocra, ocrb)..........................................244 11.3.3 input capture registers a to d (icra to icrd).................................................244 11.3.4 output compare registers ar and af (ocrar, ocraf)................................245 11.3.5 output compare register dm (ocrdm) ...........................................................245 11.3.6 timer interrupt enable register (tier) ..............................................................246 11.3.7 timer control/status register (tcsr) ................................................................247 11.3.8 timer control register (tcr) .............................................................................250 11.3.9 timer output compare control register (tocr)...............................................251 11.4 operation.................................................................................................................. .........253 11.4.1 pulse output .........................................................................................................253 11.5 operation timing ........................................................................................................... ...253 11.5.1 frc increment timing ........................................................................................253 11.5.2 output compare output timing ..........................................................................254 11.5.3 frc clear timing................................................................................................255 11.5.4 input capture input timing..................................................................................255 11.5.5 buffered input capture input timing...................................................................256 11.5.6 timing of input capture flag (icf) setting.........................................................257 11.5.7 timing of output compare flag (ocf) setting ...................................................258 11.5.8 timing of frc overflow flag setting.................................................................258 11.5.9 automatic addition timing .................................................................................259 11.5.10 mask signal generation timing ..........................................................................259 11.6 interrupt sources .......................................................................................................... .....260 11.7 usage notes................................................................................................................ .......261 11.7.1 conflict between frc write and clear................................................................261 rev. 2.0, 08/02, page xiv of xxxviii 11.7.2 conflict between frc write and increment ........................................................262 11.7.3 conflict between ocr write and compare-match .............................................262 11.7.4 switching of internal clock and frc operation .................................................264 11.7.5 module stop mode setting ..................................................................................266 section 12 8-bit timer (tmr) ......................................................................... 267 12.1 features ................................................................................................................... ..........267 12.2 input/output pins .......................................................................................................... ....270 12.3 register descriptions ...................................................................................................... ..270 12.3.1 timer counter (tcnt) ........................................................................................271 12.3.2 time constant register a (tcora) ...................................................................271 12.3.3 time constant register b (tcorb) ...................................................................271 12.3.4 timer control register (tcr) .............................................................................272 12.3.5 timer control/status register (tcsr) ................................................................275 12.3.6 input capture register (ticr).............................................................................281 12.3.7 time constant register (tcorc) .......................................................................281 12.3.8 input capture registers r and f (ticrr, ticrf)..............................................281 12.3.9 timer input select register (tisr) .....................................................................282 12.4 operation.................................................................................................................. .........282 12.4.1 pulse output .........................................................................................................282 12.5 operation timing ........................................................................................................... ...283 12.5.1 tcnt count timing............................................................................................283 12.5.2 timing of cmfa and cmfb setting at compare-match ...................................284 12.5.3 timing of timer output at compare-match ........................................................284 12.5.4 timing of counter clear at compare-match .......................................................285 12.5.5 tcnt external reset timing ..............................................................................285 12.5.6 timing of overflow flag (ovf) setting..............................................................286 12.6 operation with cascaded connection ...............................................................................286 12.6.1 16-bit count mode ..............................................................................................286 12.6.2 compare-match count mode...............................................................................287 12.7 input capture operation.................................................................................................... 287 12.8 interrupt sources .......................................................................................................... .....290 12.9 usage notes................................................................................................................ .......291 12.9.1 conflict between tcnt write and clear.............................................................291 12.9.2 conflict between tcnt write and increment .....................................................292 12.9.3 conflict between tcor write and compare-match ...........................................293 12.9.4 conflict between compare-matches a and b......................................................294 12.9.5 switching of internal clocks and tcnt operation.............................................294 12.9.6 mode setting with cascaded connection ............................................................296 12.9.7 module stop mode setting ..................................................................................296 section 13 timer connection............................................................................ 297 13.1 features ................................................................................................................... ..........297 rev. 2.0, 08/02, page xv of xxxviii 13.2 input/output pins .......................................................................................................... ....299 13.3 register descriptions...................................................................................................... ...299 13.3.1 timer connection register i (tconri)..............................................................300 13.3.2 timer connection register o (tconro)...........................................................303 13.3.3 timer connection register s (tconrs) ............................................................305 13.3.4 edge sense register (sedgr) ............................................................................307 13.4 operation.................................................................................................................. .........309 13.4.1 pwm decoding (pdc signal generation)...........................................................309 13.4.2 clamp waveform generation (cl1/cl2/cl3 signal generation)......................310 13.4.3 measurement of 8-bit timer divided waveform period.....................................312 13.4.4 2fh modification of ihi signal............................................................................314 13.4.5 ivi signal fall modification and ihi synchronization........................................316 13.4.6 internal synchronization signal generation (ihg/ivg/cl4 signal generation) ......................................................................317 13.4.7 hsynco output .................................................................................................320 13.4.8 vsynco output .................................................................................................321 13.4.9 cblank output .................................................................................................322 13.5 usage note ................................................................................................................. .......323 13.5.1 module stop mode setting...................................................................................323 section 14 watchdog timer (wdt) .................................................................325 14.1 features ................................................................................................................... ..........325 14.2 input/output pins .......................................................................................................... ....327 14.3 register descriptions...................................................................................................... ...327 14.3.1 timer counter (tcnt) ........................................................................................327 14.3.2 timer control/status register (tcsr) ................................................................328 14.4 operation.................................................................................................................. .........332 14.4.1 watchdog timer mode ........................................................................................332 14.4.2 interval timer mode ............................................................................................334 14.4.3 5(62 signal output timing................................................................................335 14.5 interrupt sources .......................................................................................................... .....335 14.6 usage notes................................................................................................................ .......336 14.6.1 notes on register access .....................................................................................336 14.6.2 conflict between timer counter (tcnt) write and increment ..........................337 14.6.3 changing values of cks2 to cks0 bits .............................................................337 14.6.4 switching between watchdog timer mode and interval timer mode ................337 14.6.5 system reset by 5(62 signal .............................................................................338 14.6.6 counter values during transitions between high-speed, sub-active, and watch modes .................................................................................................33 8 section 15 serial communication interface (sci and irda)............................339 15.1 features ................................................................................................................... ..........339 15.2 input/output pins .......................................................................................................... ....341 rev. 2.0, 08/02, page xvi of xxxviii 15.3 register descriptions ...................................................................................................... ..341 15.3.1 receive shift register (rsr)...............................................................................342 15.3.2 receive data register (rdr) ..............................................................................342 15.3.3 transmit data register (tdr) .............................................................................342 15.3.4 transmit shift register (tsr) .............................................................................342 15.3.5 serial mode register (smr)................................................................................343 15.3.6 serial control register (scr)..............................................................................345 15.3.7 serial status register (ssr).................................................................................347 15.3.8 serial interface mode register (scmr) ..............................................................349 15.3.9 bit rate register (brr).......................................................................................350 15.3.10 keyboard comparator control register (kbcomp) ..........................................356 15.4 operation in asynchronous mode.....................................................................................357 15.4.1 data transfer format ...........................................................................................357 15.4.2 receive data sampling timing and reception margin in asynchronous mode ........................................................................................359 15.4.3 clock .................................................................................................................... 360 15.4.4 sci initialization (asynchronous mode) .............................................................361 15.4.5 data transmission (asynchronous mode)...........................................................362 15.4.6 serial data reception (asynchronous mode)......................................................364 15.5 multiprocessor communication function.........................................................................368 15.5.1 multiprocessor serial data transmission ............................................................370 15.5.2 multiprocessor serial data reception..................................................................371 15.6 operation in clocked synchronous mode ........................................................................374 15.6.1 clock .................................................................................................................... 374 15.6.2 sci initialization (clocked synchronous mode) .................................................375 15.6.3 serial data transmission (clocked synchronous mode).....................................376 15.6.4 serial data reception (clocked synchronous mode)..........................................378 15.6.5 simultaneous serial data transmission and reception (clocked synchronous mode)..............................................................................380 15.7 irda operation ............................................................................................................. ....382 15.8 interrupt sources .......................................................................................................... .....385 15.9 usage notes................................................................................................................ .......386 15.9.1 module stop mode setting ..................................................................................386 15.9.2 break detection and processing...........................................................................386 15.9.3 mark state and break detection ..........................................................................386 15.9.4 receive error flags and transmit operations (clocked synchronous mode only) .....................................................................386 15.9.5 relation between writing to tdr and tdre flag .............................................386 15.9.6 restrictions on using dtc ..................................................................................387 15.9.7 sci operations during mode transitions.............................................................387 15.9.8 notes on switching from sck pins to port pins..................................................391 rev. 2.0, 08/02, page xvii of xxxviii section 16 i 2 c bus interface (iic) (optional) ...................................................393 16.1 features ................................................................................................................... ..........393 16.2 input/output pins .......................................................................................................... ....396 16.3 register descriptions...................................................................................................... ...397 16.3.1 i 2 c bus data register (icdr)..............................................................................397 16.3.2 slave address register (sar) .............................................................................398 16.3.3 second slave address register (sarx)..............................................................399 16.3.4 i 2 c bus mode register (icmr) ...........................................................................401 16.3.5 i 2 c bus control register (iccr) .........................................................................404 16.3.6 i 2 c bus status register (icsr) ............................................................................414 16.3.7 ddc switch register (ddcswr) ......................................................................418 16.3.8 i 2 c bus extended control register (icxr) .........................................................420 16.4 operation.................................................................................................................. .........424 16.4.1 i 2 c bus data format.............................................................................................424 16.4.2 initialization .........................................................................................................42 6 16.4.3 master transmit operation ..................................................................................426 16.4.4 master receive operation ....................................................................................430 16.4.5 slave receive operation ......................................................................................437 16.4.6 slave transmit operation.....................................................................................444 16.4.7 iric setting timing and scl control.................................................................446 16.4.8 automatic switching from formatless mode to i 2 c bus format.........................449 16.4.9 operation using dtc ..........................................................................................450 16.4.10 noise canceler .....................................................................................................451 16.4.11 initialization of internal state...............................................................................452 16.5 interrupt sources .......................................................................................................... .....454 16.6 usage notes................................................................................................................ .......454 16.6.1 module stop mode setting...................................................................................463 section 17 keyboard buffer controller.............................................................465 17.1 features ................................................................................................................... ..........465 17.2 input/output pins .......................................................................................................... ....466 17.3 register descriptions...................................................................................................... ...467 17.3.1 keyboard control register h (kbcrh)..............................................................467 17.3.2 keyboard control register l (kbcrl) ..............................................................469 17.3.3 keyboard data buffer register (kbbr)..............................................................470 17.4 operation.................................................................................................................. .........471 17.4.1 receive operation ................................................................................................471 17.4.2 transmit operation ..............................................................................................472 17.4.3 receive abort.......................................................................................................475 17.4.4 kclki and kdi read timing.............................................................................477 17.4.5 kclko and kdo write timing .........................................................................477 17.4.6 kbf setting timing and kclk control .............................................................478 17.4.7 receive timing ....................................................................................................479 rev. 2.0, 08/02, page xviii of xxxviii 17.4.8 kclk fall interrupt operation............................................................................480 17.5 usage notes................................................................................................................ .......481 17.5.1 kbioe setting and kclk falling edge detection.............................................481 17.5.2 module stop mode setting ..................................................................................481 section 18 host interface x-bus interface (xbs) ............................................ 483 18.1 features ................................................................................................................... ..........483 18.2 input/output pins .......................................................................................................... ....485 18.3 register descriptions ...................................................................................................... ..486 18.3.1 system control register 2 (syscr2) .................................................................486 18.3.2 host interface control register (hicr) host interface control register 2 (hicr2)........................................................................................................... .....488 18.3.3 input data register (idr) ....................................................................................491 18.3.4 output data register 1 (odr).............................................................................491 18.3.5 status register (str)...........................................................................................492 18.4 operation.................................................................................................................. .........493 18.4.1 host interface activation .....................................................................................493 18.4.2 control states .......................................................................................................495 18.4.3 a20 gate ..............................................................................................................495 18.4.4 host interface pin shutdown function ................................................................497 18.5 interrupt sources .......................................................................................................... .....499 18.5.1 ibf1, ibf2, ibf3, and ibf4 ................................................................................499 18.5.2 hirq11, hirq1, hirq12, hirq3, and hirq4 ................................................499 18.6 usage notes................................................................................................................ .......501 18.6.1 note on host interface .........................................................................................501 18.6.2 module stop mode setting ..................................................................................501 section 19 host interface lpc interface (lpc)................................................ 503 19.1 features ................................................................................................................... ..........503 19.2 input/output pins .......................................................................................................... ....505 19.3 register descriptions ...................................................................................................... ..506 19.3.1 host interface control registers 0 and 1 (hicr0, hicr1).................................507 19.3.2 host interface control registers 2 and 3 (hicr2, hicr3).................................514 19.3.3 lpc channel 3 address register (ladr3) ........................................................517 19.3.4 input data registers 1 to 3 (idr1 to idr3).........................................................518 19.3.5 output data registers 1 to 3 (odr1 to odr3)...................................................519 19.3.6 bidirectional data registers 0 to 15 (twr0 to twr15) ....................................529 19.3.7 status registers 1 to 3 (str1 to str3)...............................................................520 19.3.8 serirq control registers 0 and 1 (sirqcr0, sirqcr1)................................527 19.3.9 host interface select register (hisel) ...............................................................535 19.4 operation.................................................................................................................. .........536 19.4.1 host interface activation .....................................................................................536 19.4.2 lpc i/o cycles ....................................................................................................537 rev. 2.0, 08/02, page xix of xxxviii 19.4.3 a20 gate ..............................................................................................................539 19.4.4 host interface shutdown function (lpcpd).......................................................542 19.4.5 host interface serialized interrupt operation (serirq).....................................546 19.4.6 host interface clock start request (clkrun) ..................................................548 19.5 interrupt sources .......................................................................................................... .....548 19.5.1 ibfi1, ibfi2, ibfi3, and erri............................................................................548 19.5.2 smi, hirq1, hirq6, hirq9, hirq10, hirq11, and hirq12........................549 19.6 usage notes................................................................................................................ .......551 19.6.1 module stop mode setting...................................................................................551 19.6.2 notes on using host interface .............................................................................551 section 20 d/a converter .................................................................................553 20.1 features ................................................................................................................... ..........553 20.2 input/output pins .......................................................................................................... ....554 20.3 register descriptions...................................................................................................... ...554 20.3.1 d/a data registers 0 and 1 (dadr0, dadr1)..................................................554 20.3.2 d/a control register (dacr).............................................................................555 20.4 operation.................................................................................................................. .........556 20.5 usage note ................................................................................................................. .......557 20.5.1 module stop mode setting...................................................................................557 section 21 a/d converter .................................................................................559 21.1 features ................................................................................................................... ..........559 21.2 input/output pins .......................................................................................................... ....561 21.3 register descriptions...................................................................................................... ...562 21.3.1 a/d data registers a to d (addra to addrd)..............................................562 21.3.2 a/d control/status register (adcsr)................................................................563 21.3.3 a/d control register (adcr).............................................................................564 21.3.4 keyboard comparator control register (kbcomp) ..........................................565 21.4 operation.................................................................................................................. .........566 21.4.1 single mode .........................................................................................................566 21.4.2 scan mode............................................................................................................566 21.4.3 input sampling and a/d conversion time..........................................................568 21.4.4 external trigger input timing .............................................................................569 21.5 interrupt sources .......................................................................................................... .....569 21.6 a/d conversion accuracy definitions..............................................................................570 21.7 usage notes................................................................................................................ .......572 21.7.1 permissible signal source impedance..................................................................572 21.7.2 influences on absolute accuracy.........................................................................572 21.7.3 setting range of analog power supply and other pins ......................................573 21.7.4 notes on board design ........................................................................................573 21.7.5 notes on noise countermeasures.........................................................................573 21.7.6 module stop mode setting...................................................................................574 rev. 2.0, 08/02, page xx of xxxviii section 22 ram................................................................................................ 575 section 23 rom................................................................................................ 577 23.1 features ................................................................................................................... ..........577 23.2 mode transitions........................................................................................................... ....579 23.3 block configuration........................................................................................................ ..582 23.3.1 block configuration of 64-kbyte flash memory ................................................582 23.3.2 block configuration of 128-kbyte flash memory ..............................................583 23.3.3 block configuration of 256-kbyte flash memory ..............................................584 23.4 input/output pins .......................................................................................................... ....585 23.5 register descriptions ...................................................................................................... ..585 23.5.1 flash memory control register 1 (flmcr1).....................................................586 23.5.2 flash memory control register 2 (flmcr2).....................................................587 23.5.3 erase block registers 1 and 2 (ebr1, ebr2).....................................................587 23.6 operating modes ............................................................................................................ ...591 23.7 on-board programming modes ........................................................................................591 23.7.1 boot mode............................................................................................................592 23.7.2 user program mode .............................................................................................596 23.8 flash memory programming/erasing ...............................................................................598 23.8.1 program/program-verify .....................................................................................598 23.8.2 erase/erase-verify ...............................................................................................600 23.9 program/erase protection..................................................................................................6 02 23.9.1 hardware protection.............................................................................................602 23.9.2 software protection..............................................................................................602 23.9.3 error protection....................................................................................................602 23.10 interrupts during flash memory programming/erasing....................................................603 23.11 programmer mode........................................................................................................... ..604 23.12 usage notes............................................................................................................... ........604 section 24 masked rom .................................................................................. 607 section 25 clock pulse generator..................................................................... 609 25.1 oscillator ................................................................................................................. ..........610 25.1.1 connecting crystal resonator..............................................................................610 25.1.2 external clock input method...............................................................................611 25.2 duty correction circuit.................................................................................................... .613 25.3 medium-speed clock divider...........................................................................................613 25.4 bus master clock select circuit .......................................................................................614 25.5 subclock input circuit ..................................................................................................... .614 25.6 subclock waveform forming circuit ...............................................................................614 25.7 clock select circuit....................................................................................................... ....615 25.8 processing for x1 and x2 pins..........................................................................................615 25.9 usage notes................................................................................................................ .......616 rev. 2.0, 08/02, page xxi of xxxviii 25.9.1 note on resonator................................................................................................616 25.9.2 notes on board design ........................................................................................616 section 26 power-down modes ........................................................................617 26.1 register descriptions...................................................................................................... ...617 26.1.1 standby control register (sbycr).....................................................................618 26.1.2 low-power control register (lpwrcr)............................................................620 26.1.3 module stop control registers h and l (mstpcrh, mstpcrl) ....................621 26.2 mode transitions and lsi states.......................................................................................622 26.3 medium-speed mode ........................................................................................................62 5 26.4 sleep mode................................................................................................................. .......626 26.5 software standby mode ....................................................................................................62 7 26.6 hardware standby mode...................................................................................................628 26.7 watch mode ................................................................................................................. .....629 26.8 subsleep mode .............................................................................................................. ....630 26.9 subactive mode............................................................................................................. ....631 26.10 module stop mode.......................................................................................................... ..632 26.11 direct transitions ........................................................................................................ ......632 26.12 usage notes............................................................................................................... ........633 26.12.1 i/o port status ......................................................................................................633 26.12.2 current consumption when waiting for oscillation stabilization.......................633 26.12.3 dtc module stop mode......................................................................................633 section 27 list of registers...............................................................................635 27.1 register addresses (address order) .................................................................................635 27.2 register bits .............................................................................................................. ........646 27.3 register states in each operating mode...........................................................................655 27.4 register select conditions ................................................................................................6 64 section 28 electrical characteristics .................................................................677 28.1 electrical characteristics of h8s/2140b, h8s/2141b, h8s/2160b, and h8s/2161b ......677 28.1.1 absolute maximum ratings.................................................................................677 28.1.2 dc characteristics................................................................................................678 28.1.3 ac characteristics................................................................................................686 28.1.4 a/d conversion characteristics ...........................................................................694 28.1.5 d/a conversion characteristics ...........................................................................695 28.1.6 flash memory characteristics..............................................................................696 28.1.7 usage note ...........................................................................................................698 28.2 electrical characteristics of h8s/2145b and h8s/2148b ................................................699 28.2.1 absolute maximum ratings.................................................................................699 28.2.2 dc characteristics................................................................................................701 28.2.3 ac characteristics................................................................................................719 28.2.4 a/d conversion characteristics ...........................................................................730 rev. 2.0, 08/02, page xxii of xxxviii 28.2.5 d/a conversion characteristics...........................................................................732 28.2.6 flash memory characteristics..............................................................................733 28.2.7 usage notes .........................................................................................................735 28.3 timing chart ............................................................................................................... ......736 28.3.1 clock timing .......................................................................................................736 28.3.2 control signal timing..........................................................................................738 28.3.3 bus timing...........................................................................................................739 28.3.4 on-chip peripheral module timing ....................................................................743 appendix a i/o port states in each processing state ...................................... 751 appendix b product codes ............................................................................... 753 appendix c package dimensions ..................................................................... 754 main revisions and additions in this edition .................................................... 757 index ......................................................................................................... 785 rev. 2.0, 08/02, page xxiii of xxxviii figures section 1 overview figure 1.1 internal block diagram of h8s/2140b, h8s/2141b, h8s/2145b, and h8s/2148b ....3 figure 1.2 internal block diagram of h8s/2160b and h8s/2161b ...............................................4 figure 1.3 pin arrangement of h8s/2140b, h8s/2141b, h8s/2145b, and h8s/2148b ...............5 figure 1.4 pin arrangement of h8s/2160b and h8s/2161b .........................................................6 section 2 cpu figure 2.1 exception vector table (normal mode) .....................................................................31 figure 2.2 stack structure in normal mode .................................................................................31 figure 2.3 exception vector table (advanced mode) .................................................................32 figure 2.4 stack structure in advanced mode .............................................................................33 figure 2.5 memory map ........................................................................................................ .......33 figure 2.6 cpu internal registers ............................................................................................ ....34 figure 2.7 usage of general registers........................................................................................ ..35 figure 2.8 stack ............................................................................................................. ...............36 figure 2.9 general register data formats (1) ..............................................................................38 figure 2.9 general register data formats (2) ..............................................................................39 figure 2.10 memory data formats .............................................................................................. .40 figure 2.11 instruction formats (examples).................................................................................52 figure 2.12 branch address specification in memory indirect addressing mode ......................55 figure 2.13 state transitions ................................................................................................ ........59 section 3 mcu operating modes figure 3.1 address map for h8s/2140b and h8s/2160b (1) ......................................................71 figure 3.2 address map for h8s/2140b and h8s/2160b (2) ......................................................72 figure 3.3 address map for h8s/2141b and h8s/2161b (1) ......................................................73 figure 3.4 address map for h8s/2141b and h8s/2161b (2) ......................................................74 figure 3.5 address map for h8s/2145bv (1) ..............................................................................75 figure 3.6 address map for h8s/2145bv (2) ..............................................................................76 figure 3.7 address map for h8s/2148b (1).................................................................................77 section 4 exception handling figure 4.1 reset sequence (mode 3) ........................................................................................... .81 figure 4.2 stack status after exception handling ........................................................................83 figure 4.3 operation when sp value is odd ................................................................................84 section 5 interrupt controller figure 5.1 block diagram of interrupt controller ........................................................................86 figure 5.2 relationship between interrupts irq7 and irq6, interrupts kin15 to kin0, interrupts wue7 to wue0, and registers kmimr, kmimra, and wuemrb ......94 figure 5.3 block diagram of interrupts irq7 to irq0 ................................................................95 figure 5.4 flowchart of procedure up to interrupt acceptance in interrupt control mode 0.....100 rev. 2.0, 08/02, page xxiv of xxxviii figure 5.5 state transition in interrupt control mode 1.............................................................101 figure 5.6 flowchart of procedure up to interrupt acceptance in interrupt control mode 1 ...103 figure 5.7 interrupt exception handling ....................................................................................10 4 figure 5.8 dtc and interrupt controller ....................................................................................10 6 figure 5.9 address break block diagram ..................................................................................108 figure 5.10 address break timing example..............................................................................110 figure 5.11 conflict between interrupt generation and disabling .............................................111 section 6 bus controller figure 6.1 block diagram of bus controller ..............................................................................113 figure 6.2 ,26 signal output timing.........................................................................................119 figure 6.3 access sizes and data alignment control (8-bit access space)..............................120 figure 6.4 access sizes and data alignment control (16-bit access space) ............................121 figure 6.5 bus timing for 8-bit, 2-state access space..............................................................122 figure 6.6 bus timing for 8-bit, 3-state access space..............................................................123 figure 6.7 bus timing for 16-bit, 2-state access space (even byte access) ...........................124 figure 6.8 bus timing for 16-bit, 2-state access space (odd byte access) ............................125 figure 6.9 bus timing for 16-bit, 2-state access space (word access)...................................126 figure 6.10 bus timing for 16-bit, 3-state access space (even byte access) .........................127 figure 6.11 bus timing for 16-bit, 3-state access space (odd byte access) ..........................128 figure 6.12 bus timing for 16-bit, 3-state access space (word access).................................129 figure 6.13 example of wait state insertion timing (pin wait mode) .....................................131 figure 6.14 access timing example in burst rom space (ast = brsts1 = 1) ....................132 figure 6.15 access timing example in burst rom space (ast = brsts1 = 0) ....................132 figure 6.16 examples of idle cycle operation...........................................................................133 section 7 data transfer controller (dtc) figure 7.1 block diagram of dtc.............................................................................................. 136 figure 7.2 block diagram of dtc activation source control...................................................141 figure 7.3 dtc register information location in address space .............................................142 figure 7.4 dtc operation flowchart .........................................................................................14 4 figure 7.5 memory mapping in normal mode...........................................................................145 figure 7.6 memory mapping in repeat mode............................................................................146 figure 7.7 memory mapping in block transfer mode...............................................................147 figure 7.8 chain transfer operation .......................................................................................... 148 figure 7.9 dtc operation timing (example in normal mode or repeat mode)......................149 figure 7.10 dtc operation timing (example of block transfer mode, with block size of 2).....................................149 figure 7.11 dtc operation timing (example of chain transfer).............................................149 section 9 8-bit pwm timer (pwm) figure 9.1 block diagram of pwm timer .................................................................................218 figure 9.2 example of additional pulse timing (when upper 4 bits of pwdr = 1000) ..........226 rev. 2.0, 08/02, page xxv of xxxviii section 10 14-bit pwm timer (pwmx) figure 10.1 pwm (d/a) block diagram....................................................................................227 figure 10.2 pwm d/a operation ...............................................................................................2 34 figure 10.3 output waveform (os = 0, dadr corresponds to t l ) ...........................................236 figure 10.4 output waveform (os = 1, dadr corresponds to t h )...........................................237 figure 10.5 d/a data register configuration when cfs = 1 ....................................................237 figure 10.6 output waveform when dadr = h0207 (os = 1) ...............................................238 section 11 16-bit free-running timer (frt) figure 11.1 block diagram of 16-bit free-running timer........................................................242 figure 11.2 example of pulse output .........................................................................................2 53 figure 11.3 increment timing with internal clock source ........................................................253 figure 11.4 increment timing with external clock source .......................................................254 figure 11.5 timing of output compare a output......................................................................254 figure 11.6 clearing of frc by compare-match a signal........................................................255 figure 11.7 input capture input signal timing (usual case) ....................................................255 figure 11.8 input capture input signal timing (when icra to icrd are read) .....................256 figure 11.9 buffered input capture timing ...............................................................................256 figure 11.10 buffered input capture timing (bufea = 1).......................................................257 figure 11.11 timing of input capture flag (icfa, icfb, icfc, or icfd) setting ..................257 figure 11.12 timing of output compare flag (ocfa or ocfb) setting .................................258 figure 11.13 timing of overflow flag (ovf) setting ...............................................................258 figure 11.14 ocra automatic addition timing.......................................................................259 figure 11.15 timing of input capture mask signal setting .......................................................259 figure 11.16 timing of input capture mask signal clearing.....................................................260 figure 11.17 frc write-clear conflict......................................................................................26 1 figure 11.18 frc write-increment conflict ..............................................................................262 figure 11.19 conflict between ocr write and compare-match (when automatic addition function is not used)...............................................263 figure 11.20 conflict between ocrar/ocraf write and compare-match (when automatic addition function is used)......................................................264 section 12 8-bit timer (tmr) figure 12.1 block diagram of 8-bit timers (tmr_0 and tmr_1)...........................................268 figure 12.2 block diagram of 8-bit timers (tmr_y and tmr_x).........................................269 figure 12.3 pulse output example ............................................................................................. 282 figure 12.4 count timing for internal clock input ....................................................................283 figure 12.5 count timing for external clock input (both edges).............................................283 figure 12.6 timing of cmf setting at compare-match.............................................................284 figure 12.7 timing of toggled timer output by compare-match a signal .............................284 figure 12.8 timing of counter clear by compare-match..........................................................285 figure 12.9 timing of counter clear by external reset input ...................................................285 figure 12.10 timing of ovf flag setting ..................................................................................286 figure 12.11 timing of input capture operation .......................................................................288 rev. 2.0, 08/02, page xxvi of xxxviii figure 12.12 timing of input capture signal (input capture signal is input during ticrr and ticrf read)..............................288 figure 12.13 input capture signal selection ..............................................................................289 figure 12.14 conflict between tcnt write and clear ..............................................................291 figure 12.15 conflict between tcnt write and increment.......................................................292 figure 12.16 conflict between tcor write and compare-match.............................................293 section 13 timer connection figure 13.1 block diagram of timer connection ......................................................................298 figure 13.2 timing chart for pwm decoding ...........................................................................310 figure 13.3 timing chart for clamp waveform generation (cl1 and cl2 signals)................311 figure 13.4 timing chart for clamp waveform generation (cl3 signal) ................................311 figure 13.5 timing chart for measurement of ivi signal and ihi signal divided waveform periods.................................................................................................. ..314 figure 13.6 2fh modification timing chart...............................................................................315 figure 13.7 fall modification and ihi synchronization timing chart.......................................317 figure 13.8 ivg signal/ihg signal/cl4 signal timing chart..................................................319 figure 13.9 cblank output waveform generation ................................................................322 section 14 watchdog timer (wdt) figure 14.1 block diagram of wdt ..........................................................................................326 figure 14.2 watchdog timer mode (rst/ 10, = 1) operation .................................................333 figure 14.3 interval timer mode operation ...............................................................................334 figure 14.4 ovf flag set timing .............................................................................................. 334 figure 14.5 output timing of 5(62 signal................................................................................335 figure 14.6 writing to tcnt and tcsr (wdt_0) ...................................................................336 figure 14.7 conflict between tcnt write and increment.........................................................337 figure 14.8 sample circuit for resetting system by 5(62 signal............................................338 section 15 serial communication interface (sci and irda) figure 15.1 block diagram of sci ............................................................................................. 340 figure 15.2 data format in asynchronous communication (example with 8-bit data, parity, two stop bits)...................................................357 figure 15.3 receive data sampling timing in asynchronous mode.........................................359 figure 15.4 relation between output clock and transmit data phase (asynchronous mode)..............................................................................................3 60 figure 15.5 sample sci initialization flowchart........................................................................361 figure 15.6 example of sci transmit operation in asynchronous mode (example with 8-bit data, parity, one stop bit) .....................................................362 figure 15.7 sample serial transmission flowchart....................................................................363 figure 15.8 example of sci receive operation in asynchronous mode (example with 8-bit data, parity, one stop bit) .....................................................364 figure 15.9 sample serial reception flowchart (1) ...................................................................366 figure 15.9 sample serial reception flowchart (2) ...................................................................367 rev. 2.0, 08/02, page xxvii of xxxviii figure 15.10 example of communication using multiprocessor format (transmission of data h'aa to receiving station a) ...........................................369 figure 15.11 sample multiprocessor serial transmission flowchart.........................................370 figure 15.12 example of sci receive operation (example with 8-bit data, multiprocessor bit, one stop bit)...............................371 figure 15.13 sample multiprocessor serial reception flowchart (1) ........................................372 figure 15.13 sample multiprocessor serial reception flowchart (2) ........................................373 figure 15.14 data format in clocked synchronous communication (lsb-first) .....................374 figure 15.15 sample sci initialization flowchart......................................................................375 figure 15.16 example of sci transmit operation in clocked synchronous mode ...................376 figure 15.17 sample serial transmission flowchart..................................................................377 figure 15.18 example of sci receive operation in clocked synchronous mode.....................378 figure 15.19 sample serial reception flowchart.......................................................................379 figure 15.20 sample flowchart of simultaneous serial transmission and reception...............381 figure 15.21 irda block diagram .............................................................................................3 82 figure 15.22 irda transmission and reception.........................................................................383 figure 15.23 example of transmission using dtc in clocked synchronous mode..................387 figure 15.24 sample flowchart for mode transition during transmission ...............................388 figure 15.25 pin states during transmission in asynchronous mode (internal clock).............389 figure 15.26 pin states during transmission in clocked synchronous mode (internal clock) ................................................................................................ ......389 figure 15.27 sample flowchart for mode transition during reception.....................................390 figure 15.28 switching from sck pins to port pins ..................................................................391 figure 15.29 prevention of low pulse output at switching from sck pins to port pins ..........391 section 16 i 2 c bus interface (iic) (optional) figure 16.1 block diagram of i 2 c bus interface ........................................................................395 figure 16.2 i 2 c bus interface connections (example: this lsi as master) ...............................396 figure 16.3 i 2 c bus data format (i 2 c bus format)....................................................................424 figure 16.4 i 2 c bus data format (formatless) (iic_0 only) .....................................................424 figure 16.5 i 2 c bus data format (serial format).......................................................................425 figure 16.6 i 2 c bus timing ........................................................................................................425 figure 16.7 sample flowchart for iic initialization ...................................................................426 figure 16.8 sample flowchart for operations in master transmit mode ..................................427 figure 16.9 example of operation timing in master transmit mode (mls = wait = 0).......429 figure 16.10 example of stop condition issuance operation timing in master transmit mode (mls = wait = 0) .....................................................429 figure 16.11 sample flowchart for operations in master receive mode (hnds = 1) .............430 figure 16.12 example of operation timing in master receive mode (mls = wait = 0, hnds = 1) .............................................................................432 figure 16.13 example of stop condition issuance operation timing in master receive mode (mls = wait = 0, hnds = 1)....................................432 rev. 2.0, 08/02, page xxviii of xxxviii figure 16.14 sample flowchart for operations in master receive mode (receiving multiple bytes) (wait = 1) ..................................................................433 figure 16.15 sample flowchart for operations in master receive mode (receiving a single byte) (wait = 1).....................................................................434 figure 16.16 example of master receive mode operation timing (mls = ackb = 0, wait = 1).............................................................................436 figure 16.17 example of stop condition issuance timing in master receive mode (mls = ackb = 0, wait = 1).............................................................................437 figure 16.18 sample flowchart for operations in slave receive mode (hnds = 1)................438 figure 16.19 example of slave receive mode operation timing (1) (mls = 0, hnds= 1)....440 figure 16.20 example of slave receive mode operation timing (2) (mls = 0, hnds= 1)...440 figure 16.21 sample flowchart for operations in slave receive mode (hnds = 0)................441 figure 16.22 example of slave receive mode operation timing (1) (mls = ackb = 0).......443 figure 16.23 example of slave receive mode operation timing (2) (mls = ackb = 0).......443 figure 16.24 sample flowchart for slave transmit mode .........................................................444 figure 16.25 example of slave transmit mode operation timing (mls = 0)..........................446 figure 16.26 iric setting timing and scl control (1).............................................................447 figure 16.27 iric setting timing and scl control (2).............................................................448 figure 16.28 iric setting timing and scl control (3).............................................................449 figure 16.29 block diagram of noise canceler .........................................................................452 figure 16.30 notes on reading master receive data ................................................................458 figure 16.31 flowchart for start condition issuance instruction for retransmission and timing ...................................................................................................... .......459 figure 16.32 stop condition issuance timing............................................................................460 figure 16.33 iric flag clearing timing when wait = 1........................................................460 figure 16.34 icdr read and iccr access timing in slave transmit mode ...........................461 figure 16.35 trs bit set timing in slave mode .......................................................................462 section 17 keyboard buffer controller figure 17.1 block diagram of keyboard buffer controller .......................................................465 figure 17.2 keyboard buffer controller connection..................................................................466 figure 17.3 sample receive processing flowchart ....................................................................471 figure 17.4 receive timing................................................................................................... .....472 figure 17.5 (1) sample transmit processing flowchart .............................................................473 figure 17.5 (2) sample transmit processing flowchart .............................................................474 figure 17.6 transmit timing .................................................................................................. ....474 figure 17.7 (1) sample receive abort processing flowchart ....................................................475 figure 17.7 (2) sample receive abort processing flowchart ....................................................476 figure 17.8 receive abort and transmit start (transmission/reception switchover) timing..476 figure 17.9 kclki and kdi read timing ................................................................................477 figure 17.10 kclko and kdo write timing ..........................................................................477 figure 17.11 kbf setting and kclk automatic i/o inhibit generation timing......................478 figure 17.12 receive counter and kbbr data load timing....................................................479 rev. 2.0, 08/02, page xxix of xxxviii figure 17.13 example of kclk input fall interrupt operation.................................................480 figure 17.14 kbioe setting and kclk falling edge detection timing..................................481 section 18 host interface x-bus interface (xbs) figure 18.1 block diagram of xbs............................................................................................4 84 figure 18.2 ga20 output ...................................................................................................... .....496 figure 18.3 hirq output flowchart (example of channels 1 and 2)........................................500 section 19 host interface lpc interface (lpc) figure 19.1 block diagram of lpc ............................................................................................5 04 figure 19.2 typical /)5$0( timing .......................................................................................538 figure 19.3 abort mechanism .................................................................................................. ..538 figure 19.4 ga20 output ...................................................................................................... .....540 figure 19.5 power-down state termination timing..................................................................545 figure 19.6 serirq timing .................................................................................................... ..546 figure 19.7 clock start request timing.....................................................................................54 8 figure 19.8 hirq flowchart (example of channel 1) ...............................................................551 section 20 d/a converter figure 20.1 block diagram of d/a converter............................................................................553 figure 20.2 d/a converter operation example .........................................................................556 section 21 a/d converter figure 21.1 block diagram of a/d converter............................................................................560 figure 21.2 example of a/d converter operation (scan mode, channels an0 to an2 selected) ........................................................567 figure 21.3 a/d conversion timing ..........................................................................................56 8 figure 21.4 external trigger input timing.................................................................................569 figure 21.5 a/d conversion accuracy definitions ....................................................................571 figure 21.6 a/d conversion accuracy definitions ....................................................................571 figure 21.7 example of analog input circuit.............................................................................572 figure 21.8 example of analog input protection circuit ...........................................................574 figure 21.9 equivalent circuit of analog input pin ...................................................................574 section 23 rom figure 23.1 block diagram of flash memory ............................................................................578 figure 23.2 flash memory state transitions ..............................................................................579 figure 23.3 boot mode ........................................................................................................ .......580 figure 23.4 user program mode (example) ...............................................................................581 figure 23.5 64-kbyte flash memory block configuration ........................................................582 figure 23.6 128-kbyte flash memory block configuration ......................................................583 figure 23.7 256-kbyte flash memory block configuration ......................................................584 figure 23.8 on-chip ram area in boot mode .........................................................................595 figure 23.9 id code area..................................................................................................... ......596 figure 23.10 programming/erasing flowchart example in user program mode ......................597 figure 23.11 program/program-verify flowchart......................................................................599 rev. 2.0, 08/02, page xxx of xxxviii figure 23.12 erase/erase-verify flowchart................................................................................601 figure 23.13 memory map in programmer mode ......................................................................604 section 24 masked rom figure 24.1 block diagram of 128-kbyte masked rom (hd6432161bv) ..............................607 figure 24.2 block diagram of 64-kbyte masked rom (hd6432160bv) ................................607 section 25 clock pulse generator figure 25.1 block diagram of clock pulse generator................................................................609 figure 25.2 typical connection to crystal resonator ................................................................610 figure 25.3 equivalent circuit of crystal resonator ..................................................................610 figure 25.4 example of external clock input ............................................................................611 figure 25.5 external clock input timing ...................................................................................612 figure 25.6 timing of external clock output stabilization delay time ...................................613 figure 25.7 subclock input timing ............................................................................................ 614 figure 25.8 processing for x1 and x2 pins ................................................................................615 figure 25.9 note on board design of oscillator circuit section................................................616 section 26 power-down modes figure 26.1 mode transition diagram........................................................................................62 3 figure 26.2 medium-speed mode timing..................................................................................626 figure 26.3 application example in software standby mode....................................................628 figure 26.4 hardware standby mode timing.............................................................................629 section 28 electrical characteristics figure 28.1 darlington pair drive circuit (example).................................................................684 figure 28.2 led drive circuit (example)..................................................................................685 figure 28.3 output load circuit .............................................................................................. ...686 figure 28.4 connection of vcl capacitor .................................................................................698 figure 28.5 connection of vcl capacitor .................................................................................736 figure 28.6 system clock timing .............................................................................................. 736 figure 28.7 oscillation settling timing...................................................................................... 737 figure 28.8 oscillation setting timing (exiting software standby mode)................................737 figure 28.9 reset input timing ............................................................................................... ...738 figure 28.10 interrupt input timing .......................................................................................... .738 figure 28.11 basic bus timing (two-state access) ..................................................................739 figure 28.12 basic bus timing (three-state access) ................................................................740 figure 28.13 basic bus timing (three-state access with one wait state)...............................741 figure 28.14 burst rom access timing (two-state access) ...................................................742 figure 28.15 burst rom access timing (one-state access)....................................................742 figure 28.16 i/o port input/output timing ................................................................................743 figure 28.17 frt input/output timing......................................................................................743 figure 28.18 frt clock input timing .......................................................................................744 figure 28.19 8-bit timer output timing....................................................................................744 figure 28.20 8-bit timer clock input timing............................................................................744 rev. 2.0, 08/02, page xxxi of xxxviii figure 28.21 8-bit timer reset input timing ............................................................................744 figure 28.22 pwm, pwmx output timing...............................................................................745 figure 28.23 sck clock input timing.......................................................................................745 figure 28.24 sci input/output timing (synchronous mode) ....................................................745 figure 28.25 a/d converter external trigger input timing ......................................................745 figure 28.26 wdt output timing ( 5(62 )................................................................................746 figure 28.27 host interface (xbs) timing.................................................................................746 figure 28.28 keyboard buffer controller timing ......................................................................747 figure 28.29 i 2 c bus interface input/output timing..................................................................748 figure 28.30 host interface (lpc) timing .................................................................................748 figure 28.31 tester measurement condition..............................................................................749 appendix c package dimensions figure c.1 package dimensions (fp-100b) ...............................................................................754 figure c.2 package dimensions (tfp-100b).............................................................................755 figure c.3 package dimensions (tfp-144)................................................................................756 rev. 2.0, 08/02, page xxxii of xxxviii rev. 2.0, 08/02, page xxxiii of xxxviii tables section 1 overview table 1.1 pin functions of h8s/2141b, h8s/2140b, h8s/2145b, and h8s/2148b in each operating mode ............................................................................................. ..7 table 1.2 pin functions of h8s/2160b and h8s/2161b in each operating mode ....................12 table 1.3 pin functions......................................................................................................... ......18 section 2 cpu table 2.1 instruction classification............................................................................................ .41 table 2.2 operation notation.................................................................................................... ..42 table 2.3 data transfer instructions...........................................................................................4 3 table 2.4 arithmetic operations instructions (1)........................................................................44 table 2.4 arithmetic operations instructions (2)........................................................................45 table 2.5 logic operations instructions .....................................................................................46 table 2.6 shift instructions .................................................................................................... .....46 table 2.7 bit manipulation instructions (1) ................................................................................47 table 2.7 bit manipulation instructions (2) ................................................................................48 table 2.8 branch instructions ................................................................................................... ..49 table 2.9 system control instructions ........................................................................................50 table 2.10 block data transfer instructions ............................................................................51 table 2.11 addressing modes...................................................................................................52 table 2.12 absolute address access ranges ...........................................................................54 table 2.13 effective address calculation (1) ...........................................................................56 table 2.13 effective address calculation (2) ...........................................................................57 section 3 mcu operating modes table 3.1 mcu operating mode selection.................................................................................63 table 3.2 pin functions in each mode .......................................................................................70 section 4 exception handling table 4.1 exception types and priority......................................................................................79 table 4.2 exception handling vector table...............................................................................80 table 4.3 status of ccr after trap instruction exception handling..........................................83 section 5 interrupt controller table 5.1 pin configuration ..................................................................................................... ...87 table 5.2 correspondence between interrupt source and icr ...................................................88 table 5.3 interrupt sources, vector addresses, and interrupt priorities.....................................97 table 5.4 interrupt control modes..............................................................................................9 9 table 5.5 interrupt response times..........................................................................................105 table 5.6 number of states in interrupt handling routine execution status...........................105 section 6 bus controller table 6.1 pin configuration ..................................................................................................... .114 rev. 2.0, 08/02, page xxxiv of xxxviii table 6.2 bus specifications for basic bus interface ...............................................................118 table 6.3 address range for ,26 signal output ......................................................................119 table 6.4 data buses used and valid strobes ..........................................................................121 table 6.5 pin states in idle cycle .............................................................................................1 33 section 7 data transfer controller (dtc) table 7.1 interrupt sources, dtc vector addresses, and corresponding dtces...................143 table 7.2 register functions in normal mode .........................................................................145 table 7.3 register functions in repeat mode ..........................................................................146 table 7.4 register functions in block transfer mode .............................................................147 table 7.5 dtc execution status...............................................................................................150 table 7.6 number of states required for each execution status.............................................150 section 8 i/o ports table 8.1 port functions of h8s/2140b, h8s/2141b, h8s/2145b, and h8s/2148b ..............156 table 8.2 input pull-up mos states (port 1) ...........................................................................162 table 8.3 input pull-up mos states (port 2) ...........................................................................166 table 8.4 input pull-up mos states (port 3) ...........................................................................169 table 8.5 input pull-up mos states (port 6) ...........................................................................180 table 8.6 input pull-up mos states (port a) ..........................................................................197 table 8.7 input pull-up mos states (port b)...........................................................................203 table 8.8 h8s/2160b, h8s/2161b additional port functions.................................................204 table 8.9 input pull-up mos states (port c and port d).........................................................209 table 8.10 input pull-up mos states (port e and port f)......................................................214 section 9 8-bit pwm timer (pwm) table 9.1 pin configuration ..................................................................................................... .219 table 9.2 internal clock selection ............................................................................................22 1 table 9.3 resolution, pwm conversion period and carrier frequency when ? = 10 mhz.....222 table 9.4 duty cycle of basic pulse.........................................................................................225 table 9.5 position of pulses added to basic pulses..................................................................226 section 10 14-bit pwm timer (pwmx) table 10.1 pin configuration ..................................................................................................22 8 table 10.2 read and write access methods for 16-bit registers ..........................................234 table 10.3 settings and operation (examples when ? = 10 mhz) .........................................235 table 10.4 position of pulse to be added to basic pulse (cfs = 1) .......................................239 section 11 16-bit free-running timer (frt) table 11.1 pin configuration ..................................................................................................24 3 table 11.2 frt interrupt sources...........................................................................................260 table 11.3 switching of internal clock and frc operation ..................................................265 section 12 8-bit timer (tmr) table 12.1 pin configuration ..................................................................................................27 0 table 12.2 clock input to tcnt and count condition ..........................................................273 rev. 2.0, 08/02, page xxxv of xxxviii table 12.3 input capture signal selection..............................................................................289 table 12.4 interrupt sources of 8-bit timers tmr_0, tmr_1, tmr_y, and tmr_x........290 table 12.5 timer output priorities .........................................................................................294 table 12.6 switching of internal clocks and tcnt operation..............................................295 section 13 timer connection table 13.1 pin configuration ..................................................................................................29 9 table 13.2 synchronization signal connection enable ..........................................................302 table 13.3 registers accessible by tmr_x/tmr_y............................................................306 table 13.4 examples of tcr settings ....................................................................................309 table 13.5 examples of tcorb (pulse width threshold) settings ......................................309 table 13.6 examples of tcr and tcsr settings...................................................................313 table 13.7 examples of tcr, tcsr, tocr, and ocrdm settings ....................................315 table 13.8 examples of tcr, tcsr, and tcorb settings ..................................................316 table 13.9 examples of ocrar, ocraf, tcora, tcorb, tcr, and tcsr settings ....318 table 13.10 hsynco output modes ......................................................................................320 table 13.11 vsynco output modes ......................................................................................321 section 14 watchdog timer (wdt) table 14.1 pin configuration ..................................................................................................32 7 table 14.2 wdt interrupt source...........................................................................................335 section 15 serial communication interface (sci and irda) table 15.1 pin configuration ..................................................................................................34 1 table 15.2 relationships between n setting in brr and bit rate b .....................................350 table 15.3 brr settings for various bit rates (asynchronous mode) .................................351 table 15.4 maximum bit rate for each frequency (asynchronous mode)...........................354 table 15.5 maximum bit rate with external clock input (asynchronous mode).................354 table 15.6 brr settings for various bit rates (clocked synchronous mode) .....................355 table 15.7 maximum bit rate with external clock input (clocked synchronous mode).....355 table 15.8 serial transfer formats (asynchronous mode) ....................................................358 table 15.9 ssr status flags and receive data handling.......................................................365 table 15.10 ircks2 to ircks0 bit settings .............................................................................384 table 15.11 sci interrupt sources ............................................................................................385 section 16 i 2 c bus interface (iic) (optional) table 16.1 pin configuration ..................................................................................................39 6 table 16.2 communication format.........................................................................................400 table 16.3 i 2 c transfer rate ...................................................................................................403 table 16.4 flags and transfer states (master mode) .............................................................410 table 16.5 flags and transfer states (slave mode)................................................................412 table 16.6 i 2 c bus data format symbols...............................................................................425 table 16.7 examples of operation using dtc ......................................................................451 table 16.8 iic interrupt sources.............................................................................................454 table 16.9 i 2 c bus timing (scl and sda outputs)..............................................................455 rev. 2.0, 08/02, page xxxvi of xxxviii table 16.10 permissible scl rise time (t sr ) values ................................................................455 table 16.11 i 2 c bus timing (with maximum influence of t sr /t sf ) .............................................457 section 17 keyboard buffer controller table 17.1 pin configuration ..................................................................................................46 6 section 18 host interface x-bus interface (xbs) table 18.1 pin configuration ..................................................................................................48 5 table 18.2 set/clear timing for str flags............................................................................493 table 18.3 host interface channel selection and pin operation ............................................494 table 18.4 host interface operations from hif host, and slave operation...........................495 table 18.5 ga20 (p81) set/clear timing...............................................................................496 table 18.6 fast a20 gate output signal.................................................................................497 table 18.7 scope of hif pin shutdown..................................................................................498 table 18.8 input buffer full interrupts ...................................................................................499 table 18.9 hirq setting/clearing conditions .......................................................................500 section 19 host interface lpc interface (lpc) table 19.1 pin configuration ..................................................................................................50 5 table 19.2 register selection..................................................................................................5 18 table 19.3 ga20 (p81) set/clear timing...............................................................................539 table 19.4 fast a20 gate output signals ..............................................................................541 table 19.5 scope of host interface pin shutdown..................................................................543 table 19.6 scope of initialization in each host interface mode ............................................544 table 19.7 receive complete interrupts and error interrupt ..................................................548 table 19.8 hirq setting and clearing conditions.................................................................550 section 20 d/a converter table 20.1 pin configuration ..................................................................................................55 4 table 20.2 d/a channel enable..............................................................................................555 section 21 a/d converter table 21.1 pin configuration ..................................................................................................56 1 table 21.2 analog input channels and corresponding addr registers...............................562 table 21.3 a/d conversion time (single mode) ...................................................................569 section 23 rom table 23.1 differences between boot mode and user program mode...................................579 table 23.2 pin configuration ..................................................................................................58 5 table 23.3 operating modes and rom ..................................................................................591 table 23.4 on-board programming mode settings................................................................591 table 23.5 boot mode operation............................................................................................594 table 23.6 system clock frequencies for which automatic adjustment of lsi bit rate is possible.................................................................................................... ..........595 section 25 clock pulse generator table 25.1 damping resistance values..................................................................................610 rev. 2.0, 08/02, page xxxvii of xxxviii table 25.2 crystal resonator parameters ...............................................................................611 table 25.3 external clock input conditions...........................................................................612 table 25.4 external clock output stabilization delay time..................................................613 table 25.5 subclock input conditions ....................................................................................614 section 26 power-down modes table 26.1 operating frequency and wait time ....................................................................619 table 26.2 lsi internal states in each mode..........................................................................624 section 28 electrical characteristics table 28.1 absolute maximum ratings..................................................................................677 table 28.2 dc characteristics (1)...........................................................................................678 table 28.2 dc characteristics (2)...........................................................................................681 table 28.2 dc characteristics (3) when lpc function is used ............................................683 table 28.3 permissible output currents .................................................................................684 table 28.4 bus drive characteristics......................................................................................685 table 28.5 clock timing ........................................................................................................6 87 table 28.6 control signal timing...........................................................................................688 table 28.7 bus timing (1) (normal mode) ............................................................................689 table 28.7 bus timing (2) (advanced mode) ........................................................................690 table 28.8 timing of on-chip peripheral modules (1)..........................................................691 table 28.8 timing of on-chip peripheral modules (2)..........................................................692 table 28.9 keyboard buffer controller timing......................................................................693 table 28.10 i 2 c bus timing......................................................................................................693 table 28.11 lpc module timing .............................................................................................694 table 28.12 a/d conversion characteristics (an7 to an0 input: 134/266-state conversion) ..................................................694 table 28.13 a/d conversion characteristics (cin15 to cin0 input: 134/266-state conversion) ..............................................695 table 28.14 d/a conversion characteristics ............................................................................695 table 28.15 flash memory characteristics...............................................................................696 table 28.16 absolute maximum ratings..................................................................................699 table 28.17 dc characteristics (1)...........................................................................................701 table 28.17 dc characteristics (2)...........................................................................................703 table 28.17 dc characteristics (3)...........................................................................................705 table 28.17 dc characteristics (4)...........................................................................................708 table 28.17 dc characteristics (5)...........................................................................................710 table 28.17 dc characteristics (6)...........................................................................................713 table 28.17 dc characteristics (7) (3-v version of h8s/2145bv) when lpc function is used .................................................................................715 table 28.18 permissible output currents .................................................................................716 table 28.19 bus drive characteristics......................................................................................718 table 28.20 clock timing ........................................................................................................ 719 table 28.21 control signal timing...........................................................................................720 rev. 2.0, 08/02, page xxxviii of xxxviii table 28.22 bus timing (1) (normal mode) ............................................................................721 table 28.22 bus timing (2) (advanced mode) ........................................................................723 table 28.23 timing of on-chip peripheral modules (1)..........................................................725 table 28.23 timing of on-chip peripheral modules (2)..........................................................727 table 28.24 keyboard buffer controller timing......................................................................728 table 28.25 i 2 c bus timing......................................................................................................728 table 28.26 lpc module timing (for h8s/2145b only) .......................................................729 table 28.27 a/d conversion characteristics (an7 to an0 input: 134/266-state conversion) ..................................................730 table 28.28 a/d conversion characteristics (cin15 to cin0 input: 134/266-state conversion) ..............................................731 table 28.29 d/a conversion characteristics ............................................................................732 table 28.30 flash memory characteristics (operation range at programming/erasing) ........733 appendix a table a.1 i/o port states in each processing state ...............................................................751 rev. 2.0, 08/02, page 1 of 788 section 1 overview 1.1 features high-speed h8s/2000 central processing unit with an internal 16-bit architecture upward-compatible with h8/300 and h8/300h cpus on an object level sixteen 16-bit general registers 65 basic instructions various peripheral functions data transfer controller (dtc) 8-bit pwm timer (pwm) 14-bit pwm timer (pwmx) 16-bit free-running timer (frt) 8-bit timer (tmr) timer connection watchdog timer (wdt) asynchronous or clocked synchronous serial communication interface (sci,irda) i 2 c bus interface (iic) keyboard buffer controller host interface x-bus interface (xbs) host interface lpc interface (lpc) 8-bit d/a converter 10-bit a/d converter clock pulse generator rev. 2.0, 08/02, page 2 of 788 on-chip memory rom model rom ram remarks f-ztat version hd64f2161bv * 128 kbytes 4 kbytes hd64f2160bv * 64 kbytes 4 kbytes hd64f2141bv * 128 kbytes 4 kbytes hd64f2140bv * 64 kbytes 4 kbytes hd64f2145bv * 256 kbytes 8 kbytes under development hd64f2148bv * 128 kbytes 4 kbytes hd64f2148b 128 kbytes 4 kbytes hd6432161bv * 128 kbytes 4 kbytes hd6432160bv * 64 kbytes 4 kbytes hd6432161bvw * 128 kbytes 4 kbytes masked rom version hd6432160bvw * 64 kbytes 4 kbytes under development note: * 3-v version product general i/o ports i/o pins: 74 (h8s/2140b, h8s/2141b, h8s/2145b, and h8s/2148b) i/o pins: 114 (h8s/2160b and h8s/2161b) input-only pins: 8 supports various power-down states compact package product package code body size pin pitch h8s/2161b, h8s/2160b tqfp-144 tfp-144 18.0 18.0 mm 0.4 mm h8s/2141b, h8s/2140b h8s/2145b, h8s/2148b qfp-100b tqfp-100b fp-100b tfp-100b 16.0 16.0 mm 0.5 mm rev. 2.0, 08/02, page 3 of 788 1.2 block diagram h8s/2000 cpu dtc interrup controller wdt 2 channels rom (flash memory) ram 8-bit pwm 16-bit frt 8-bit timer 4 channels timer connection 14-bit pwm host interfaces (lpc * , xbs) 10-bit a/d converter 8-bit d/a converter sci 3 channels (irda 1 channel) iic 2 channels p17/a7/pw7 p16/a6/pw6 p15/a5/pw5 p14/a4/pw4 p13/a3/pw3 p12/a2/pw2 p11/a1/pw1 p10/a0/pw0 p27/a15/pw15/cblank p26/a14/pw14 p25/a13/pw13 p24/a12/pw12 p23/a11/pw11 p22/a10/pw10 p21/a9/pw9 p20/a8/pw8 pa7/a23/ /cin15/ps2cd pa6/a22/ /cin14/ps2cc pa5/a21/ /cin13/ps2bd pa4/a20/ /cin12/ps2bc pa3/a19/ /cin11/ps2ad pa2/a18/ /cin10/ps2ac pa1/a17/ /cin9 pa0/a16/ /cin8 p37/d15/hdb7/serirq * p36/d14/hdb6/lclk * p35/d13/hdb5/ * p34/d12/hdb4/ * p33/d11/hdb3/lad3 * p32/d10/hdb2/lad2 * p31/d9/hdb1/lad1 * p30/d8/hdb0/lad0 * pb7/d7/ * pb6/d6/ * pb5/d5/ * pb4/d4/ * pb3/d3/ * / pb2/d2/ * / pb1/d1/ * /hirq4/lsci * pb0/d0/ * /hirq3/ * p97/ /sda0 p96/?/excl p95/ / / p94/ / p93/ / p92/ p91/ p90/ / / / p67/tmox/cin7/ / p66/ftob/cin6/ / p65/ftid/cin5/ p64/ftic/cin4/ /clampo p63/ftib/cin3/ /vfbacki p62/ftia/cin2/ /vsynci/tmiy p61/ftoa/cin1/ /vsynco p60/ftci/cin0/ /hfbacki/tmix p47/pwx1 p46/pwx0 p45/tmri1/hirq12/csynci p44/tmo1/hirq1/hsynco p43/tmci1/hirq11/hsynci p42/tmri0/sck2/sda1 p41/tmo0/rxd2/irrxd p40/tmci0/txd2/irtxd p52/sck0/scl0 p51/rxd0 p50/txd0 p77/an7/da1 p76/an6/da0 p75/an5 p74/an4 p73/an3 p72/an2 p71/an1 p70/an0 p86/ /sck1/scl1 p85/ /rxd1 p84/ /txd1 p83/ * p82/hifsd/ * p81/ /ga20 p80/ha0/ * avref avcc avss xtal extal vccb md1 md0 nmi vcc vcl vss vss vss vss port 8 port 7 clock pulse generator internal data bus internal address bus bus controller port a port 2 port 1 port 3 port b port 9 port 6 port 4 port 5 note: * the lpc function and the pin function are not supported by the h8s/2148b. keyboard buffer controller 3 channels figure 1.1 internal block diagram of h8s/2140b, h8s/2141b, h8s/2145b, and h8s/2148b rev. 2.0, 08/02, page 4 of 788 h8s/2000 cpu dtc bus controller interrupt controller wdt 2 channels keyboard buffer controller 3 channels rom (flash memory, masked rom) ram 8-bit pwm 16-bit frt 8-bit timer 4 channels timer connection 14-bit pwm host interfaces (lpc, xbs) 10-bit a/d converter 8-bit d/a converter sci 3 channels (irda 1 channel) iic 2 channels p17/a7/pw7 p16/a6/pw6 p15/a5/pw5 p14/a4/pw4 p13/a3/pw3 p12/a2/pw2 p11/a1/pw1 p10/a0/pw0 p27/a15/pw15/cblank p26/a14/pw14 p25/a13/pw13 p24/a12/pw12 p23/a11/pw11 p22/a10/pw10 p21/a9/pw9 p20/a8/pw8 pa7/a23/ /cin15/ps2cd pa6/a22/ /cin14/ps2cc pa5/a21/ /cin13/ps2bd pa4/a20/ /cin12/ps2bc pa3/a19/ /cin11/ps2ad pa2/a18/ /cin10/ps2ac pa1/a17/ /cin9 pa0/a16/ /cin8 p37/d15/hdb7/serirq p36/d14/hdb6/lclk p35/d13/hdb5/ p34/d12/hdb4/ p33/d11/hdb3/lad3 p32/d10/hdb2/lad2 p31/d9/hdb1/lad1 p30/d8/hdb0/lad0 pb7/d7/ pb6/d6/ pb5/d5/ pb4/d4/ pb3/d3/ / pb2/d2/ / pb1/d1/ /hirq4/lsci pb0/d0/ /hirq3/ p97/ /sda0 p96/?/excl p95/ / / p94/ / p93/ / p92/ p91/ p90/ / / / p67/tmox/cin7/ / p66/ftob/cin6/ / p65/ftid/cin5/ p64/ftic/cin4/ /clampo p63/ftib/cin3/ /vfbacki p62/ftia/cin2/ /vsynci/tmiy p61/ftoa/cin1/ /vsynco p60/ftci/cin0/ /hfbacki/tmix p47/pwx1 p46/pwx0 p45/tmri1/hirq12/csynci p44/tmo1/hirq1/hsynco p43/tmci1/hirq11/hsynci p42/tmri0/sck2/sda1 p41/tmo0/rxd2/irrxd p40/tmci0/txd2/irtxd p52/sck0/scl0 p51/rxd0 p50/txd0 x1 x2 xtal extal vccb md1 md0 nmi vcc vcc vcl vss vss vss vss vss clock pulse generator internal data bus internal address bus port 9 port 6 port 4 port 5 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 port d port c port b port 3 port 1 port 2 port a p77/an7/da1 p76/an6/da0 p75/an5 p74/an4 p73/an3 p72/an2 p71/an1 p70/an0 p86/ /sck1/scl1 p85/ /rxd1 p84/ /txd1 p83/ p82/hifsd/ p81/ /ga20 p80/ha0/ avref avcc avss port 8 port 7 pg7 pg6 pg5 pg4 pg3 pg2 pg1 pg0 port g pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 port f pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 port e figure 1.2 internal block diagram of h8s/2160b and h8s/2161b rev. 2.0, 08/02, page 5 of 788 1.3 pin arrangement and functions 1.3.1 pin arrangement fp-100b tfp-100b (top view) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 xtal extal vccb md1 md0 nmi vcl pa7/a23/cin15/ /ps2cd pa6/a22/cin14/ /ps2cc p52/sck0/scl0 p51/rxd0 p50/txd0 vss p97/ /sda0 p96/ /excl p95/ / / p94/ / pa5/a21/cin13/ /ps2bd pa4/a20/cin12/ /ps2bc p93/ / p92/ p91/ p90/ / / / p14/a4/pw4 p15/a5/pw5 p16/a6/pw6 p17/a7/pw7 vss vss pb4/d4/ * pb5/d5/ * p20/a8/pw8 p21/a9/pw9 p22/a10/pw10 p23/a11/pw11 p24/a12/pw12 p25/a13/pw13 p26/a14/pw14 p27/a15/pw15/cblank vcc pb6/d6/ * pb7/d7/ * p47/pwx1 p46/pwx0 p45/tmri1/hirq12/csynci p44/tmo1/hirq1/hsynco p43/tmci1/hirq11/hsynci p42/tmri0/sck2/sda1 p41/tmo0/rxd2/irrxd p40/tmci0/txd2/irtxd pa0/a16/cin8/ pa1/a17/cin9/ avss p77/an7/da1 p76/an6/da0 p75/an5 p74/an4 p73/an3 p72/an2 p71/an1 p70/an0 avcc avref p67/tmox/cin7/ / p66/ftob/cin6/ / p65/ftid/cin5/ p64/ftic/cin4/ /clampo pa2/a18/cin10/ /ps2ac pa3/a19/cin11/ /ps2ad p63/ftib/cin3/ /vfbacki p62/ftia/cin2/ /vsynci/tmiy p61/ftoa/cin1/ /vsynco p60/ftci/cin0/ /hfbacki/tmix p13/a3/pw3 p12/a2/pw2 p11/a1/pw1 p10/a0/pw0 pb3/d3/ * / pb2/d2/ * / p30/d8 /hdb0/lad0 * p31/d9 /hdb1/lad1 * p32/d10/hdb2/lad2 * p33/d11/hdb3/lad3 * p34/d12/hdb4/ * p35/d13/hdb5/ * p36/d14/hdb6/lclk * p37/d15/hdb7/serirq * pb1/d1/ * /hirq4/lsci * pb0/d0/ * /hirq3/ * vss p80/ha0/ * p81/ /ga20 p82/hifsd/ * p83/ * p84/ /txd1 p85/ /rxd1 p86/ /sck1/scl1 55 54 53 52 51 12345678910111213141516171819202122232425 note: * the lpc function and the pin function are not supported by the h8s/2148b. figure 1.3 pin arrangement of h8s/2140b, h8s/2141b, h8s/2145b, and h8s/2148b rev. 2.0, 08/02, page 6 of 788 tfp-144 (top view) 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 vcc p43/tmci1/hirq11/hsynci p44/tmo1/hirq1/hsynco p45/tmri1/hirq12/csynci p46/pwx0 p47/pwx1 vss md1 md0 nmi vcl p52/sck0/scl0 p51/ rxd0 p50/txd0 p97/ /sda0 p96/ / excl p95/ / / p94/ / p93/ / p92/ p91/ p90/ / / / pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 pa7/a23/cin15/ /ps2cd pa6/a22/cin14/ /ps2cc pa5/a21/cin13/ /ps2bd vccb p13/a3/pw3 p14/a4/pw4 p15/a5/pw5 p16/a6/pw6 p17/a7/pw7 p20/a8/pw8 p21/a9/pw9 p22/a10/pw10 p23/a11/pw11 p24/a12/pw12 p25/a13/pw13 p26/a14/pw14 p27/a15/pw15/cblank vss pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 vcc p67/tmox/cin7/ / p66/ftob/cin6/ / p65/ftid/cin5/ p64/ftic/cin4/ /clampo p63/ftib/cin3/ /vfbacki p62/ftia/cin2/ /vsynci/tmiy p61/ftoa/cin1/ /vsynco p60/ftci/cin0/ /hfbacki/tmix avref avcc p77/an7/da1 p76/an6/da0 p75/an5 p74/an4 p73/an3 p72/an2 p71/an1 p70/an0 avss pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 pg0 pg1 pg2 pg3 pg4 pg5 pg6 pg7 pf0 pf1 pf2 pf3 pf4 pf5 pf6 pf7 vss pa0/a16/cin8/ pa1/a17/cin9/ pa2/a18/cin10/ /ps2ac pa3/a19/cin11/ /ps2ad pa4/a20/cin12/ /ps2bc p12/a2/pw2 p11/a1/pw1 vss p10/a0/pw0 pb7/d7/ pb6/d6/ pb5/d5/ pb4/d4/ pb3/d3/ / pb2/d2/ / pb1/d1/hirq4/ /lsci pb0/d0/hirq3/ / p30/d8/hdb0/lad0 p31/d9/hdb1/lad1 p32/d10/hdb2/lad2 p33/d11/hdb3/lad3 p34/d12/hdb4/ p35/d13/hdb5/ p36/d14/hdb6/lclk p37/d15/hdb7/serirq p80/ha0/ p81/ /ga20 p82/hifsd/ p83/ p84/ /txd1 p85/ /rxd1 p86/ /sck1/scl1 p40/tmci0/txd2/irtxd p41/tmo0/rxd2/irrxd p42/tmri0/sck2/sda1 vss x1 x2 xtal extal 88 87 86 85 84 12345678910111213141516171819202122232425 26 27 28 29 30 31 32 33 34 35 36 83 82 81 80 79 78 77 76 75 74 73 figure 1.4 pin arrangement of h8s/2160b and h8s/2161b rev. 2.0, 08/02, page 7 of 788 1.3.2 pin functions in each operating mode table 1.1 pin functions of h8s/2141b, h8s/2140b, h8s/2145b, and h8s/2148b in each operating mode pin name pin no. extended modes single-chip modes flash memory fp-100b tfp-100b mode 1 mode 2, mode 3 (expe = 1) mode 2, mode 3 (expe = 0) programmer mode 1 5(6 5(6 5(6 5(6 2 xtal xtal xtal xtal 3 extal extal extal extal 4 vccb vccb vccb vcc 5 md1 md1 md1 vss 6 md0 md0 md0 vss 7 nmi nmi nmi fa9 8 67%< 67%< 67%< vcc 9 vcl vcl vcl vcc 10 (b) pa7/cin15/ .,1 48 / ps2cd pa7/a23/cin15/ .,1 48 /ps2cd pa7/cin15/ .,1 48 / ps2cd nc 11 (b) pa6/cin14/ .,1 47 / ps2cc pa6/a22/cin14/ .,1 47 /ps2cc pa6/cin14/ .,1 47 / ps2cc nc 12 (n) p52/sck0/scl0 p52/sck0/scl0 p52/sck0/scl0 nc 13 p51/rxd0 p51/rxd0 p51/rxd0 fa17 14 p50/txd0 p50/txd0 p50/txd0 nc 15 vss vss vss vss 16 (n) p97/ :$,7 /sda0 p97/ :$,7 /sda0 p97/sda0 vcc 17 p96/?/excl p96/?/excl p96/?/excl nc 18 $6 / ,26 $6 / ,26 p95/ &6 4 fa16 19 +:5 +:5 p94/ ,2: fa15 20 (b) pa5/cin13/ .,1 46 / ps2bd pa5/a21/cin13/ .,1 46 /ps2bd pa5/cin13/ .,1 46 / ps2bd nc 21 (b) pa4/cin12/ .,1 45 / ps2bc pa4/a20/cin12/ .,1 45 /ps2bc pa4/cin12/ .,1 45 / ps2bc nc rev. 2.0, 08/02, page 8 of 788 pin name pin no. extended modes single-chip modes flash memory fp-100b tfp-100b mode 1 mode 2, mode 3 (expe = 1) mode 2, mode 3 (expe = 0) programmer mode 22 5' 5' p93/ ,25 :( 23 p92/ ,54 3 p92/ ,54 3 p92/ ,54 3 vss 24 p91/ ,54 4 p91/ ,54 4 p91/ ,54 4 vcc 25 p90/ /:5 / ,54 5 / $'75* p90/ /:5 / ,54 5 / $'75* p90/ (&6 5 / ,54 5 / $'75* vcc 26 p60/ftci/cin0/ .,1 3 /hfbacki/ tmix p60/ftci/cin0/ .,1 3 /hfbacki/ tmix p60/ftci/cin0/ .,1 3 /hfbacki/ tmix nc 27 p61/ftoa/cin1/ .,1 4 /vsynco p61/ftoa/cin1/ .,1 4 /vsynco p61/ftoa/cin1/ .,1 4 /vsynco nc 28 p62/ftia/cin2/ .,1 5 /vsynci/tmiy p62/ftia/cin2/ .,1 5 /vsynci/tmiy p62/ftia/cin2/ .,1 5 /vsynci/tmiy nc 29 p63/ftib/cin3/ .,1 6 /vfbacki p63/ftib/cin3/ .,1 6 /vfbacki p63/ftib/cin3/ .,1 6 /vfbacki nc 30 (b) pa3/cin11/ .,1 44 / ps2ad pa3/a19/cin11/ .,1 44 /ps2ad pa3/cin11/ .,1 44 / ps2ad nc 31 (b) pa2/cin10/ .,1 43 / ps2ac pa2/a18/cin10/ .,1 43 /ps2ac pa2/cin10/ .,1 43 / ps2ac nc 32 p64/ftic/cin4/ .,1 7 /clampo p64/ftic/cin4/ .,1 7 /clampo p64/ftic/cin4/ .,1 7 /clampo nc 33 p65/ftid/cin5/ .,1 8 p65/ftid/cin5/ .,1 8 p65/ftid/cin5/ .,1 8 nc 34 p66/ftob/cin6/ .,1 9 / ,54 9 p66/ftob/cin6/ .,1 9 / ,54 9 p66/ftob/cin6/ .,1 9 / ,54 9 nc 35 p67/tmox/cin7/ .,1 : / ,54 : p67/tmox/cin7/ .,1 : / ,54 : p67/tmox/cin7/ .,1 : / ,54 : vss 36 avref avref avref vcc 37 avcc avcc avcc vcc 38 p70/an0 p70/an0 p70/an0 nc 39 p71/an1 p71/an1 p71/an1 nc 40 p72/an2 p72/an2 p72/an2 nc 41 p73/an3 p73/an3 p73/an3 nc rev. 2.0, 08/02, page 9 of 788 pin name pin no. extended modes single-chip modes flash memory fp-100b tfp-100b mode 1 mode 2, mode 3 (expe = 1) mode 2, mode 3 (expe = 0) programmer mode 42 p74/an4 p74/an4 p74/an4 nc 43 p75/an5 p75/an5 p75/an5 nc 44 p76/an6/da0 p76/an6/da0 p76/an6/da0 nc 45 p77/an7/da1 p77/an7/da1 p77/an7/da1 nc 46 avss avss avss vss 47 (b) pa1/cin9/ .,1 < pa1/a17/cin9/ .,1 < pa1/cin9/ .,1 < nc 48 (b) pa0/cin8/ .,1 ; pa0/a16/cin8/ .,1 ; pa0/cin8/ .,1 ; nc 49 p40/tmci0/txd2/ irtxd p40/tmci0/txd2/ irtxd p40/tmci0/txd2/ irtxd nc 50 p41/tmo0/rxd2/ irrxd p41/tmo0/rxd2/ irrxd p41/tmo0/rxd2/ irrxd nc 51 (n) p42/tmri0/sck2/ sda1 p42/tmri0/sck2/ sda1 p42/tmri0/sck2/ sda1 nc 52 p43/tmci1/ hsynci p43/tmci1/ hsynci p43/tmci1/hirq11/ hsynci nc 53 p44/tmo1/ hsynco p44/tmo1/ hsynco p44/tmo1/hirq1/ hsynco nc 54 p45/tmri1/ csynci p45/tmri1/ csynci p45/tmri1/hirq12/ csynci nc 55 p46/pwx0 p46/pwx0 p46/pwx0 nc 56 p47/pwx1 p47/pwx1 p47/pwx1 nc 57 pb7/d7/ :8( : * pb7/d7/ :8( : * pb7/ :8( : * nc 58 pb6/d6/ :8( 9 * pb6/d6/ :8( 9 * pb6/ :8( 9 * nc 59 vcc vcc vcc vcc 60 a15 p27/a15/pw15/ cblank p27/pw15/ cblank &( 61 a14 p26/a14/pw14 p26/pw14 fa14 62 a13 p25/a13/pw13 p25/pw13 fa13 63 a12 p24/a12/pw12 p24/pw12 fa12 64 a11 p23/a11/pw11 p23/pw11 fa11 rev. 2.0, 08/02, page 10 of 788 pin name pin no. extended modes single-chip modes flash memory fp-100b tfp-100b mode 1 mode 2, mode 3 (expe = 1) mode 2, mode 3 (expe = 0) programmer mode 65 a10 p22/a10/pw10 p22/pw10 fa10 66 a9 p21/a9/pw9 p21/pw9 2( 67 a8 p20/a8/pw8 p20/pw8 fa8 68 pb5/d5/ :8( 8 * pb5/d5/ :8( 8 * pb5/ :8( 8 * nc 69 pb4/d4/ :8( 7 * pb4/d4/ :8( 7 * pb4/ :8( 7 * nc 70 vss vss vss vss 71 vss vss vss vss 72 a7 p17/a7/pw7 p17/pw7 fa7 73 a6 p16/a6/pw6 p16/pw6 fa6 74 a5 p15/a5/pw5 p15/pw5 fa5 75 a4 p14/a4/pw4 p14/pw4 fa4 76 a3 p13/a3/pw3 p13/pw3 fa3 77 a2 p12/a2/pw2 p12/pw2 fa2 78 a1 p11/a1/pw1 p11/pw1 fa1 79 a0 p10/a0/pw0 p10/pw0 fa0 80 pb3/d3/ :8( 6 * pb3/d3/ :8( 6 * pb3/ :8( 6 * / &6 7 nc 81 pb2/d2/ :8( 5 * pb2/d2/ :8( 5 * pb2/ :8( 5 * / &6 6 nc 82 d8 d8 p30/hdb0/lad0 * fo0 83 d9 d9 p31/hdb1/lad1 * fo1 84 d10 d10 p32/hdb2/lad2 * fo2 85 d11 d11 p33/hdb3/lad3 * fo3 86 d12 d12 p34/hdb4/ /)5$0( * fo4 87 d13 d13 p35/hdb5/ /5(6(7 * fo5 88 d14 d14 p36/hdb6/lclk * fo6 89 d15 d15 p37/hdb7/serirq * fo7 90 pb1/d1/ :8( 4 * pb1/d1/ :8( 4 * pb1/hirq4/ :8( 4 * / lsci * nc 91 pb0/d0/ :8( 3 * pb0/d0/ :8( 3 * pb0/hirq3/ :8( 3 * / /60, * nc rev. 2.0, 08/02, page 11 of 788 pin name pin no. extended modes single-chip modes flash memory fp-100b tfp-100b mode 1 mode 2, mode 3 (expe = 1) mode 2, mode 3 (expe = 0) programmer mode 92 vss vss vss vss 93 p80 p80 p80/ha0/ 30( * nc 94 p81 p81 p81/ &6 5 /ga20 nc 95 p82 p82 p82/hifsd/ &/.581 * nc 96 p83 p83 p83/ /3&3' * nc 97 p84/ ,54 6 /txd1 p84/ ,54 6 /txd1 p84/ ,54 6 /txd1 nc 98 p85/ ,54 7 /rxd1 p85/ ,54 4/rxd1 p85/ ,54 7 /rxd1 nc 99 (n) p86/ ,54 8 /sck1/ scl1 p86/ ,54 8 /sck1/ scl1 p86/ ,54 8 /sck1/ scl1 nc 100 5(62 5(62 5(62 nc note: * the (b) in pin no. means the vccb drive and the (n) in pin no. means the nmos push- pull/open-drain drive. * : the lpc function and the :8( pin function are not supported by the h8s/2148b. rev. 2.0, 08/02, page 12 of 788 table 1.2 pin functions of h8s/2160b and h8s/2161b in each operating mode pin name pin no. extended modes single-chip modes flash memory tfp-144 mode 1 mode 2, mode 3 (expe = 1) mode 2, mode 3 (expe = 0)) programmer mode 1 vcc vcc vcc vcc 2 p43/tmci1/ hsynci p43/tmci1/ hsynci p43/tmci1/hirq11/ hsynci nc 3 p44/tmo1/ hsynco p44/tmo1/ hsynco p44/tmo1/hirq1/ hsynco nc 4 p45/tmri1/ csynci p45/tmri1/ csynci p45/tmri1/hirq12/ csynci nc 5 p46/pwx0 p46/pwx0 p46/pwx0 nc 6 p47/pwx1 p47/pwx1 p47/pwx1 nc 7 vss vss vss vss 8 5(6 5(6 5(6 5(6 9 md1 md1 md1 vss 10 md0 md0 md0 vss 11 nmi nmi nmi fa9 12 67%< 67%< 67%< vcc 13 vcl vcl vcl vcc 14 (n) p52/sck0/scl0 p52/sck0/scl0 p52/sck0/scl0 fa18 15 p51/rxd0 p51/rxd0 p51/rxd0 fa17 16 p50/txd0 p50/txd0 p50/txd0 nc 17 (n) p97/ :$,7 /sda0 p97/ :$,7 /sda0 p97/sda0 vcc 18 p96/?/excl p96/?/excl p96/?/excl nc 19 $6 / ,26 $6 / ,26 p95/ &6 4 fa16 20 +:5 +:5 p94/ ,2: fa15 21 5' 5' p93/ ,25 :( 22 p92/ ,54 3 p92/ ,54 3 p92/ ,54 3 vss 23 p91/ ,54 4 p91/ ,54 4 p91/ ,54 4 vcc 24 p90/ /:5 / ,54 5 / $'75* p90/ /:5 / ,54 5 / $'75* p90/ ,54 5 / $'75* / (&6 5 vcc 25 pe7 pe7 pe7 nc rev. 2.0, 08/02, page 13 of 788 pin name pin no. extended modes single-chip modes flash memory tfp-144 mode 1 mode 2, mode 3 (expe = 1) mode 2, mode 3 (expe = 0) programmer mode 26 pe6 pe6 pe6 nc 27 pe5 pe5 pe5 nc 28 pe4 pe4 pe4 nc 29 pe3 pe3 pe3 nc 30 pe2 pe2 pe2 nc 31 pe1 pe1 pe1 nc 32 pe0 pe0 pe0 nc 33 (b) pa7/cin15/ .,1 48 / ps2cd pa7/a23/cin15/ .,1 48 /ps2cd pa7/cin15/ .,1 48 / ps2cd nc 34 (b) pa6/cin14/ .,1 47 / ps2cc pa6/a22/cin14/ .,1 47 /ps2cc pa6/cin14/ .,1 47 / ps2cc nc 35 (b) pa5/cin13/ .,1 46 / ps2bd pa5/a21/cin13/ .,1 46 /ps2bd pa5/cin13/ .,1 46 / ps2bd nc 36 vccb vccb vccb vcc 37 (b) pa4/cin12/ .,1 45 / ps2bc pa4/a20/cin12/ .,1 45 /ps2bc pa4/cin12/ .,1 45 / ps2bc nc 38 (b) pa3/cin11/ .,1 44 / ps2ad pa3/a19/cin11/ .,1 44 /ps2ad pa3/cin11/ .,1 44 / ps2ad nc 39 (b) pa2/cin10/ .,1 43 / ps2ac pa2/a18/cin10/ .,1 43 /ps2ac pa2/cin10/ .,1 43 / ps2ac nc 40 (b) pa1/cin9/ .,1 < pa1/a17/cin9/ .,1 < pa1/cin9/ .,1 < nc 41 (b) pa0/cin8/ .,1 ; pa0/a16/cin8/ .,1 ; pa0/cin8/ .,1 ; nc 42 vss vss vss vss 43 pf7 pf7 pf7 nc 44 pf6 pf6 pf6 nc 45 pf5 pf5 pf5 nc 46 pf4 pf4 pf4 nc 47 pf3 pf3 pf3 nc 48 pf2 pf2 pf2 nc 49 pf1 pf1 pf1 nc 50 pf0 pf0 pf0 nc rev. 2.0, 08/02, page 14 of 788 pin name pin no. extended modes single-chip modes flash memory tfp-144 mode 1 mode 2, mode 3 (expe = 1) mode 2, mode 3 (expe = 0) programmer mode 51 (n) pg7 pg7 pg7 nc 52 (n) pg6 pg6 pg6 nc 53 (n) pg5 pg5 pg5 nc 54 (n) pg4 pg4 pg4 nc 55 (n) pg3 pg3 pg3 nc 56 (n) pg2 pg2 pg2 nc 57 (n) pg1 pg1 pg1 nc 58 (n) pg0 pg0 pg0 nc 59 pd7 pd7 pd7 nc 60 pd6 pd6 pd6 nc 61 pd5 pd5 pd5 nc 62 pd4 pd4 pd4 nc 63 pd3 pd3 pd3 nc 64 pd2 pd2 pd2 nc 65 pd1 pd1 pd1 nc 66 pd0 pd0 pd0 nc 67 avss avss avss vss 68 p70/an0 p70/an0 p70/an0 nc 69 p71/an1 p71/an1 p71/an1 nc 70 p72/an2 p72/an2 p72/an2 nc 71 p73/an3 p73/an3 p73/an3 nc 72 p74/an4 p74/an4 p74/an4 nc 73 p75/an5 p75/an5 p75/an5 nc 74 p76/an6/da0 p76/an6/da0 p76/an6/da0 nc 75 p77/an7/da1 p77/an7/da1 p77/an7/da1 nc 76 avcc avcc avcc vcc 77 avref avref avref vcc 78 p60/ftci/cin0/ .,1 3 /hfbacki/ tmix p60/ftci/cin0/ .,1 3 /hfbacki/ tmix p60/ftci/cin0/ .,1 3 /hfbacki/ tmix nc rev. 2.0, 08/02, page 15 of 788 pin name pin no. extended modes single-chip modes flash memory tfp-144 mode 1 mode 2, mode 3 (expe = 1) mode 2, mode 3 (expe = 0) programmer mode 79 p61/ftoa/cin1/ .,1 4 /vsynco p61/ftoa/cin1/ .,1 4 /vsynco p61/ftoa/cin1/ .,1 4 /vsynco nc 80 p62/ftia/cin2/ .,1 5 /vsynci/tmiy p62/ftia/cin2/ .,1 5 /vsynci/tmiy p62/ftia/cin2/ .,1 5 /vsynci/tmiy nc 81 p63/ftib/cin3/ .,1 6 /vfbacki p63/ftib/cin3/ .,1 6 /vfbacki p63/ftib/cin3/ .,1 6 /vfbacki nc 82 p64/ftic/cin4/ .,1 7 /clampo p64/ftic/cin4/ .,1 7 /clampo p64/ftic/cin4/ .,1 7 /clampo nc 83 p65/ftid/cin5/ .,1 8 p65/ftid/cin5/ .,1 8 p65/ftid/cin5/ .,1 8 nc 84 p66/ftob/cin6/ .,1 9 / ,54 9 p66/ftob/cin6/ .,1 9 / ,54 9 p66/ftob/cin6/ .,1 9 / ,54 9 nc 85 p67/tmox/cin7/ .,1 : / ,54 : p67/tmox/cin7/ .,1 : / ,54 : p67/tmox/cin7/ .,1 : / ,54 : vss 86 vcc vcc vcc vcc 87 pc7 pc7 pc7 nc 88 pc6 pc6 pc6 nc 89 pc5 pc5 pc5 nc 90 pc4 pc4 pc4 nc 91 pc3 pc3 pc3 nc 92 pc2 pc2 pc2 nc 93 pc1 pc1 pc1 nc 94 pc0 pc0 pc0 nc 95 vss vss vss vss 96 a15 p27/a15/pw15/ cblank p27/pw15/cblank &( 97 a14 p26/a14/pw14 p26/pw14 fa14 98 a13 p25/a13/pw13 p25/pw13 fa13 99 a12 p24/a12/pw12 p24/pw12 fa12 100 a11 p23/a11/pw11 p23/pw11 fa11 101 a10 p22/a10/pw10 p22/pw10 fa10 rev. 2.0, 08/02, page 16 of 788 pin name pin no. extended modes single-chip modes flash memory tfp-144 mode 1 mode 2, mode 3 (expe = 1) mode 2, mode 3 (expe = 0) programmer mode 102 a9 p21/a9/pw9 p21/pw9 2( 103 a8 p20/a8/pw8 p20/pw8 fa8 104 a7 p17/a7/pw7 p17/pw7 fa7 105 a6 p16/a6/pw6 p16/pw6 fa6 106 a5 p15/a5/pw5 p15/pw5 fa5 107 a4 p14/a4/pw4 p14/pw4 fa4 108 a3 p13/a3/pw3 p13/pw3 fa3 109 a2 p12/a2/pw2 p12/pw2 fa2 110 a1 p11/a1/pw1 p11/pw1 fa1 111 vss vss vss vss 112 a0 p10/a0/pw0 p10/pw0 fa0 113 pb7/d7/ :8( : pb7/d7/ :8( : pb7/ :8( : nc 114 pb6/d6/ :8( 9 pb6/d6/ :8( 9 pb6/ :8( 9 nc 115 pb5/d5/ :8( 8 pb5/d5/ :8( 8 pb5/ :8( 8 nc 116 pb4/d4/ :8( 7 pb4/d4/ :8( 7 pb4/ :8( 7 nc 117 pb3/d3/ :8( 6 pb3/d3/ :8( 6 pb3/ :8( 6 / &6 7 nc 118 pb2/d2/ :8( 5 pb2/d2/ :8( 5 pb2/ :8( 5 / &6 6 nc 119 pb1/d1/ :8( 4 pb1/d1/ :8( 4 pb1/hirq4/ :8( 4 / lsci nc 120 pb0/d0/ :8( 3 pb0/d0/ :8( 3 pb0/hirq3/ :8( 3 / /60, nc 121 d8 d8 p30/hdb0/lad0 fo0 122 d9 d9 p31/hdb1/lad1 fo1 123 d10 d10 p32/hdb2/lad2 fo2 124 d11 d11 p33/hdb3/lad3 fo3 125 d12 d12 p34/hdb4/ /)5$0( fo4 126 d13 d13 p35/hdb5/ /5(6(7 fo5 127 d14 d14 p36/hdb6/lclk fo6 128 d15 d15 p37/hdb7/serirq fo7 129 p80 p80 p80/ha0/ 30( nc rev. 2.0, 08/02, page 17 of 788 pin name pin no. extended modes single-chip modes flash memory tfp-144 mode 1 mode 2, mode 3 (expe = 1) mode 2, mode 3 (expe = 0) programmer mode 130 p81 p81 p81/ &6 5 /ga20 nc 131 p82 p82 p82/hifsd/ &/.581 nc 132 p83 p83 p83/ /3&3' nc 133 p84/ ,54 6 /txd1 p84/ ,54 6 /txd1 p84/ ,54 6 /txd1 nc 134 p85/ ,54 7 /rxd1 p85/ ,54 7 /rxd1 p85/ ,54 7 /rxd1 nc 135 (n) p86/ ,54 8 /sck1/ scl1 p86/ ,54 8 /sck1/ scl1 p86/ ,54 8 /sck1/ scl1 nc 136 p40/tmci0/txd2/ irtxd p40/tmci0/txd2/ irtxd p40/tmci0/txd2/ irtxd nc 137 p41/tmo0/rxd2/ irrxd p41/tmo0/rxd2/ irrxd p41/tmo0/rxd2/ irrxd nc 138 (n) p42/tmri0/sck2/ sda1 p42/tmri0/sck2/ sda1 p42/tmri0/sck2/ sda1 nc 139 vss vss vss vss 140 x1 x1 x1 nc 141 x2 x2 x2 nc 142 5(62 5(62 5(62 nc 143 xtal xtal xtal xtal 144 extal extal extal extal note: * the (b) in pin no. means the vccb drive and the (n) in pin no. means the nmos push- pull/open-drain drive. rev. 2.0, 08/02, page 18 of 788 1.3.3 pin functions table 1.3 pin functions pin no. type symbol fp-100b, tfp-100b tfp-144 i/o name and function vcc 59 1, 86 input power supply pin. connect the pin to the system power supply. vcl 9 13 input power supply pin. connect the pin to vcc. vccb 4 36 input the power supply for the port a input/output buffer. power vss 15, 70, 71, 92 7, 42, 95, 111, 139 input ground pin. connect to the system power supply (0 v). xtal 2 143 input extal 3 144 input pins for connection to crystal resonators. the extal pin can also input an external clock. see section 25, clock pulse generator, for typical connection diagrams. ? 17 18 output supplies the system clock to external devices. excl 17 18 input input a 32.768 khz external subclock. x1 140 input leave open. clock x2 141 input leave open. operating mode control md1 md0 5 6 9 10 input these pins set the operating mode. these pins should not be changed while the mcu is operating. 5(6 1 8 input reset pin. when this pin becomes low, the chip is reset. 5(62 100 142 output outputs reset signal to external device. system control 67%< 8 12 input when this pin is driven low, a transition is made to hardware standby mode. rev. 2.0, 08/02, page 19 of 788 pin no. type symbol fp-100b, tfp-100b tfp-144 i/o name and function a23 to a16 10, 11, 20, 21, 30, 31, 47, 48 33, 34, 35, 37, 38, 39, 40, 41 output address output pins when 16-mbyte space is used. address bus a15 to a0 60 to 67, 72 to 79 96 to 110, 112 output address output pins d15 to d8 89 to 82 128 to 121 input/ output bidirectional data bus for upper byte of 16- bit data. data bus d7 to d0 57, 58, 68, 69, 80, 81, 90, 91 113 to 120 input/ output bidirectional data bus for lower byte of 16- bit data. :$,7 16 17 input requests insertion of a wait state in the bus cycle when accessing external 3-state address space. 5' 22 21 output when this pin is low, it indicates that the external address space is being read. +:5 19 20 output when this pin is low, it indicates that the external address space is being written to. the upper half of the data bus is valid. /:5 25 24 output when this pin is low, it indicates that the external address space is being written to. the lower half of the data bus is valid. bus control $6 / ,26 18 19 output when this pin is low, it indicates that address output on the address bus is valid. nmi 7 11 input input pin for a nonmaskable interrupt request. interrupt signals ,54 3 to ,54 : 23 to 25, 97 to 99, 34, 35 22 to 24, 133 to 135, 84, 85 input these pins request a maskable interrupt. ftci 26 78 input the counter clock input pin. ftoa 27 79 output the output compare a output pin. ftob 34 84 output the output compare b output pin. 16-bit free- running timer (frt) ftia 28 80 input the input capture a input pin. rev. 2.0, 08/02, page 20 of 788 pin no. type symbol fp-100b, tfp-100b tfp-144 i/o name and function ftib 29 81 input the input capture b input pin. ftic 32 82 input the input capture c input pin. 16-bit free- running timer (frt) ftid 33 83 input the input capture d input pin. tmo0 tmo1 tmox 50 53 35 137 3 85 output the waveform output pins for the output compare function. tmci0 tmci1 49 52 136 2 input input pins for the external clock input to counters. 8-bit timer (tmr_0, tmr_1, tmr_x) tmri0 tmri1 51 54 138 4 input the counter reset input pins. 8-bit timer (tmr_x, tmr_y) tmix tmiy 26 28 78 80 input the counter event input and counter reset input pins. 8-bit pwm timer (pwm) pw15 to pw0 60 to 67, 72 to 79 96 to 110, 112 output pwm timer pulse output pins. 14-bit pwm timer (pwmx) pwx0 pwx1 55 56 5 6 output pwm d/a pulse output pins. txd0 txd1 txd2 14 97 49 16 133 136 output transmit data output pins. rxd0 rxd1 rxd2 13 98 50 15 134 137 input receive data input pins. serial communi- cation interface (sci_0, sci_1, sci_2) sck0 sck1 sck2 12 99 51 14 135 138 input/ output clock input/output pins. the output type is nmos push-pull. irtxd 49 136 output sci with irda (sci_2) irrxd 50 137 input input and output pins for data encoded for irda use. rev. 2.0, 08/02, page 21 of 788 pin no. type symbol fp-100b, tfp-100b tfp-144 i/o name and function ps2ac ps2bc ps2cc 31 21 11 39 37 34 input/ output keyboard buffer controller synchronization clock input/output pins. keyboard buffer controller ps2ad ps2bd ps2cd 30 20 10 38 35 33 input/ output keyboard buffer controller data input/output pins. hdb7 to hdb0 89 to 82 128 to 121 input/ output bidirectional 8-bit bus for accessing xbs. &6 4 , &6 5 / (&6 5 , &6 6 , &6 7 18, 94, 25, 81, 80 19, 130, 24, 118, 117 input input pins for selecting xbs channels 1 to 4. the &6 5 or (&6 5 input pin is selected with the system control register. ,25 22 21 input input pin that enables reading from xbs. ,2: 19 20 input input pin that enables writing to xbs. ha0 93 129 input input pin that indicates whether an access is a data access or command access. ga20 94 130 output a20 gate control signal output pin. hirq11 hirq1 hirq12 hirq3 hirq4 52 53 54 91 90 2 3 4 120 119 output output pins for interrupt requests to the host. host interface (xbs) hifsd 95 131 input control input pin used to place xbs input/output pins in the high-impedance/ cutoff state. lad3 to lad0 85 to 82 124 to 121 input/ output lpc command, address, and data input/output pins. /)5$0( 86 125 input input pin that indicates the start of an lpc cycle or forced termination of an abnormal lpc cycle. /5(6(7 87 126 input input pin that indicates an lpc reset. host interface (lpc) lclk 88 127 input the lpc clock input pin. rev. 2.0, 08/02, page 22 of 788 pin no. type symbol fp-100b, tfp-100b tfp-144 i/o name and function serirq 89 128 input/ output input/output pin for lpc serialized host interrupts (hirq1, smi, hirq6, hirq9 to hirq12). lsci, /60, , 30( 90, 91, 93 119, 120, 129 input/ output lpc auxiliary output pins. functionally, they are general i/o ports. ga20 94 130 input/ output a20 gate control signal output pin. output state monitoring input is possible. &/.581 95 131 input/ output input/output pin that requests the start of lclk operation when lclk is stopped. host interface (lpc) /3&3' 96 132 input input pin that controls lpc module shutdown. .,1 3 to .,1 48 26 to 29, 32 to 35, 48, 47, 31, 30, 21, 20, 11, 10 78 to 85, 41 to 37, 35 to 33 input matrix keyboard input pins. .,1 3 to .,1 48 are used as key-scan inputs, and p10 to p17 and p20 to p27 are used as key-scan outputs. this allows a maximum 16-output 16-input, 256-key matrix to be configured. keyboard buffer controller :8( 3 to :8( : 91, 90, 81, 80, 69, 68, 58, 57 120 to 113 input wakeup event input pins. these pins allow the same kind of wakeup as key-wakeup from various sources. an7 to an0 45 to 38 68 to 75 input analog input pins. cin0 to cin15 26 to 29, 32 to 35, 48, 47, 31, 30, 21, 20, 11, 10 78 to 85, 41 to 37, 35 to 33 input a/d conversion input pins, but since they are also used as digital input/output pins, accuracy will fall. a/d converter $'75* 25 24 input pin for input of an external trigger to start a/d conversion. d/a converter da0 da1 44 45 74 75 output analog output pins. rev. 2.0, 08/02, page 23 of 788 pin no. type symbol fp-100b, tfp-100b tfp-144 i/o name and function avcc 37 76 input the analog power supply pin for the a/d converter and d/a converter. when the a/d and d/a converters are not used, this pin should be connected to the system power supply (+3 v). avref 36 77 input the reference power supply pin for the a/d converter and d/a converter. when the a/d and d/a converters are not used, this pin should be connected to the system power supply (+3 v). a/d converter d/a converter avss 46 67 input the ground pin for the a/d converter and d/a converter. this pin should be connected to the system power supply (0 v). vsynci hsynci csynci vfbacki hfbacki 28 52 54 29 26 80 2 4 81 78 input timer connection synchronous signal input pins. timer connec- tion vsynco hsynco clampo cblank 27 53 32 60 79 3 82 96 output timer connection synchronous signal output pins. scl0 scl1 12 99 14 135 input/ output i 2 c clock i/o pins. the output type is nmos open-drain output. i 2 c bus interface (iic) sda0 sda1 16 51 17 138 input/ output i 2 c data i/o pins. the output type is nmos open-drain output. rev. 2.0, 08/02, page 24 of 788 pin no. type symbol fp-100b, tfp-100b tfp-144 i/o name and function p17 to p10 72 to 79 104 to 110, 112 input/ output eight input/output pins. p27 to p20 60 to 67 96 to 103 input/ output eight input/output pins. p37 to p30 89 to 82 128 to 121 input/ output eight input/output pins. p47 to p40 56 to 49 6 to 2, 138 to 136 input/ output eight input/output pins. (the output type of p42 is nmos push- pull.) p52 to p50 12 to 14 14 to 16 input/ output three input/output pins. (the output type of p52 is nmos push- pull.) p67 to p60 35 to 32 29 to 26 85 to 78 input/ output eight input/output pins. p77 to p70 45 to 38 75 to 68 input eight input pins. p86 to p80 99 to 93 135 to 129 input/ output seven input/output pins. (the output type of p86 is nmos push- pull.) p97 to p90 16 to 19 22 to 25 17 to 24 input/ output eight input/output pins. (the output type of p97 is nmos push- pull.) pa7 to pa0 10, 11, 20, 21, 30, 31, 47, 48 33 to 35, 37 to 41 input/ output eight input/output pins. pb7 to pb0 57, 58, 68, 69, 80, 81, 90, 91 113 to 120 input/ output eight input/output pins. pc7 to pc0 87 to 94 input/ output eight input/output pins. pd7 to pd0 59 to 66 input/ output eight input/output pins. i/o ports pe7 to pe0 25 to 32 input/ output eight input/output pins. rev. 2.0, 08/02, page 25 of 788 pin no. type symbol fp-100b, tfp-100b tfp-144 i/o name and function pf7 to pf0 43 to 50 input/ output eight input/output pins. i/o ports pg7 to pg0 51 to 58 input/ output eight input/output pins. (the output type of pg7 to pg0 in the h8s/2160b and the h8s/2161b is nmos push-pull.) rev. 2.0, 08/02, page 26 of 788 rev. 2.0, 08/02, page 27 of 788 section 2 cpu the h8s/2000 cpu is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the h8/300 and h8/300h cpus. the h8s/2000 cpu has sixteen 16-bit general registers, can address a 16-mbyte linear address space, and is ideal for realtime control. this section describes the h8s/2000 cpu. the usable modes and address spaces differ depending on the product. for details on each product, refer to section 3, mcu operating modes. 2.1 features upward-compatibility with h8/300 and h8/300h cpus can execute h8/300 cpu and h8/300h cpu object programs general-register architecture sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers sixty-five basic instructions 8/16/32-bit arithmetic and logic instructions multiply and divide instructions powerful bit-manipulation instructions eight addressing modes register direct [rn] register indirect [@ern] register indirect with displacement [@(d:16,ern) or @(d:32,ern)] register indirect with post-increment or pre-decrement [@ern+ or @Cern] absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] immediate [#xx:8, #xx:16, or #xx:32] program-counter relative [@(d:8,pc) or @(d:16,pc)] memory indirect [@@aa:8] 16-mbyte address space program: 16 mbytes data: 16 mbytes high-speed operation all frequently-used instructions are executed in one or two states 8/16/32-bit register-register add/subtract: 1 state 8 8-bit register-register multiply: 12 states (mulxu.b), 13 states (mulxs.b) 16 ? 8-bit register-register divide: 12 states (divxu.b) 16 16-bit register-register multiply: 20 states (mulxu.w), 21 states (mulxs.w) 32 ? 16-bit register-register divide: 20 states (divxu.w) cpu210a_010020020700 rev. 2.0, 08/02, page 28 of 788 two cpu operating modes normal mode advanced mode power-down state transition to power-down state by sleep instruction selectable cpu clock speed 2.1.1 differences between h8s/2600 cpu and h8s/2000 cpu the differences between the h8s/2600 cpu and the h8s/2000 cpu are as shown below. register configuration the mac register is supported only by the h8s/2600 cpu. basic instructions the four instructions mac, clrmac, ldmac, and stmac are supported only by the h8s/2600 cpu. the number of execution states of the mulxu and mulxs instructions execution states instruction mnemonic h8s/2600 h8s/2000 mulxu.b rs, rd 3 12 mulxu mulxu.w rs, erd 4 20 mulxs.b rs, rd 4 13 mulxs mulxs.w rs, erd 5 21 in addition, there are differences in address space, ccr and exr register functions, power-down modes, etc., depending on the model. 2.1.2 differences from h8/300 cpu in comparison to the h8/300 cpu, the h8s/2000 cpu has the following enhancements. more general registers and control registers eight 16-bit extended registers and one 8-bit control register have been added. expanded address space normal mode supports the same 64-kbyte address space as the h8/300 cpu. advanced mode supports a maximum 16-mbyte address space. enhanced addressing the addressing modes have been enhanced to make effective use of the 16-mbyte address space. rev. 2.0, 08/02, page 29 of 788 enhanced instructions addressing modes of bit-manipulation instructions have been enhanced. signed multiply and divide instructions have been added. two-bit shift and two-bit rotate instructions have been added. instructions for saving and restoring multiple registers have been added. a test and set instruction has been added. higher speed basic instructions are executed twice as fast. 2.1.3 differences from h8/300h cpu in comparison to the h8/300h cpu, the h8s/2000 cpu has the following enhancements. additional control register one 8-bit control register has been added. enhanced instructions addressing modes of bit-manipulation instructions have been enhanced. two-bit shift and two-bit rotate instructions have been added. instructions for saving and restoring multiple registers have been added. a test and set instruction has been added. higher speed basic instructions are executed twice as fast. rev. 2.0, 08/02, page 30 of 788 2.2 cpu operating modes the h8s/2000 cpu has two operating modes: normal and advanced. normal mode supports a maximum 64-kbyte address space. advanced mode supports a maximum 16-mbyte address space. the mode is selected by the lsi's mode pins. 2.2.1 normal mode the exception vector table and stack have the same structure as in the h8/300 cpu in normal mode. address space linear access to a maximum address space of 64 kbytes is possible. extended registers (en) the extended registers (e0 to e7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. when extended register en is used as a 16-bit register it can contain any value, even when the corresponding general register (rn) is used as an address register. (if general register rn is referenced in the register indirect addressing mode with pre-decrement (@Crn) or post- increment (@rn+) and a carry or borrow occurs, the value in the corresponding extended register (en) will be affected.) instruction set all instructions and addressing modes can be used. only the lower 16 bits of effective addresses (ea) are valid. exception vector table and memory indirect branch addresses in normal mode, the top area starting at h'0000 is allocated to the exception vector table. one branch address is stored per 16 bits. the exception vector table in normal mode is shown in figure 2.1. for details on the exception vector table, see section 4, exception handling. the memory indirect addressing mode (@@aa:8) employed in the jmp and jsr instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. in normal mode, the operand is a 16-bit (word) operand, providing a 16-bit branch address. branch addresses can be stored in the top area from h'0000 to h'00ff. note that this area is also used for the exception vector table. stack structure in normal mode, when the program counter (pc) is pushed onto the stack in a subroutine call in normal mode, and the pc and condition-code register (ccr) are pushed onto the stack in exception handling, they are stored as shown in figure 2.2. the extended control register (exr) is not pushed onto the stack. for details, see section 4, exception handling. rev. 2.0, 08/02, page 31 of 788 h'0000 h'0001 h'0002 h'0003 h'0004 h'0005 h'0006 h'0007 h'0008 h'0009 h'000a h'000b reset exception vector (reserved for system use) exception vector 1 exception vector 2 exception vector table (reserved for system use) figure 2.1 exception vector table (normal mode) (a) subroutine branch (b) exception handling pc (16 bits) ccr ccr * pc (16 bits) sp note: * ignored when returning. sp figure 2.2 stack structure in normal mode 2.2.2 advanced mode address space linear access to a maximum address space of 16 mbytes is possible. extended registers (en) the extended registers (e0 to e7) can be used as 16-bit registers. they can also be used as the upper 16-bit segments of 32-bit registers or address registers. instruction set all instructions and addressing modes can be used. rev. 2.0, 08/02, page 32 of 788 exception vector table and memory indirect branch addresses in advanced mode, the top area starting at h'00000000 is allocated to the exception vector table in 32-bit units. in each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (see figure 2.3). for details on the exception vector table, see section 4, exception handling. h'00000000 h'00000003 h'00000004 h'0000000b h'0000000c h'00000010 h'00000008 h'00000007 reserved reserved reserved reset exception vector (reserved for system use) exception vector table exception vector 1 (reserved for system use) figure 2.3 exception vector table (advanced mode) the memory indirect addressing mode (@@aa:8) employed in the jmp and jsr instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. in advanced mode, the operand is a 32-bit longword operand, providing a 32-bit branch address. the upper 8 bits of these 32 bits are a reserved area that is regarded as h'00. branch addresses can be stored in the area from h'00000000 to h'000000ff. note that the top area of this range is also used for the exception vector table. stack structure in advanced mode, when the program counter (pc) is pushed onto the stack in a subroutine call, and the pc and condition-code register (ccr) are pushed onto the stack in exception handling, they are stored as shown in figure 2.4. the extended control register (exr) is not pushed onto the stack. for details, see section 4, exception handling. rev. 2.0, 08/02, page 33 of 788 (a) subroutine branch (b) exception handling pc (24 bits) ccr pc (24 bits) sp sp reserved figure 2.4 stack structure in advanced mode 2.3 address space figure 2.5 shows a memory map of the h8s/2000 cpu. the h8s/2000 cpu provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-mbyte (architecturally 4-gbyte) address space in advanced mode. the usable modes and address spaces differ depending on the product. for details on each product, refer to section 3, mcu operating modes. h'0000 h'ffff h'00000000 h'ffffffff h'00ffffff 64 kbytes 16 mbytes program area data area (b) advanced mode (a) normal mode not available in this lsi figure 2.5 memory map rev. 2.0, 08/02, page 34 of 788 2.4 register configuration the h8s/2000 cpu has the internal registers shown in figure 2.6. there are two types of registers: general registers and control registers. control registers are a 24-bit program counter (pc), an 8-bit extended control register (exr), and an 8-bit condition code register (ccr). t i2i1i0 exr * 76543210 pc 23 0 15 0 7 0 7 0 e0 e1 e2 e3 e4 e5 e6 e7 r0h r1h r2h r3h r4h r5h r6h r7h r0l r1l r2l r3l r4l r5l r6l r7l sp pc exr t i2 to i0 ccr i ui : stack pointer : program counter : extended control register : trace bit : interrupt mask bits : condition-code register : interrupt mask bit : user bit or interrupt mask bit : half-carry flag : user bit : negative flag : zero flag : overflow flag : carry flag er0 er1 er2 er3 er4 er5 er6 er7 (sp) iuihunzvc ccr 76543210 h u n z v c general registers (rn) and extended registers (en) control registers legend ---- note: * does not affect operation in this lsi. figure 2.6 cpu internal registers rev. 2.0, 08/02, page 35 of 788 2.4.1 general registers the h8s/2000 cpu has eight 32-bit general registers. these general registers are all functionally alike and can be used as both address registers and data registers. when a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. figure 2.7 illustrates the usage of the general registers. when the general registers are used as 32-bit registers or address registers, they are designated by the letters er (er0 to er7). when the general registers are used as 16-bit registers, the er registers are divided into 16-bit general registers designated by the letters e (e0 to e7) and r (r0 to r7). these registers are functionally equivalent, providing a maximum sixteen 16-bit registers. the e registers (e0 to e7) are also referred to as extended registers. when the general registers are used as 8-bit registers, the r registers are divided into 8-bit general registers designated by the letters rh (r0h to r7h) and rl (r0l to r7l). these registers are functionally equivalent, providing a maximum sixteen 8-bit registers. the usage of each register can be selected independently. general register er7 has the function of the stack pointer (sp) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. figure 2.8 shows the stack. ? address registers ? 32-bit registers ? 16-bit registers ? 8-bit registers er registers (er0 to er7) e registers (extended registers) (e0 to e7) r registers (r0 to r7) rh registers (r0h to r7h) rl registers (r0l to r7l) figure 2.7 usage of general registers rev. 2.0, 08/02, page 36 of 788 sp (er7) free area stack area figure 2.8 stack 2.4.2 program counter (pc) this 24-bit counter indicates the address of the next instruction the cpu will execute. the length of all cpu instructions is 2 bytes (one word), so the least significant pc bit is ignored. (when an instruction is fetched for read, the least significant pc bit is regarded as 0.) 2.4.3 extended control register (exr) exr does not affect operation in this lsi. bit bit name initial value r/w description 7 t 0 r/w trace bit does not affect operation in this lsi. 6 to 3 all 1 r reserved these bits are always read as 1. 2 to 0 i2 i1 i0 all 1 r/w interrupt mask bits 2 to 0 do not affect operation in this lsi. 2.4.4 condition-code register (ccr) this 8-bit register contains internal cpu status information, including an interrupt mask bit (i) and half-carry (h), negative (n), zero (z), overflow (v), and carry (c) flags. operations can be performed on the ccr bits by the ldc, stc, andc, orc, and xorc instructions. the n, z, v, and c flags are used as branching conditions for conditional branch (bcc) instructions. rev. 2.0, 08/02, page 37 of 788 bit bit name initial value r/w description 7 i 1 r/w interrupt mask bit masks interrupts other than nmi when set to 1. nmi is accepted regardless of the i bit setting. the i bit is set to 1 at the start of an exception-handling sequence. for details, refer to section 5, interrupt controller. 6 ui undefined r/w user bit or interrupt mask bit can be written to and read from by software using the ldc, stc, andc, orc, and xorc instructions. 5 h undefined r/w half-carry flag when the add.b, addx.b, sub.b, subx.b, cmp.b or neg.b instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. when the add.w, sub.w, cmp.w, or neg.w instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. when the add.l, sub.l, cmp.l, or neg.l instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. 4 u undefined r/w user bit can be written to and read from by software using the ldc, stc, andc, orc, and xorc instructions. 3 n undefined r/w negative flag stores the value of the most significant bit of data as a sign bit. 2 z undefined r/w zero flag set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. 1 v undefined r/w overflow flag set to 1 when an arithmetic overflow occurs, and cleared to 0 otherwise. 0 c undefined r/w carry flag set to 1 when a carry occurs, and cleared to 0 otherwise. used by add instructions, to indicate a carry subtract instructions, to indicate a borrow shift and rotate instructions, to indicate a carry the carry flag is also used as a bit accumulator by bit manipulation instructions. rev. 2.0, 08/02, page 38 of 788 2.4.5 initial register values the program counter (pc) among cpu internal registers is initialized when reset exception handling loads a start address from a vector table. the trace (t) bit in exr is cleared to 0, and the interrupt mask (i) bits in ccr and exr are set to 1. the other ccr bits and the general registers are not initialized. note that the stack pointer (er7) is undefined. the stack pointer should therefore be initialized by an mov.l instruction executed immediately after a reset. 2.5 data formats the h8s/2000 cpu can process 1-bit, 4-bit bcd, 8-bit (byte), 16-bit (word), and 32-bit (longword) data. bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, , 7) of byte operand data. the daa and das decimal-adjust instructions treat byte data as two digits of 4-bit bcd data. 2.5.1 general register data formats figure 2.9 shows the data formats of general registers. 70 70 msb lsb msb lsb 70 43 don't care don't care don't care 70 43 70 don't care 65432 710 70 don't care 65432 710 don't care rnh rnl rnh rnl rnh rnl data type register number data image byte data byte data 4-bit bcd data 4-bit bcd data 1-bit data 1-bit data upper lower upper lower figure 2.9 general register data formats (1) rev. 2.0, 08/02, page 39 of 788 15 0 msb lsb 15 0 msb lsb 31 16 msb 15 0 lsb en rn ern en rn rnh rnl msb lsb : general register er : general register e : general register r : general register rh : general register rl : most significant bit : least significant bit data type data image register number word data word data rn en longword data legend ern figure 2.9 general register data formats (2) rev. 2.0, 08/02, page 40 of 788 2.5.2 memory data formats figure 2.10 shows the data formats in memory. the h8s/2000 cpu can access word data and longword data in memory, but word or longword data must begin at an even address. if an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. this also applies to instruction fetches. when sp (er7) is used as an address register to access the stack, the operand size should be word size or longword size. 70 76 543210 msb lsb msb msb lsb lsb data type address 1-bit data byte data word data address l address l address 2m address 2m + 1 longword data address 2n address 2n + 1 address 2n + 2 address 2n + 3 data image figure 2.10 memory data formats rev. 2.0, 08/02, page 41 of 788 2.6 instruction set the h8s/2000 cpu has 65 types of instructions. the instructions are classified by function as shown in table 2.1. table 2.1 instruction classification function instructions size types mov b/w/l pop * 1 , push * 1 w/l ldm * 5 , stm * 5 l data transfer movfpe * 3 , movtpe * 3 b 5 add, sub, cmp, neg b/w/l addx, subx, daa, das b inc, dec b/w/l adds, subs l mulxu, divxu, mulxs, divxs b/w extu, exts w/l arithmetic operations tas * 4 b 19 logic operations and, or, xor, not b/w/l 4 shift shal, shar, shll, shlr, rotl, rotr, rotxl, rotxr b/w/l 8 bit manipulation bset, bclr, bnot, btst, bld, bild, bst, bist, band, biand, bor, bior, bxor, bixor b14 branch b cc * 2 , jmp, bsr, jsr, rts 5 system control trapa, rte, sleep, ldc, stc, andc, orc, xorc, nop 9 block data transfer eepmov 1 total: 65 notes: b: byte size; w: word size; l: longword size. 1. pop.w rn and push.w rn are identical to mov.w @sp+, rn and mov.w rn, @- sp. pop.l ern and push.l ern are identical to mov.l @sp+, ern and mov.l ern, @-sp. 2. b cc is the general name for conditional branch instructions. 3. cannot be used in this lsi. 4. when using the tas instruction, use registers er0, er1, er4, and er5. 5. er7 is not used as the register that can be saved (stm)/restored (ldm) when using stm/ldm instruction, because er7 is the stack pointer. rev. 2.0, 08/02, page 42 of 788 2.6.1 table of instructions classified by function tables 2.3 to 2.10 summarize the instructions in each functional category. the notation used in tables 2.3 to 2.10 is defined below. table 2.2 operation notation symbol description rd general register (destination) * rs general register (source) * rn general register * ern general register (32-bit register) (ead) destination operand (eas) source operand exr extended control register ccr condition-code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr pc program counter sp stack pointer #imm immediate data disp displacement + addition C subtraction multiplication ? division logical and logical or ? logical exclusive or ? move ~ not (logical complement) :8/:16/:24/:32 8-, 16-, 24-, or 32-bit length note: * general registers include 8-bit registers (r0h to r7h, r0l to r7l), 16-bit registers (r0 to r7, e0 to e7), and 32-bit registers (er0 to er7). rev. 2.0, 08/02, page 43 of 788 table 2.3 data transfer instructions instruction size * 1 function mov b/w/l (eas) ? rd, rs ? (ead) moves data between two general registers or between a general register and memory, or moves immediate data to a general register. movfpe b cannot be used in this lsi. movtpe b cannot be used in this lsi. pop w/l @sp+ ? rn pops a general register from the stack. pop.w rn is identical to mov.w @sp+, rn. pop.l ern is identical to mov.l @sp+, ern push w/l rn ? @-sp pushes a general register onto the stack. push.w rn is identical to mov.w rn, @-sp. push.l ern is identical to mov.l ern, @-sp. ldm * 2 l @sp+ ? rn (register list) pops two or more general registers from the stack. stm * 2 l rn (register list) ? @-sp pushes two or more general registers onto the stack. notes: 1. size refers to the operand size. b: byte w: word l: longword 2. er7 is not used as the register that can be saved (stm)/restored (ldm) when using stm/ldm instruction, because er7 is the stack pointer. rev. 2.0, 08/02, page 44 of 788 table 2.4 arithmetic operations instructions (1) instruction size * function add sub b/w/l rd rs ? rd, rd #imm ? rd performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (subtraction on immediate data and data in a general register cannot be performed in bytes. use the subx or add instruction.) addx subx brd rs c ? rd, rd #imm c ? rd performs addition or subtraction with carry on data in two general registers, or on immediate data and data in a general register. inc dec b/w/l rd 1 ? rd, rd 2 ? rd adds or subtracts the value 1 or 2 to or from data in a general register. (only the value 1 can be added to or subtracted from byte operands.) adds subs lrd 1 ? rd, rd 2 ? rd, rd 4 ? rd adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. daa das b rd (decimal adjust) ? rd decimal-adjusts an addition or subtraction result in a general register by referring to ccr to produce 4-bit bcd data. mulxu b/w rd rs ? rd performs unsigned multiplication on data in two general registers: either 8 bits 8 bits ? 16 bits or 16 bits 16 bits ? 32 bits. mulxs b/w rd rs ? rd performs signed multiplication on data in two general registers: either 8 bits 8 bits ? 16 bits or 16 bits 16 bits ? 32 bits. divxu b/w rd ? rs ? rd performs unsigned division on data in two general registers: either 16 bits ? 8 bits ? 8-bit quotient and 8-bit remainder or 32 bits ? 16 bits ? 16-bit quotient and 16-bit remainder. note: * size refers to the operand size. b: byte w: word l: longword rev. 2.0, 08/02, page 45 of 788 table 2.4 arithmetic operations instructions (2) instruction size * 1 function divxs b/w rd ? rs ? rd performs signed division on data in two general registers: either 16 bits ? 8 bits ? 8-bit quotient and 8-bit remainder or 32 bits ? 16 bits ? 16-bit quotient and 16-bit remainder. cmp b/w/l rd C rs, rd C #imm compares data in a general register with data in another general register or with immediate data, and sets the ccr bits according to the result. neg b/w/l 0 C rd ? rd takes the two's complement (arithmetic complement) of data in a general register. extu w/l rd (zero extension) ? rd extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. exts w/l rd (sign extension) ? rd extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. tas * 2 b @erd C 0, 1 ? ( rev. 2.0, 08/02, page 46 of 788 table 2.5 logic operations instructions instruction size * function and b/w/l rd rs ? rd, rd #imm ? rd performs a logical and operation on a general register and another general register or immediate data. or b/w/l rd rs ? rd, rd #imm ? rd performs a logical or operation on a general register and another general register or immediate data. xor b/w/l rd ? rs ? rd, rd ? #imm ? rd performs a logical exclusive or operation on a general register and another general register or immediate data. not b/w/l ~ rd ? rd takes the one's complement (logical complement) of data in a general register. note: * size refers to the operand size. b: byte w: word l: longword table 2.6 shift instructions instruction size * function shal shar b/w/l rd (shift) ? rd performs an arithmetic shift on data in a general register. 1-bit or 2 bit shift is possible. shll shlr b/w/l rd (shift) ? rd performs a logical shift on data in a general register. 1-bit or 2 bit shift is possible. rotl rotr b/w/l rd (rotate) ? rd rotates data in a general register. 1-bit or 2 bit rotation is possible. rotxl rotxr b/w/l rd (rotate) ? rd rotates data including the carry flag in a general register. 1-bit or 2 bit rotation is possible. note: * size refers to the operand size. b: byte w: word l: longword rev. 2.0, 08/02, page 47 of 788 table 2.7 bit manipulation instructions (1) instruction size * function bset b 1 ? ( rev. 2.0, 08/02, page 48 of 788 table 2.7 bit manipulation instructions (2) instruction size * function bxor b c ? ( rev. 2.0, 08/02, page 49 of 788 table 2.8 branch instructions instruction size function branches to a specified address if a specified condition is true. the branching conditions are listed below. mnemonic description condition bra (bt) always (true) always brn (bf) never (false) never bhi high c z = 0 bls low or same c z = 1 bcc (bhs) carry clear (high or same) c = 0 bcs (blo) carry set (low) c = 1 bne not equal z = 0 beq equal z = 1 bvc overflow clear v = 0 bvs overflow set v = 1 bpl plus n = 0 bmi minus n = 1 bge greater or equal n ? v = 0 blt less than n ? v = 1 bgt greater than z (n ? v) = 0 ble less or equal z (n ? v) = 1 bcc jmp branches unconditionally to a specified address. bsr branches to a subroutine at a specified address jsr branches to a subroutine at a specified address rts returns from a subroutine rev. 2.0, 08/02, page 50 of 788 table 2.9 system control instructions instruction size * function trapa starts trap-instruction exception handling. rte returns from an exception-handling routine. sleep causes a transition to a power-down state. ldc b/w (eas) ? ccr, (eas) ? exr moves the memory operand contents or immediate data to ccr or exr. although ccr and exr are 8-bit registers, word-size transfers are performed between them and memory. the upper 8 bits are valid. stc b/w ccr ? (ead), exr ? (ead) transfers ccr or exr contents to a general register or memory operand. although ccr and exr are 8-bit registers, word-size transfers are performed between them and memory. the upper 8 bits are valid. andc b ccr #imm ? ccr, exr #imm ? exr logically ands the ccr or exr contents with immediate data. orc b ccr #imm ? ccr, exr #imm ? exr logically ors the ccr or exr contents with immediate data. xorc b ccr ? #imm ? ccr, exr ? #imm ? exr logically exclusive-ors the ccr or exr contents with immediate data. nop pc + 2 ? pc only increments the program counter. note: * size refers to the operand size. b: byte w: word rev. 2.0, 08/02, page 51 of 788 table 2.10 block data transfer instructions instruction size function eepmov.b if r4l 1 0 then repeat @er5 + ? @er6+ r4lC1 ? r4l until r4l = 0 else next; eepmov.w if r4 1 0 then repeat @er5 + ? @er6+ r4C1 ? r4 until r4 = 0 else next; transfers a data block. starting from the address set in er5, transfers data for the number of bytes set in r4l or r4 to the address location set in er6. execution of the next instruction begins as soon as the transfer is completed. 2.6.2 basic instruction formats the h8s/2000 cpu instructions consist of 2-byte (1-word) units. an instruction consists of an operation field (op), a register field (r), an effective address extension (ea), and a condition field (cc). figure 2.11 shows examples of instruction formats. operation field indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. the operation field always includes the first four bits of the instruction. some instructions have two operation fields. register field specifies a general register. address registers are specified by 3 bits, and data registers by 3 bits or 4 bits. some instructions have two register fields, and some have no register field. effective address extension 8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. condition field specifies the branching condition of bcc instructions. rev. 2.0, 08/02, page 52 of 788 op op rn rm nop, rts add.b rn, rm mov.b @(d:16, rn), rm rn rm op ea (disp) op cc ea (disp) bra d:16 (1) operation field only (2) operation field and register fields (3) operation field, register fields, and effective address extension (4) operation field, effective address extension, and condition field figure 2.11 instruction formats (examples) 2.7 addressing modes and effective address calculation the h8s/2000 cpu supports the eight addressing modes listed in table 2.11. each instruction uses a subset of these addressing modes. arithmetic and logic operations instructions can use the register direct and immediate addressing modes. data transfer instructions can use all addressing modes except program-counter relative and memory indirect. bit manipulation instructions can use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (bset, bclr, bnot, and btst instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. table 2.11 addressing modes no. addressing mode symbol 1 register direct rn 2 register indirect @ern 3 register indirect with displacement @(d:16,ern)/@(d:32,ern) 4 register indirect with post-increment register indirect with pre-decrement @ern+ @Cern 5 absolute address @aa:8/@aa:16/@aa:24/@aa:32 6 immediate #xx:8/#xx:16/#xx:32 7 program-counter relative @(d:8,pc)/@(d:16,pc) 8 memory indirect @@aa:8 rev. 2.0, 08/02, page 53 of 788 2.7.1 register directrn the register field of the instruction code specifies an 8-, 16-, or 32-bit general register which contains the operand. r0h to r7h and r0l to r7l can be specified as 8-bit registers. r0 to r7 and e0 to e7 can be specified as 16-bit registers. er0 to er7 can be specified as 32-bit registers. 2.7.2 register indirect@ern the register field of the instruction code specifies an address register (ern) which contains the address of a memory operand. if the address is a program instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (h'00). 2.7.3 register indirect with displacement@(d:16, ern) or @(d:32, ern) a 16-bit or 32-bit displacement contained in the instruction code is added to an address register (ern) specified by the register field of the instruction, and the sum gives the address of a memory operand. a 16-bit displacement is sign-extended when added. 2.7.4 register indirect with post-increment or pre-decrement@ern+ or @-ern register indirect with post-increment@ern+: the register field of the instruction code specifies an address register (ern) which contains the address of a memory operand. after the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. the value added is 1 for byte access, 2 for word access, and 4 for longword access. for word or longword transfer instructions, the register value should be even. register indirect with pre-decrement@-ern: the value 1, 2, or 4 is subtracted from an address register (ern) specified by the register field in the instruction code, and the result becomes the address of a memory operand. the result is also stored in the address register. the value subtracted is 1 for byte access, 2 for word access, and 4 for longword access. for word or longword transfer instructions, the register value should be even. 2.7.5 absolute address@aa:8, @aa:16, @aa:24, or @aa:32 the instruction code contains the absolute address of a memory operand. the absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). table 2.12 indicates the accessible absolute address ranges. to access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. for an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (h'ffff). for a 16-bit absolute address, the upper 16 bits are a sign extension. for a 32-bit absolute address, the entire address space is accessed. rev. 2.0, 08/02, page 54 of 788 a 24-bit absolute address (@aa:24) indicates the address of a program instruction. the upper 8 bits are all assumed to be 0 (h'00). table 2.12 absolute address access ranges absolute address normal mode advanced mode 8 bits (@aa:8) h'ff00 to h'ffff h'ffff00 to h'ffffff 16 bits (@aa:16) h'000000 to h'007fff, h'ff8000 to h'ffffff data address 32 bits (@aa:32) program instruction address 24 bits (@aa:24) h'0000 to h'ffff h'000000 to h'ffffff 2.7.6 immediate#xx:8, #xx:16, or #xx:32 the 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data contained in an instruction code can be used directly as an operand. the adds, subs, inc, and dec instructions implicitly contain immediate data in their instruction codes. some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. the trapa instruction contains 2-bit immediate data in its instruction code, specifying a vector address. 2.7.7 program-counter relative@(d:8, pc) or @(d:16, pc) this mode can be used by the bcc and bsr instructions. an 8-bit or 16-bit displacement contained in the instruction code is sign-extended to 24 bits and added to the 24-bit address indicated by the pc value to generate a 24-bit branch address. only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (h'00). the pc value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is C126 to +128 bytes (C63 to +64 words) or C32766 to +32768 bytes (C16383 to +16384 words) from the branch instruction. the resulting value should be an even number. rev. 2.0, 08/02, page 55 of 788 2.7.8 memory indirect@@aa:8 this mode can be used by the jmp and jsr instructions. the instruction code contains an 8-bit absolute address specifying a memory operand which contains a branch address. the upper bits of the 8-bit absolute address are all assumed to be 0, so the address range is 0 to 255 (h'0000 to h'00ff in normal mode, h'000000 to h'0000ff in advanced mode). in normal mode, the memory operand is a word operand and the branch address is 16 bits long. in advanced mode, the memory operand is a longword operand, the first byte of which is assumed to be 0 (h'00). note that the top area of the address range in which the branch address is stored is also used for the exception vector area. for further details, refer to section 4, exception handling. if an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or the instruction code to be fetched at the address preceding the specified address. (for further information, see section 2.5.2, memory data formats.) specified by @aa:8 specified by @aa:8 branch address branch address reserved (a) normal mode (b) advanced mode figure 2.12 branch address specification in memory indirect addressing mode rev. 2.0, 08/02, page 56 of 788 2.7.9 effective address calculation table 2.13 indicates how effective addresses are calculated in each addressing mode. in normal mode, the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. table 2.13 effective address calculation (1) no 1 offset 1 2 4 r op 31 0 31 23 2 3 register indirect with displacement @(d:16,ern) or @(d:32,ern) 4 r op disp r op rm op rn 31 0 31 0 r op don't care 31 23 31 0 don't care 31 0 disp 31 0 31 0 31 23 31 0 don't care 31 23 31 0 don't care 24 24 24 24 addressing mode and instruction format effective address calculation effective address (ea) register direct (rn) general register contents general register contents general register contents general register contents sign extension register indirect (@ern) register indirect with post-increment or pre-decrement ? register indirect with post-increment @ern+ ? register indirect with pre-decrement @-ern 1, 2, or 4 1, 2, or 4 operand size byte word longword operand is general register contents. rev. 2.0, 08/02, page 57 of 788 table 2.13 effective address calculation (2) no 5 op 31 23 31 0 don't care abs @aa:8 7 h'ffff op 31 23 31 0 don't care @aa:16 op @aa:24 @aa:32 abs 15 16 31 23 31 0 don't care 31 23 31 0 don't care abs op abs 6 op imm #xx:8/#xx:16/#xx:32 8 24 24 24 24 addressing mode and instruction format absolute address immediate effective address calculation effective address (ea) sign extension operand is immediate data. 31 23 7 program-counter relative @(d:8,pc)/@(d:16,pc) memory indirect @@aa:8 ? ? 31 0 don't care 23 0 disp 0 31 23 31 0 don't care disp op 23 op 8 abs 31 0 abs h'000000 7 8 0 15 31 23 31 0 don't care 15 h'00 16 op abs 31 0 abs h'000000 7 8 0 31 24 24 24 pc contents sign extension memory contents memory contents rev. 2.0, 08/02, page 58 of 788 2.8 processing states the h8s/2000 cpu has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and program stop state. figure 2.13 indicates the state transitions. reset state in this state the cpu and on-chip peripheral modules are all initialized and stopped. when the 5(6 input goes low, all current processing stops and the cpu enters the reset state. all interrupts are masked in the reset state. reset exception handling starts when the 5(6 signal changes from low to high. for details, refer to section 4, exception handling. the reset state can also be entered by a watchdog timer overflow. exception-handling state the exception-handling state is a transient state that occurs when the cpu alters the normal processing flow due to an exception source, such as, a reset, trace, interrupt, or trap instruction. the cpu fetches a start address (vector) from the exception vector table and branches to that address. for further details, refer to section 4, exception handling. program execution state in this state the cpu executes program instructions in sequence. bus-released state in a product which has a bus master other than the cpu, such as a data transfer controller (dtc), the bus-released state occurs when the bus has been released in response to a bus request from a bus master other than the cpu. while the bus is released, the cpu halts operations. for details, see section 6, bus controller (bsc). program stop state this is a power-down state in which the cpu stops operating. the program stop state occurs when a sleep instruction is executed or the cpu enters hardware standby mode. for details, refer to section 26, power-down modes. rev. 2.0, 08/02, page 59 of 788 end of bus request bus request program execution state bus-released state sleep mode exception-handling state software standby mode = high reset state = high, = low hardware standby mode * 2 power-down state * 3 * 1 notes: 1. 2. 3. from any state except hardware standby mode, a transition to the reset state occurs whenever goes low. a transition can also be made to the reset state when the watchdog timer overflows. from any state, a transition to hardware standby mode occurs when goes low. the power-down state also includes watch mode, subactive mode, subsleep mode, etc. for details, refer to section 26, power-down modes. sleep instruction with lson = 0, ssby = 0 interrupt request end of bus request bus request request for exception handling end of exception handling external interrupt request sleep instruction with lson = 0, pss = 0, ssby = 1 figure 2.13 state transitions rev. 2.0, 08/02, page 60 of 788 2.9 usage notes 2.9.1 note on tas instruction usage when using the tas instruction, use registers er0, er1, er4 and er5. the tas instruction is not generated by the hitachi h8s and h8/300 series c/c++ compilers. when the tas instruction is used as a user-defined intrinsic function, use registers er0, er1, er4 and er5. 2.9.2 note on stm/ldm instruction usage er7 is not used as the register that can be saved (stm)/restored (ldm) when using stm/ldm instruction, because er7 is the stack pointer. two, three, or four registers can be saved/restored by one stm/ldm instruction. the following ranges can be specified in the register list. two registers: er0er1, er2er3, or er4er5 three registers: er0er2 or er4er6 four registers: er0er3 the stm/ldm instruction including er7 is not generated by the hitachi h8s and h8/300 series c/c++ compilers. 2.9.3 note on bit manipulation instructions the bset, bclr, bnot, bst, and bist instructions read data from the specified address in byte units, manipulate the data of the target bit, and write data to the same address again in byte units. special care is required when using these instructions in cases where a register containing a write-only bit is used or a bit is directly manipulated for a port, because this may rewrite data of a bit other than the bit to be manipulated. example: the bclr instruction is executed for ddr in port 4. p47 and p46 are input pins, with a low-level signal input at p47 and a high-level signal input at p46. p45 to p40 are output pins and output low-level signals. the following shows an example in which p40 is set to be an input pin with the bclr instruction. rev. 2.0, 08/02, page 61 of 788 prior to executing bclr: p47 p46 p45 p44 p43 p42 p41 p40 input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level ddr 00111111 dr 10000000 bclr instruction executed: bclr #0, @p4ddr the bclr instruction is executed for ddr in port 4. after executing bclr: p47 p46 p45 p44 p43 p42 p41 p40 input/output output output output output output output output input pin state low level high level low level low level low level low level low level high level ddr 1 111111 0 dr 1 0 00000 0 operation: 1. when the bclr instruction is executed, first the cpu reads p4ddr. since p4ddr is a write-only register, so the cpu reads hff. in this example p4ddr has a value of h'3f, but the value read by the cpu is h'ff. 2. the cpu clears bit 0 of the read data to 0, changing data to h'fe. 3. the cpu writes h'fe to ddr, completing execution of bclr. as a result of the bclr instruction, bit 0 in ddr is set to 0, and p40 becomes an input pin. however, bits 7 and 6 of ddr are modified to 1, therefore p47 and p46 become output pins. rev. 2.0, 08/02, page 62 of 788 2.9.4 eepmov instruction 1. eepmov is a block-transfer instruction and transfers the byte size of data indicated by r4l, which starts from the address indicated by r5, to the address indicated by r6. r6 r6 + r4l r5 r5 + r4l 2. set r4l and r6 so that the end address of the destination address (value of r6 + r4l) does not exceed h'ffff (the value of r6 must not change from h'ffff to h'0000 during execution). invalid h'ffff r6 r6 + r4l r5 r5 + r4l rev. 2.0, 08/02, page 63 of 788 section 3 mcu operating modes 3.1 mcu operating mode selection this lsi has three operating modes (modes 1 to 3). the operating mode is determined by the setting of the mode pins (md1 and md0). table 3.1 shows the mcu operating mode selection. table 3.1 lists the mcu operating modes. table 3.1 mcu operating mode selection mcu operating mode md1 md0 cpu operating mode description on-chip rom 00 1 0 1 normal expanded mode with on-chip rom disabled disabled 2 0 advanced expanded mode with on-chip rom enabled single-chip mode 3 1 1 normal expanded mode with on-chip rom enabled single-chip mode enabled mode 1 is an expanded mode that allows access to external memory and peripheral devices. with modes 2 and 3, operation begins in single-chip mode after reset release, but a transition can be made to external expansion mode by setting the expe bit in mdcr to 1. mode 0 cannot be used in this lsi. thus, mode pins should be set to enable mode 1, 2 or 3 in normal program execution state. mode pins should not be changed during operation. 3.2 register descriptions the following registers are related to the operating mode. for details on the bus control register (bcr), refer to section 6.3.1, bus control register (bcr). mode control register (mdcr) system control register (syscr) serial timer control register (stcr) rev. 2.0, 08/02, page 64 of 788 3.2.1 mode control register (mdcr) mdcr is used to set an operating mode and to monitor the current operating mode. bit bit name initial value r/w description 7 expe * r/w * extended mode enable specifies extended mode. fixed to 1 and cannot be modified in mode 1. readable/writable and the initial value is 0 in mode 2 or 3. 0: single-chip mode 1: extended mode 6 to 2 all 0 r reserved these bits are always read as 0. these bits cannot be modified. 1 0 mds1 mds0 * * r r mode select 1 and 0 these bits indicate the input levels at mode pins (md1 and md0) (the current operating mode). bits mds1 and mds0 correspond to md1 and md0, respectively. these bits are read-only bits and they cannot be written to. the mode pin (md1 and md0) input levels are latched into these bits when mdcr is read. these latches are canceled by a reset. note: * the initial values are determined by the settings of the md1 and md0 pins. rev. 2.0, 08/02, page 65 of 788 3.2.2 system control register (syscr) syscr selects a system pin function, monitors a reset source, selects the interrupt control mode and the detection edge for nmi, pin location selection, enables or disables register access to the on-chip peripheral modules, and enables or disables on-chip ram address space. bit bit name initial value r/w description 7 cs2e 0 r/w chip select 2 enable specifies the location of the control pin ( &6 5 ) of the host interface together with the fga20e bit in hicr. see section 18, host interface x-bus interface (xbs), for details. 6 iose 0 r/w ios enable enables or disables $6 / ,26 pin function in extended mode. 0: $6 pin outputs low when an external area is accessed. 1: ,26 pin outputs low when a specified address of addresses h(ff)f000 to h(ff)f7ff is accessed. 5 4 intm1 intm0 0 0 r r/w these bits select the control mode of the interrupt controller. for details on the interrupt control modes and interrupt control select modes 1 and 0, see section 5.6, interrupt control modes and interrupt operation. 00: interrupt control mode 0 01: interrupt control mode 1 10: setting prohibited 11: setting prohibited 3 xrst 1 r external reset this bit indicates the reset source. a reset is caused by an external reset input, or when the watchdog timer overflows. 0: a reset is caused when the watchdog timer overflows. 1: a reset is caused by an external reset. rev. 2.0, 08/02, page 66 of 788 bit bit name initial value r/w description 2 nmieg 0 r/w nmi edge select selects the valid edge of the nmi interrupt input. 0: an interrupt is requested at the falling edge of nmi input 1: an interrupt is requested at the rising edge of nmi input 1 hie 0 r/w host interface enable controls cpu access to the host interface registers (hicr, idr1, odr1, str1, idr2, odr2, and str2), the keyboard matrix interrupt and mos input pull-up control registers (kmimr, kmpcr, and kmimra), the 8-bit timer (tmr_x and tmr_y) registers (tcr_x/tcr_y, tcsr_x/tcsr_y, ticrr/tcora_y, ticrf/tcorb_y, tcnt_x/tcnt_y, tcorc/tisr, tcora_x, and tcorb_x), and the timer connection registers (tconri, tconro, tconrs, and sedgr). 0: in areas h'(ff)fff0 to h'(ff)fff7 and h'(ff)fffc to h'(ff)ffff, cpu access to 8-bit timer (tmr_x and tmr_y) registers and timer connection registers is permitted 1: in areas h'(ff)fff0 to h'(ff)fff7 and h'(ff)fffc to h'(ff)ffff, cpu access to host interface registers and keyboard matrix interrupt and mos input pull-up control registers is permitted 0 rame 1 r/w ram enable enables or disables on-chip ram. the rame bit is initialized when the reset state is released. 0: on-chip ram is disabled 1: on-chip ram is enabled rev. 2.0, 08/02, page 67 of 788 3.2.3 serial timer control register (stcr) stcr enables or disables register access, iic operating mode, and on-chip flash memory, and selects the input clock of the timer counter. bit bit name initial value r/w description 7 iics 0 r/w i 2 c extra buffer select specifies bits 7 to 4 of port a as output buffers similar to slc and sda. these pins are used to implement an i 2 c interface only by software. 0: pa7 to pa4 are normal input/output pins. 1: pa7 to pa4 are input/output pins enabling bus driving. 6 5 iicx1 iicx0 0 0 r/w r/w i 2 c transfer rate select 1 and 0 these bits control the iic operation. these bits select a transfer rate in master mode together with bits cks2 to cks0 in the i 2 c bus mode register (icmr). for details on the transfer rate, refer to table 16.3. 4 iice 0 r/w i 2 c master enable enables or disables cpu access for iic registers (iccr, icsr, icdr/sarx, icmr/sar), pwmx registers (dadrah/dacr, dadral, dadrbh/dacnth, dadrbl/dacntl), and sci registers (smr, brr, scmr). 0: sci_1 registers are accessed in an area from h(ff)ff88 to h(ff)ff89 and from h(ff)ff8e to h(ff)ff8f. sci_2 registers are accessed in an area from h(ff)ffa0 to h(ff)ffa1 and from h(ff)ffa6 to h(ff)ffa7. sci_0 registers are accessed in an area from h(ff)ffd8 to h(ff)ffd9 and from h(ff)ffde to h(ff)ffdf. 1: iic_1 registers are accessed in an area from h(ff)ff88 to h(ff)ff89 and from h(ff)ff8e to h(ff)ff8f. pwmx registers are accessed in an area from h(ff)ffa0 to h(ff)ffa1 and from h(ff)ffa6 to h(ff)ffa7. iic_0 registers are accessed in an area from h(ff)ffd8 to h(ff)ffd9 and from h(ff)ffde to h(ff)ffdf. rev. 2.0, 08/02, page 68 of 788 bit bit name initial value r/w description 3 flshe 0 r/w flash memory control register enable enables or disables cpu access for flash memory registers (flmcr1, flmcr2, ebr1, ebr2), control registers in power-down state (sbycr, lpwrcr, mstpcrh, mstpcrl), and control registers of on- chip peripheral modules (pcsr, syscr2). 0: registers in power-down state and control registers of on-chip peripheral modules are accessed in an area from h(ff)ff80 to h(ff)ff87. 1: control registers of flash memory are accessed in an area from h(ff)ff80 to h(ff)ff87. 2 0 r/(w)reserved the initial value should not be changed. 1 0 icks1 icks0 0 0 r/w r/w internal clock source select 1, 0 these bits select a clock to be input to the timer counter (tcnt) and a count condition together with bits cks2 to cks0 in the timer control register (tcr). for details, refer to section 12.3.4, timer control register (tcr). rev. 2.0, 08/02, page 69 of 788 3.3 operating mode descriptions 3.3.1 mode 1 the cpu can access a 64-kbyte address space in normal mode. the on-chip rom is disabled. ports 1 and 2 function as an address bus, port 3 functions as a data bus, and part of port 9 carries bus control signals. clearing the abw bit to 0 in the wscr register makes port b a data bus. 3.3.2 mode 2 the cpu can access a 16-mbyte address space in advanced mode. the on-chip rom is enabled. after a reset, the lsi is set to single-chip mode. to access an external address space, bit expe in mdcr should be set to 1. when the expe bit in mdcr is set to 1, ports 1, 2 and a function as input ports after a reset. ports 1, 2 and a output an address by setting 1 to the corresponding port data direction register (ddr). port 3 functions as a data bus, and parts of port 9 carry bus control signals. port b functions as a data bus when the abw bit in wscr is cleared to 0. 3.3.3 mode 3 the cpu can access a 64-kbyte address space in normal mode. the on-chip rom is enabled. the cpu can access a 56-kbyte address space in mode 3. after a reset, the lsi is set to single-chip mode. to access an external address space, bit expe in mdcr should be set to 1. when the expe bit in mdcr is set to 1, ports 1 and 2 function as input ports after a reset. ports 1 and 2 function as an address bus by setting 1 to the corresponding port data direction register (ddr). port 3 functions as a data bus, and parts of port 9 carry bus control signals. port b functions as a data bus when the abw bit in wscr is cleared to 0. 3.3.4 pin functions in each operating mode pin functions of ports 1 to 3, 9, a, and b depend on the operating mode. table 3.2 shows pin functions in each operating mode. rev. 2.0, 08/02, page 70 of 788 table 3.2 pin functions in each mode port mode 1 mode 2 mode 3 port 1 a p * /a p * /a port 2 a p * /a p * /a port a p p * /a p port 3 d p * /d p * /d port b p * /d p * /d p * /d p97 p * /c p * /c p * /c p96 c * /p p * /c p * /c p95 to p93 c p * /c p * /c p92 to p91 p p p port 9 p90 p * /c p * /c p * /c port c to port g p p p legend p: i/o port a: address bus output d: data bus i/o c: control signals, clock i/o * : immediately after reset rev. 2.0, 08/02, page 71 of 788 3.4 address map in each operating mode figures 3.1 to 3.10 show the address map in each operating mode. note: these areas can be used as an external address space by clearing bit rame in syscr to 0. mode 2 ( expe = 0) advanced mode single-chip mode h'01ffff h'020000 h'000000 on-chip rom external address space on-chip rom mode 2 ( expe = 1) advanced mode extended mode with on-chip rom enabled internal i/o registers 2 on-chip ram internal i/o registers 1 on-chip ram (128 bytes) internal i/o registers 2 on-chip ram * internal i/o registers 1 h'ffe080 h'fffeff h'ffffff h'fffe50 h'ffff7f h'ffff80 h'ffff00 on-chip ram (128 bytes) * external address space internal i/o registers 3 internal i/o registers 3 h'fff800 h'fffe4f h'fff7ff h'ffefff h'fff000 reserved area reserved area h'0000 external address space mode 1 normal mode extended mode with on-chip rom disabled internal i/o registers 2 on-chip ram * internal i/o registers 1 h'e080 h'feff h'ffff h'fe50 h'ff7f h'ff80 h'ff00 on-chip ram (128 bytes) * external address space internal i/o registers 3 h'f800 h'fe4f h'f7ff h'efff h'f000 h'00ffff h'01ffff h'000000 h'ffe080 h'fffeff h'ffffff h'fffe50 h'ffff7f h'ffff80 h'ffff00 h'fff800 h'fffe4f h'ffefff h'00ffff figure 3.1 address map for h8s/2140b and h8s/2160b (1) rev. 2.0, 08/02, page 72 of 788 note: these areas can be used as an external address space by clearing bit rame in syscr to 0. mode 3 ( expe = 0) normal mode single-chip mode h'dfff h'0000 h'dfff h'0000 on-chip rom external address space on-chip rom mode 3 ( expe = 1) normal mode extended mode with on-chip rom enabled internal i/o registers 2 on-chip ram internal i/o registers 1 h'efff h'e080 h'feff h'ffff h'fe50 h'ff7f h'ff80 h'ff00 on-chip ram (128 bytes) internal i/o registers 2 on-chip ram * internal i/o registers 1 h'e080 h'feff h'ffff h'fe50 h'ff7f h'ff80 h'ff00 on-chip ram (128 bytes) * external address space internal i/o registers 3 internal i/o registers 3 h'f800 h'fe4f h'f800 h'fe4f h'f7ff h'efff h'f000 figure 3.2 address map for h8s/2140b and h8s/2160b (2) rev. 2.0, 08/02, page 73 of 788 note: these areas can be used as an external address space by clearing bit rame in syscr to 0. mode 2 ( expe = 0) advanced mode single-chip mode h'01ffff h'020000 h'000000 on-chip rom external address space on-chip rom mode 2 ( expe = 1) advanced mode extended mode with on-chip rom enabled internal i/o registers 2 on-chip ram internal i/o registers 1 on-chip ram (128 bytes) internal i/o registers 2 on-chip ram * internal i/o registers 1 h'ffe080 h'fffeff h'ffffff h'fffe50 h'ffff7f h'ffff80 h'ffff00 on-chip ram (128 bytes) * external address space internal i/o registers 3 internal i/o registers 3 h'fff800 h'fffe4f h'fff7ff h'ffefff h'fff000 h'0000 external address space mode 1 normal mode extended mode with on-chip rom disabled internal i/o registers 2 on-chip ram * internal i/o registers 1 h'e080 h'feff h'ffff h'fe50 h'ff7f h'ff80 h'ff00 on-chip ram (128 bytes) * external address space internal i/o registers 3 h'f800 h'fe4f h'f7ff h'efff h'f000 h'01ffff h'000000 h'ffe080 h'fffeff h'ffffff h'fffe50 h'ffff7f h'ffff80 h'ffff00 h'fff800 h'fffe4f h'ffefff figure 3.3 address map for h8s/2141b and h8s/2161b (1) rev. 2.0, 08/02, page 74 of 788 note: these areas can be used as an external address space by clearing bit rame in syscr to 0. mode 3 ( expe = 0) normal mode single-chip mode h'dfff h'0000 h'dfff h'0000 on-chip rom external address space on-chip rom mode 3 ( expe = 1) normal mode extended mode with on-chip rom enabled internal i/o registers 2 on-chip ram internal i/o registers 1 h'efff h'e080 h'feff h'ffff h'fe50 h'ff7f h'ff80 h'ff00 on-chip ram (128 bytes) internal i/o registers 2 on-chip ram * internal i/o registers 1 h'e080 h'feff h'ffff h'fe50 h'ff7f h'ff80 h'ff00 on-chip ram (128 bytes) * external address space internal i/o registers 3 internal i/o registers 3 h'f800 h'fe4f h'f800 h'fe4f h'f7ff h'efff h'f000 figure 3.4 address map for h8s/2141b and h8s/2161b (2) rev. 2.0, 08/02, page 75 of 788 note: these areas can be used as an external address space by clearing bit rame in syscr to 0. mode 2 ( expe = 0) advanced mode single-chip mode h'03ffff h'040000 h'000000 on-chip rom external address space on-chip rom mode 2 ( expe = 1) advanced mode extended mode with on-chip rom enabled internal i/o registers 2 on-chip ram internal i/o registers 1 on-chip ram (128 bytes) internal i/o registers 2 on-chip ram * internal i/o registers 1 h'ffd080 h'fffeff h'ffffff h'fffe50 h'ffff7f h'ffff80 h'ffff00 on-chip ram (128 bytes) * external address space internal i/o registers 3 internal i/o registers 3 h'fff800 h'fffe4f h'fff7ff h'ffefff h'fff000 h'0000 external address space mode 1 normal mode extended mode with on-chip rom disabled internal i/o registers 2 on-chip ram * internal i/o registers 1 h'e080 h'feff h'ffff h'fe50 h'ff7f h'ff80 h'ff00 on-chip ram (128 bytes) * external address space internal i/o registers 3 h'f800 h'fe4f h'f7ff h'efff h'f000 h'03ffff h'000000 h'ffd080 h'fffeff h'ffffff h'fffe50 h'ffff7f h'ffff80 h'ffff00 h'fff800 h'fffe4f h'ffefff figure 3.5 address map for h8s/2145bv (1) rev. 2.0, 08/02, page 76 of 788 note: these areas can be used as an external address space by clearing bit rame in syscr to 0. mode 3 ( expe = 0) normal mode single-chip mode h'dfff h'0000 h'dfff h'0000 on-chip rom external address space on-chip rom mode 3 ( expe = 1) normal mode extended mode with on-chip rom enabled internal i/o registers 2 on-chip ram internal i/o registers 1 h'efff h'e080 h'feff h'ffff h'fe50 h'ff7f h'ff80 h'ff00 on-chip ram (128 bytes) internal i/o registers 2 on-chip ram * internal i/o registers 1 h'e080 h'feff h'ffff h'fe50 h'ff7f h'ff80 h'ff00 on-chip ram (128 bytes) * external address space internal i/o registers 3 internal i/o registers 3 h'f800 h'fe4f h'f800 h'fe4f h'f7ff h'efff h'f000 figure 3.6 address map for h8s/2145bv (2) rev. 2.0, 08/02, page 77 of 788 note: these areas can be used as an external address space by clearing bit rame in syscr to 0. mode 2 ( expe = 0) advanced mode single-chip mode h'03ffff h'040000 h'000000 on-chip rom external address space on-chip rom mode 2 ( expe = 1) advanced mode extended mode with on-chip rom enabled internal i/o registers 2 on-chip ram internal i/o registers 1 on-chip ram (128 bytes) internal i/o registers 2 on-chip ram * internal i/o registers 1 h'ffd080 h'fffeff h'ffffff h'fffe50 h'ffff7f h'ffff80 h'ffff00 on-chip ram (128 bytes) * external address space reserved area h'fff800 h'fffe4f h'fff7ff h'ffefff h'fff000 h'0000 external address space mode 1 normal mode extended mode with on-chip rom disabled internal i/o registers 2 on-chip ram * internal i/o registers 1 h'e080 h'feff h'ffff h'fe50 h'ff7f h'ff80 h'ff00 on-chip ram (128 bytes) * external address space h'f800 h'fe4f h'f7ff h'efff h'f000 h'03ffff h'000000 h'ffd080 h'fffeff h'ffffff h'fffe50 h'ffff7f h'ffff80 h'ffff00 h'ffefff reserved area figure 3.7 address map for h8s/2148b (1) rev. 2.0, 08/02, page 78 of 788 note: these areas can be used as an external address space by clearing bit rame in syscr to 0. mode 3 ( expe = 0) normal mode single-chip mode h'dfff h'0000 h'dfff h'0000 on-chip rom external address space on-chip rom mode 3 ( expe = 1) normal mode extended mode with on-chip rom enabled internal i/o registers 2 on-chip ram internal i/o registers 1 h'efff h'e080 h'feff h'ffff h'fe50 h'ff7f h'ff80 h'ff00 on-chip ram (128 bytes) internal i/o registers 2 on-chip ram * internal i/o registers 1 h'e080 h'feff h'ffff h'fe50 h'ff7f h'ff80 h'ff00 on-chip ram (128 bytes) * external address space reserved area h'f800 h'fe4f h'f7ff h'efff h'f000 figure 3.8 address map for h8s/2148b (2) rev. 2.0, 08/02, page 79 of 788 section 4 exception handling 4.1 exception handling types and priority as table 4.1 indicates, exception handling may be caused by a reset, interrupt, direct transition, or trap instruction. exception handling is prioritized as shown in table 4.1. if two or more exceptions occur simultaneously, they are accepted and processed in order of priority. table 4.1 exception types and priority priority exception type start of exception handling reset starts immediately after a low-to-high transition of the 5(6 pin, or when the watchdog timer overflows. interrupt starts when execution of the current instruction or exception handling ends, if an interrupt request has been issued. interrupt detection is not performed on completion of andc, orc, xorc, or ldc instruction execution, or on completion of reset exception handling. high direct transition starts when a direction transition occurs as the result of sleep instruction execution. low trap instruction started by execution of a trap (trapa) instruction. trap instruction exception handling requests are accepted at all times in program execution state. rev. 2.0, 08/02, page 80 of 788 4.2 exception sources and exception vector table different vector addresses are assigned to different exception sources. table 4.2 lists the exception sources and their vector addresses. table 4.2 exception handling vector table vector address exception source vector number normal mode advanced mode reset 0 h'0000 to h'0001 h'000000 to h'000003 reserved for system use 1 ? 5 h'0002 to h'0003 | h'000a to h'000b h'000004 to h'000007 | h'000014 to h'000017 direct transition 6 h'000c to h'000d h'000018 to h'00001b external interrupt (nmi) 7 h'000e to h'000f h'00001c to h'00001f 8 h'0010 to h'0011 h'000020 to h'000023 9 h'0012 to h'0013 h'000024 to h'000027 10 h'0014 to h'0015 h'000028 to h'00002b trap instruction (four sources) 11 h'0016 to h'0017 h'00002c to h'00002f reserved for system use 12 ? 15 h'0018 to h'0019 | h'001e to h'001f h'000030 to h'000033 | h'00003c to h'00003f irq0 16 h'0020 to h'0021 h'000040 to h'000043 irq1 17 h'0022 to h'0023 h'000044 to h'000047 irq2 18 h'0024 to h'0025 h'000048 to h'00004b irq3 19 h'0026 to h'0027 h'00004c to h'00004f irq4 20 h'0028 to h'0029 h'000050 to h'000053 irq5 21 h'002a to h'002b h'000054 to h'000057 irq6 22 h'002c to h'002d h'000058 to h'00005b external interrupt irq7 23 h'002e to h'002f h'00005c to h'00005f internal interrupt * 24 ? 107 h'0030 to h'0031 ? h'00de to h'00df h'000060 to h'000063 ? h'0001bc to h'0001bf note: * for details on the internal interrupt vector table, see section 5.5, interrupt exception handling vector table. rev. 2.0, 08/02, page 81 of 788 4.3 reset a reset has the highest exception priority. when the 5(6 pin goes low, all processing halts and this lsi enters the reset. to ensure that this lsi is reset, hold the 5(6 pin low for at least 20 ms at power-on. to reset the chip during operation, hold the 5(6 pin low for at least 20 states. a reset initializes the internal state of the cpu and the registers of on-chip peripheral modules. the chip can also be reset by overflow of the watchdog timer. for details, see section 14, watchdog timer (wdt). 4.3.1 reset exception handling when the 5(6 pin goes high after being held low for the necessary time, this lsi starts reset exception handling as follows: 1. the internal state of the cpu and the registers of the on-chip peripheral modules are initialized and the i bit is set to 1 in ccr. 2. the reset exception handling vector address is read and transferred to the pc, and program execution starts from the address indicated by the pc. figure 4.1 shows an example of the reset sequence. ? internal address bus internal read signal internal write signal internal data bus vector fetch (1) reset exception handling vector address ((1) = h'0000) (2) start address (contents of reset exception handling vector address) (3) start address ((3) = (2)) (4) first program instruction (1) (3) high internal processing prefetch of first program instruction (2) (4) figure 4.1 reset sequence (mode 3) rev. 2.0, 08/02, page 82 of 788 4.3.2 interrupts after reset if an interrupt is accepted after a reset and before the stack pointer (sp) is initialized, the pc and ccr will not be saved correctly, leading to a program crash. to prevent this, all interrupt requests, including nmi, are disabled immediately after a reset. since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: mov.l #xx: 32, sp). 4.3.3 on-chip peripheral modules after reset is cancelled after a reset is cancelled, the module stop control registers (mstpcr) are initialized, and all modules except the dtc operate in module stop mode. therefore, the registers of on-chip peripheral modules cannot be read from or written to. to read from and write to these registers, clear module stop mode. 4.4 interrupt exception handling interrupts are controlled by the interrupt controller. the sources to start interrupt exception handling are external interrupt sources (nmi, irq7 to irq0, kin15 to kin0, and wue7 to wue0) and internal interrupt sources from the on-chip peripheral modules. nmi is an interrupt with the highest priority. for details, refer to section 5, interrupt controller. interrupt exception handling is conducted as follows: 1. the values in the program counter (pc) and condition code register (ccr) are saved to the stack. 2. a vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the pc, and program execution begins from that address. 4.5 trap instruction exception handling trap instruction exception handling starts when a trapa instruction is executed. trap instruction exception handling can be executed at all times in the program execution state. trap instruction exception handling is conducted as follows: 1. the values in the program counter (pc) and condition code register (ccr) are saved to the stack. 2. a vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the pc, and program execution starts from that address. the trapa instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. rev. 2.0, 08/02, page 83 of 788 table 4.3 shows the status of ccr after execution of trap instruction exception handling. table 4.3 status of ccr after trap instruction exception handling ccr interrupt control mode i ui 01 111 legend 1: set to 1 : retains value prior to execution 4.6 stack status after exception handling figure 4.2 shows the stack after completion of trap instruction exception handling and interrupt exception handling. ccr ccr * pc (16 bits) sp note: ignored on return. normal mode advanced mode ccr pc (24 bits) sp figure 4.2 stack status after exception handling rev. 2.0, 08/02, page 84 of 788 4.7 usage note when accessing word data or longword data, this lsi assumes that the lowest address bit is 0. the stack should always be accessed in words or longwords, and the value of the stack pointer (sp: er7) should always be kept even. use the following instructions to save registers: push.w rn (or mov.w rn, @-sp) push.l ern (or mov.l ern, @-sp) use the following instructions to restore registers: pop.w rn (or mov.w @sp+, rn) pop.l ern (or mov.l @sp+, ern ) setting sp to an odd value may lead to a malfunction. figure 4.3 shows an example of what happens when the sp value is odd. sp ccr : pc : r1l : sp : condition code register program counter general register r1l stack pointer ccr sp sp r1l h'ffeffa h'ffeffb h'ffeffc h'ffeffd h'ffefff pc pc trapa instruction executed sp set to h'fffeff data saved above sp mov.b r1l, @-er7 executed contents of ccr lost address legend note: this diagram illustrates an example in which the interrupt control mode is 0 in advanced mode. figure 4.3 operation when sp value is odd rev. 2.0, 08/02, page 85 of 788 section 5 interrupt controller 5.1 features two interrupt control modes any of two interrupt control modes can be set by means of the intm1 and intm0 bits in the system control register (syscr). priorities settable with icr an interrupt control register (icr) is provided for setting interrupt priorities. three priority levels can be set for each module for all interrupts except nmi and address break. independent vector addresses all interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. thirty-one external interrupts nmi is the highest-priority interrupt, and is accepted at all times. rising edge or falling edge detection can be selected for nmi. falling-edge, rising-edge, or both-edge detection, or level sensing, can be selected for ,54 : to ,54 3 . the irq6 interrupt is shared by the interrupt from the ,54 9 pin and eight external interrupt inputs ( .,1 : to .,1 3 ), and the irq7 interrupt is shared by the interrupt from the ,54 : pin and sixteen external interrupt inputs ( .,1 48 to .,1 ; and :8( : to :8( 3 ). .,1 48 to .,1 3 and :8( : to :8( 3 can be masked individually by the user program. dtc control the dtc can be activated by an interrupt request. rev. 2.0, 08/02, page 86 of 788 syscr nmi input irq input internal interrupt request swdtend to ibf13 nmieg intm1, intm0 nmi input irq input isr iscr ier icr interrupt controller priority check interrupt request vector number i, ui ccr cpu icr iscr ier isr kmimr wuemr syscr : interrupt control register : irq sense control register : irq enable register : irq status register : keyboard matrix interrupt mask register : wake-up event interrupt mask register : system control register legend: kin and wue input kmimr wuemr kin input wue input figure 5.1 block diagram of interrupt controller rev. 2.0, 08/02, page 87 of 788 5.2 input/output pins table 5.1 summarizes the pins of the interrupt controller. table 5.1 pin configuration symbol i/o function nmi input nonmaskable external interrupt rising edge or falling edge can be selected ,54 : to ,54 3 input maskable external interrupts rising edge, falling edge, or both edges, or level sensing, can be selected individually for each pin. .,1 48 to .,1 3 input maskable external interrupts falling edge or level sensing can be selected. :8( : to :8( 3 * input maskable external interrupts falling edge or level sensing can be selected. note: * not supported by the h8s/2148b. 5.3 register descriptions the interrupt controller has the following registers. for details on the system control register (syscr), refer to section 3.2.2, system control register (syscr). interrupt control registers a to c (icra to icrc) address break control register (abrkcr) break address registers a to c (bara to barc) irq sense control registers (iscrh, iscrl) irq enable register (ier) irq status register (isr) keyboard matrix interrupt mask registers (kmimra, kmimr) wake-up event interrupt mask register (wuemrb) rev. 2.0, 08/02, page 88 of 788 5.3.1 interrupt control registers a to c (icra to icrc) the icr registers set interrupt control levels for interrupts other than nmi and address breaks. the correspondence between interrupt sources and icra to icrc settings is shown in table 5.2. bit bit name initial value r/w description 7 to 0 icrn7 to ircn0 all 0 r/w interrupt control level 0: corresponding interrupt source is interrupt control level 0 (no priority) 1: corresponding interrupt source is interrupt control level 1 (priority) n: a to c table 5.2 correspondence between interrupt source and icr register bit bit name icra icrb icrc 7 icrn7 irq0 a/d converter sci_0 6 icrn6 irq1 frt sci_1 5 icrn5 irq2, irq3 sci_2 4 icrn4 irq4, irq5 iic_0 3 icrn3 irq6, irq7 tmr_0 iic_1 2 icrn2 dtc tmr_1 1 icrn1 wdt_0 tmr_x , tmr_y lpc * 0 icrn0 wdt_1 xbs, keyboard buffer controller n: a to c ? : reserved. the write value should always be 0. note: * on products not including lpc, this bit is reserved. the write value should always be 0. rev. 2.0, 08/02, page 89 of 788 5.3.2 address break control register (abrkcr) abrkcr controls the address breaks. when both the cmf flag and bie flag are set to 1, an address break is requested. bit bit name initial value r/w description 7 cmf 0 r condition match flag address break source flag. indicates that an address specified by bara to barc is prefetched. [setting condition] when an address specified by bara to barc is prefetched while the bie flag is set to 1. [clearing condition] when an exception handling is executed for an address break interrupt. 6 to 1 all 0 r reserved these bits are always read as 0 and cannot be modified. 0 bie 0 r/w break interrupt enable enables or disables address break. 0: disabled 1: enabled 5.3.3 break address registers a to c (bara to barc) the bar registers specify an address that is to be a break address. an address in which the first byte of an instruction exists should be set as a break address. in normal mode, addresses a23 to a16 are not compared. bara bit bit name initial value r/w description 7 to 0 a23 to a16 all 0 r/w addresses 23 to 16 the a23 to a16 bits are compared with a23 to a16 in the internal address bus. rev. 2.0, 08/02, page 90 of 788 barb bit bit name initial value r/w description 7 to 0 a15 to a8 all 0 r/w addresses 15 to 8 the a15 to a8 bits are compared with a15 to a8 in the internal address bus. barc bit bit name initial value r/w description 7 to 1 a7 to a1 all 0 r/w addresses 7 to 1 the a7 to a1 bits are compared with a7 to a1 in the internal address bus. 0 0 r reserved this bit is always read as 0 and cannot be modified. 5.3.4 irq sense control registers (iscrh, iscrl) the iscr registers select the source that generates an interrupt request at pins ,54 : to ,54 3 . iscrh bit bit name initial value r/w description 7 6 irq7scb irq7sca 0 0 r/w r/w 5 4 irq6scb irq6sca 0 0 r/w r/w 3 2 irq5scb irq5sca 0 0 r/w r/w 1 0 irq4scb irq4sca 0 0 r/w r/w irqn sense control b irqn sense control a 00: interrupt request generated at low level of ,54q input 01: interrupt request generated at falling edge of ,54q input 10: interrupt request generated at rising edge of ,54q input 11: interrupt request generated at both falling and rising edges of ,54q input (n = 7 to 4) rev. 2.0, 08/02, page 91 of 788 iscrl bit bit name initial value r/w description 7 6 irq3scb irq3sca 0 0 r/w r/w 5 4 irq2scb irq2sca 0 0 r/w r/w 3 2 irq1scb irq1sca 0 0 r/w r/w 1 0 irq0scb irq0sca 0 0 r/w r/w irqn sense control b irqn sense control a 00: interrupt request generated at low level of ,54q input 01: interrupt request generated at falling edge of ,54q input 10: interrupt request generated at rising edge of ,54q input 11: interrupt request generated at both falling and rising edges of ,54q input (n = 3 to 0) 5.3.5 irq enable register (ier) ier controls the enabling and disabling of interrupt requests irq7 to irq0. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 irq7e irq6e irq5e irq4e irq3e irq2e irq1e irq0e 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w irqn enable (n = 7 to 0) the irqn interrupt request is enabled when this bit is 1. rev. 2.0, 08/02, page 92 of 788 5.3.6 irq status register (isr) the isr register is a flag register that indicates the status of irq7 to irq0 interrupt requests. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 irq7f irq6f irq5f irq4f irq3f irq2f irq1f irq0f 0 0 0 0 0 0 0 0 r/(w) * 2 r/(w) * 2 r/(w) * 2 r/(w) * 2 r/(w) * 2 r/(w) * 2 r/(w) * 2 r/(w) * 2 [setting condition] when the interrupt source selected by the iscr registers occurs [clearing conditions] when reading irqnf flag when irqnf = 1, then writing 0 to irqnf flag when interrupt exception handling is executed when low-level detection is set and ,54q input is high (n = 7 to 0) * 1 when irqn interrupt exception handling is executed when falling-edge, rising-edge, or both-edge detection is set * 1 notes: 1. when a product, in which a dtc is incorporated, is used, the corresponding flag bit is not automatically cleared even when exception handing is executed. for details, refer to section 5.8.4, setting on a product incorporating dtc. 2. only 0 can be written, for flag clearing. 5.3.7 keyboard matrix interrupt mask registers (kmimra, kmimr) wake-up event interrupt mask register (wuemrb) the kmimra, kmimr, and wuemrb registers enable or disable key-sensing interrupt inputs ( .,1 48 to .,1 3 ), and wake-up event interrupt inputs ( :8( : to :8( 3 ). kmimra bit bit name initial value r/w description 7 6 5 4 3 2 1 0 kmimr15 kmimr14 kmimr13 kmimr12 kmimr11 kmimr10 kmimr9 kmimr8 1 1 1 1 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w keyboard matrix interrupt mask 15 to 8 these bits enable or disable a key-sensing input interrupt request (kin15 to kin8). 0: enables a key-sensing input interrupt request 1: disables a key-sensing input interrupt request rev. 2.0, 08/02, page 93 of 788 kmimr bit bit name initial value r/w description 7 6 5 4 3 2 1 0 kmimr7 kmimr6 kmimr5 kmimr4 kmimr3 kmimr2 kmimr1 kmimr0 1 0 1 1 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w keyboard matrix interrupt mask 7 to 0 these bits enable or disable a key-sensing input interrupt request (kin7 to kin0). kmimr6 also performs interrupt request mask control for pin ,54 9 . 0: enables a key-sensing input interrupt request 1: disables a key-sensing input interrupt request wuemrb* bit bit name initial value r/w description 7 6 5 4 3 2 1 0 wuemr7 wuemr6 wuemr5 wuemr4 wuemr3 wuemr2 wuemr1 wuemr0 1 1 1 1 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w wake-up event interrupt mask 7 to 0 these bits enable or disable a wake-up event input interrupt request (wue7 to wue0). 0: enables a wake-up event input interrupt request 1: disables a wake-up event input interrupt request note: * not supported by the h8s/2148b. figure 5.2 shows the relationship between interrupts irq7 and irq6, interrupts kin15 to kin0, interrupts wue7 to wue0, and registers kmimra, kmimr, and wuemrb. rev. 2.0, 08/02, page 94 of 788 internal signal irq6e edge level selection enable/disable circuit edge level selection enable/disable circuit irq6sc interrupt kmimr0 (initial value 1) p60/ kmimr5 (initial value 1) p65/ kmimr6 (initial value 0) p66/ / kmimr7 (initial value 1) p67/ / internal signal irq7e irq7sc interrupt kmimr8 (initial value 1) pa0/ kmimr9 (initial value 1) pa1/ wuemr7 (initial value 1) pb7/ figure 5.2 relationship between interrupts irq7 and irq6, interrupts kin15 to kin0, interrupts wue7 to wue0, and registers kmimr, kmimra, and wuemrb if any of bits kmimr15 to kmimr8 or wuemrb7 to wuemrb0 is cleared to 0, interrupt input from the ,54 : pin will be ignored. when pins .,1 : to .,1 3 , .,1 48# to .,1 ; , or :8( : to :8( 3 are used as key-sense interrupt input pins or wakeup event interrupt input pins, either low- level sensing or falling-edge sensing must be designated as the interrupt sense condition for the corresponding interrupt source (irq6 or irq7). 5.4 interrupt sources 5.4.1 external interrupts there are four types of external interrupts: nmi, irq7 to irq0, kin15 to kin0 and wue7 to wue0. wue7 to wue0 and kin15 to kin8 share the irq7 interrupt source, and kin7 to kin0 share the irq6 interrupt source. of these, nmi, irq7, irq6 , and irq2 to irq0 can be used to restore this lsi from software standby mode. rev. 2.0, 08/02, page 95 of 788 nmi interrupt: nmi is the highest-priority interrupt, and is always accepted by the cpu regardless of the interrupt control mode or the status of the cpu interrupt mask bits. the nmieg bit in syscr can be used to select whether an interrupt is requested at a rising edge or a falling edge on the nmi pin. irq7 to irq0 interrupts: interrupts irq7 to irq0 are requested by an input signal at pins ,54 : to ,54 3 . interrupts irq7 to irq0 have the following features: the interrupt exception handling for interrupt requests irq7 to irq0 can be started at an independent vector address. using iscr, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pins ,54 : to ,54 3 . enabling or disabling of interrupt requests irq7 to irq0 can be selected with ier. interrupt control levels can be specified by the icr settings. the status of interrupt requests irq7 to irq0 is indicated in isr. isr flags can be cleared to 0 by software. the detection of irq7 to irq0 interrupts does not depend on whether the relevant pin has been set for input or output. however, when a pin is used as an external interrupt input pin, do not clear the corresponding ddr to 0 to use the pin as an i/o pin for another function. a block diagram of interrupts irq7 to irq0 is shown in figure 5.3. irqn interrupt request irqne irqnf s r q clear signal edge/level detection circuit irqnsca, irqnscb input n = 7 to 0 figure 5.3 block diagram of interrupts irq7 to irq0 rev. 2.0, 08/02, page 96 of 788 when pin ,54 9 is used as an irq6 interrupt input pin, clear the kmimr6 bit to 0. when pin ,54 : is used as an irq7 interrupt pin, set all of bits kmimr15 to kmimr8 and wuemr7 to wuemr0 to 1. if any of these bits is cleared to 0, irq7 interrupt input from the ,54 : pin will be ignored. since interrupt request flags irq7f to irq0f are set each time the setting condition is satisfied, regardless of the ier setting, refer to a needed flag only. kin15 to kin0 interrupts, wue7 to wue0 interrupts: interrupts kin15 to kin0 and wue7 to wue0 are requested by an input signal at pins .,1 48 to .,1 3 and :8( : to :8( 3 . when pins .,1 48 to .,1 3 and :8( : to :8( 3 are used for key-sense input or wakeup event, clear the corresponding kmimr and wuemr bits to 0 in order to enable their key-sense input and wakeup event interrupts. remaining unused kmimr and wuemr bits for key-sense input should be set to 1 in order to disable interrupts. interrupts wue7 to wue0 and kin15 to kin8 generate irq7 interrupts, and interrupts kin7 to kin0 generate irq6 interrupts. the pin conditions for interrupt request generation, enable of interrupt requests, settings of interrupt control levels, and status display of interrupt requests depend on each setting and display of the irq7 or irq6 interrupt. when pins .,1 : to .,1 3 , .,1 48# to .,1 ; , or :8( : to :8( 3 are used as key-sense interrupt input pins or wakeup event interrupt input pins, either low-level sensing or falling-edge sensing must be designated as the interrupt sense condition for the corresponding interrupt source (irq6 or irq7). 5.4.2 internal interrupts internal interrupts issued from the on-chip peripheral modules have the following features: 1. for each on-chip peripheral module there are flags that indicate the interrupt request status, and enable bits that individually select enabling or disabling of these interrupts. when the enable bit for a particular interrupt source is set to 1, an interrupt request is sent to the interrupt controller. 2. the control level for each interrupt can be set by icr. 3. the dtc can be activated by an interrupt request from an on-chip peripheral module. 4. an interrupt request that activates the dtc is not affected by the interrupt control mode or the status of the cpu interrupt mask bits. 5.5 interrupt exception handling vector table table 5.3 lists interrupt exception handling sources, vector addresses, and interrupt priorities. for default priorities, the lower the vector number, the higher the priority. modules set at the same priority will conform to their default priorities. priorities within a module are fixed. rev. 2.0, 08/02, page 97 of 788 an interrupt control level can be specified for a module to which an icr bit is assigned. interrupt requests from modules that are set to control level 1 (priority) by the icr bit setting and the i and ui bits in ccr are given priority and processed before interrupt requests from modules that are set to control level 0 (no priority). table 5.3 interrupt sources, vector addresses, and interrupt priorities vector address origin of interrupt source name vector number normal mode advanced mode icr priority nmi 7 h'000e h'00001c high irq0 16 h'0020 h'000040 icra7 irq1 17 h'0022 h'000044 icra6 irq2 irq3 18 19 h'0024 h'0026 h'000048 h'00004c icra5 irq4 irq5 20 21 h'0028 h'002a h'000050 h'000054 icra4 external pin irq6, kin7 to kin0 irq7, kin15 to kin8, wue7 to wue0 22 23 h'002c h'002e h'000058 h'00005c icra3 dtc swdtend (software activation data transfer end) 24 h'0030 h'000060 icra2 wdt_0 wovi0 (interval timer) 25 h'0032 h'000064 icra1 wdt_1 wovi1 (interval timer) 26 h'0034 h'000068 icra0 address break 27 h'0036 h'00006c a/d converter adi (a/d conversion end) 28 h'0038 h'000070 icrb7 reserved for system use 29 to 47 h003a to h005e h000074 to h0000bc frt icia (input capture a) icib (input capture b) icic (input capture c) icid (input capture d) ocia (output compare a) ocib (output compare b) fovi (overflow) reserved for system use 48 49 50 51 52 53 54 55 h'0060 h'0062 h'0064 h'0066 h'0068 h'006a h'006c h'006e h'0000c0 h'0000c4 h'0000c8 h'0000cc h'0000d0 h'0000d4 h'0000d8 h'0000dc icrb6 reserved for system use 56 to 63 h0070 to h007e h0000e0 to h0000fc tmr_0 cmia0 (compare match a) cmib0 (compare match a) ovi0 (overflow) reserved for system use 64 65 66 67 h'0080 h'0082 h'0084 h'0086 h'000100 h'000104 h'000108 h'00010c icrb3 low rev. 2.0, 08/02, page 98 of 788 vector address origin of interrupt source name vector number normal mode advanced mode icr priority tmr_1 cmia1 (compare match a) cmib1 (compare match b) ovi1 (overflow) reserved for system use 68 69 70 71 h'0088 h'008a h'008c h'008e h'000110 h'000114 h'000118 h'00011c icrb2 high tmr_x, tmr_y cmiay (compare match a) cmiby (compare match b) oviy (overflow) icix (input capture x) 72 73 74 75 h'0090 h'0092 h'0094 h'0096 h'000120 h'000124 h'000128 h'00012c icrb1 xbs ibf1 (idr1 reception completion) ibf2 (idr2 reception completion) ibf3 (idr3 reception completion) ibf4 (idr4 reception completion) 76 77 78 79 h'0098 h'009a h'009c h'009e h'000130 h'000134 h'000138 h'00013c icrb0 sci_0 eri0 (reception error 0) rxi0 (reception completion 0) txi0 (transmission data empty 0) tei0 (transmission end 0) 80 81 82 83 h'00a0 h'00a2 h'00a4 h'00a6 h'000140 h'000144 h'000148 h'00014c icrc7 sci_1 eri1 (reception error 1) rxi1 (reception completion 1) txi1 (transmission data empty 1) tei1 (transmission end 1) 84 85 86 87 h'00a8 h'00aa h'00ac h'00ae h'000150 h'000154 h'000158 h'00015c icrc6 sci_2 eri2 (reception error 2) rxi2 (reception completion 2) txi2 (transmission data empty 2) tei2 (transmission end 2) 88 89 90 91 h'00b0 h'00b2 h'00b4 h'00b6 h'000160 h'000164 h'000168 h'00016c icrc5 iic_0 iici0 (1-byte transmission/ reception completion) ddcswi (format switch) 92 93 h'00b8 h'00ba h'000170 h'000174 icrc4 iic_1 iici1 (1-byte transmission/ reception completion) reserved for system use 94 95 h00bc h00be h000178 h00017c icrc3 keyboard buffer controller kbia (reception completion a) kbib (reception completion b) kbic (reception completion c) reserved for system use 96 97 98 99 h00c0 h00c2 h00c4 h'00c6 h000180 h000184 h000188 h00018c icrb0 reserved for system use 100 to 107 h00c8 to h00d6 h000190 to h0001ac lpc * erri (transfer error) ibf1 (idr1 reception completion) ibf2 (idr2 reception completion) ibf3 (idr3 reception completion) 108 109 110 111 h00d8 h00da h00dc h00de h0001b0 h0001b4 h0001b8 h0001bc icrc1 low note: * reserved for system use on products not including lpc. rev. 2.0, 08/02, page 99 of 788 5.6 interrupt control modes and interrupt operation the interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 1. interrupt operations differ depending on the interrupt control mode. nmi interrupts and address break interrupts are always accepted except for in reset state or in hardware standby mode. the interrupt control mode is selected by syscr. table 5.4 shows the interrupt control modes. table 5.4 interrupt control modes syscr interrupt control mode intm1 intm0 priority setting registers interrupt mask bits description 0 0 icr i interrupt mask control is performed by the i bit. priority levels can be set with icr. 1 0 1 icr i, ui 3-level interrupt mask control is performed by the i bit. priority levels can be set with icr. 5.6.1 interrupt control mode 0 in interrupt control mode 0, interrupt requests other than nmi and address breaks are masked by icr and the i bit of the ccr in the cpu. figure 5.4 shows a flowchart of the interrupt acceptance operation. 1. if an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. according to the interrupt control level specified in icr, the interrupt controller only accepts an interrupt request with interrupt control level 1 (priority), and holds pending an interrupt request with interrupt control level 0 (no priority). if several interrupt requests are issued, an interrupt request with the highest priority is accepted according to the priority order, an interrupt handling is requested to the cpu, and other interrupt requests are held pending. 3. if the i bit in ccr is set to 1, only nmi and address break interrupts are accepted by the interrupt controller, and other interrupt requests are held pending. if the i bit is cleared to 0, any interrupt request is accepted. 4. when the cpu accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. the pc and ccr are saved to the stack area by interrupt exception handling. the pc saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. 6. next, the i bit in ccr is set to 1. this masks all interrupts except for nmi and address break interrupts. rev. 2.0, 08/02, page 100 of 788 7. the cpu generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. program excution state interrupt generated? nmi an interrupt with interrupt control level 1? irq0 irq1 ibfi3 irq0 irq1 ibfi3 i = 0 save pc and ccr i 1 read vector address branch to interrupt handling routine yes no yes yes yes no no yes no yes no yes yes no no yes yes no hold pending figure 5.4 flowchart of procedure up to interrupt acceptance in interrupt control mode 0 rev. 2.0, 08/02, page 101 of 788 5.6.2 interrupt control mode 1 in interrupt control mode 1, mask control is applied to three levels for irq and on-chip peripheral module interrupt requests by comparing the i and ui bits in ccr in the cpu, and the icr setting. an interrupt request with interrupt control level 0 is accepted when the i bit in ccr is cleared to 0. when the i bit is set to 1, the interrupt request is held pending an interrupt request with interrupt control level 1 is accepted when the i bit or ui bit in ccr is cleared to 0. when both i and ui bits are set to 1, the interrupt request is held pending. for instance, the state transition when the interrupt enable bit corresponding to each interrupt is set to 1, and icra to icrc are set to h20, h00, and h00, respectively (irq2 and irq3 interrupts are set to control level 1, and other interrupts are set to control level 0) is shown below. figure 5.5 shows a state transition diagram. all interrupt requests are accepted when i = 0. (priority order: nmi > irq2 > irq3 > address break > irq0 > irq1 ) only nmi, irq2, irq3 and address break interrupt requests are accepted when i = 1 and ui = 0. only an nmi and address break interrupt request is accepted when i = 1 and ui = 1. only nmi and address break interrupt requests are accepted all interrupt requests are accepted exception handling execution or i 1, ui 1 i 0 i 1, ui 0 i 0 ui 0 exception handling execution or ui 1 only nmi, address break, irq2, and irq3 interrupt requests are accepted figure 5.5 state transition in interrupt control mode 1 figure 5.6 shows a flowchart of the interrupt acceptance operation. 1. if an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. according to the interrupt control level specified in icr, the interrupt controller only accepts an interrupt request with interrupt control level 1 (priority), and holds pending an interrupt request with interrupt control level 0 (no priority). if several interrupt requests are issued, an interrupt request with the highest priority is accepted according to the priority order, an interrupt handling is requested to the cpu, and other interrupt requests are held pending. rev. 2.0, 08/02, page 102 of 788 3. an interrupt request with interrupt control level 1 is accepted when the i bit is cleared to 0, or when the i bit is set to 1 while the ui bit is cleared to 0. an interrupt request with interrupt control level 0 is accepted when the i bit is cleared to 0. when the i bit is set to 1, only an nmi or address break interrupt request is accepted, and other interrupts are held pending. when both the i and ui bits are set to 1, only an nmi or address break interrupt request is accepted, and other interrupts are held pending. when the i bit is cleared to 0, the ui bit is not affected. 4. when the cpu accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. the pc and ccr are saved to the stack area by interrupt exception handling. the pc saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. 6. the i and ui bits in ccr are set to 1. this masks all interrupts except for an nmi or address break interrupt. 7. the cpu generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. rev. 2.0, 08/02, page 103 of 788 program excution state interrupt generated? nmi an interrupt with interrupt control level 1? irq0 irq1 ifbfi3 irq0 irq1 ifbfi3 ui = 0 save pc and ccr i 1, ui 1 read vector address branch to interrupt handling routine yes no yes yes yes no no yes no yes no yes yes no no yes yes no hold pending i = 0 i = 0 yes yes no no figure 5.6 flowchart of procedure up to interrupt acceptance in interrupt control mode 1 5.6.3 interrupt exception handling sequence figure 5.7 shows the interrupt exception handling sequence. the example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. rev. 2.0, 08/02, page 104 of 788 (14) (12) (10) (6) (4) (2) (1) (5) (7) (9) (11) (13) prefetch of instruction in interrupt-handling routine vector fetch stack access instruction prefetch internal processing internal processing interrupt is accepted interrupt level decision and wait for end of instruction interrupt request signal internal address bus internal read signal internal write signal internal data bus ? (3) (1) (2) (4) (3) (5) (7) instruction prefetch address (instruction is not executed. address is saved as pc contents, becoming return address.) instruction code (not executed) instruction prefetch address (instruction is not executed.) sp C 2 sp C 4 saved pc and ccr vector address starting address of interrupt-handling routine (contents of vector address) starting address of interrupt-handling routine ((13) = (10) (12)) first instruction in interrupt-handling routine (6) (8) (9) (11) (10) (12) (13) (14) (8) figure 5.7 interrupt exception handling rev. 2.0, 08/02, page 105 of 788 5.6.4 interrupt response times table 5.5 shows interrupt response times - the intervals between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. the execution status symbols used in table 5.5 are explained in table 5.6. table 5.5 interrupt response times no. execution status normal mode advanced mode 1 interrupt priority determination * 1 3 2 number of wait states until executing instruction ends * 2 1 to (19 + 2s i ) 3 pc, ccr stack save 2s k 2s k 4 vector fetch s i 2s i 5 instruction fetch * 3 2s i 6 internal processing * 4 2 total (using on-chip memory) 11 to 31 12 to 32 notes: 1. two states in case of internal interrupt. 2. refers to mulxs and divxs instructions. 3. prefetch after interrupt acceptance and prefetch of interrupt handling routine. 4. internal processing after interrupt acceptance and internal processing after vector fetch. table 5.6 number of states in interrupt handling routine execution status object of access external device 8-bit bus 16-bit bus symbol internal memory 2-state access 3-state access 2-state access 3-state access instruction fetch s i branch address read s j stack manipulation s k 1 4 6 + 2m 2 3 + m legend m: number of wait states in external device access rev. 2.0, 08/02, page 106 of 788 5.6.5 dtc activation by interrupt the dtc can be activated by an interrupt. in this case, the following options are available: interrupt request to cpu activation request to dtc selection of a number of the above for details on interrupt requests that can be used to activate the dtc, see section 7, data transfer controller (dtc). figure 5.8 shows a block diagram of the dtc and interrupt controller. selection circuit dtcer dtvecr control logic determination of priority cpu dtc select signal irq interrupt on-chip supporting module clear signal interrupt controller i, ui interrupt source clear signal interrupt request dtc activation request vector number cpu interrupt request vector number swdte clear signal clear signal figure 5.8 dtc and interrupt controller selection of interrupt source: interrupt factors are selected as dtc activation source or cpu interrupt source by the dtce bit of dtcera to dtcere of dtc. by specifying the disel bit of the dtcs mrb, it is possible to clear the dtce bit to 0 after dtc data transfer, and request a cpu interrupt. if dtc carries out the designate number of data transfers and the transfer counter reads 0, after dtc data transfer, the dtce bit is also cleared to 0, and an interrupt is requested to the cpu. determination of priority: the dtc activation source is selected in accordance with the default priority order, and is not affected by mask or priority levels. see table 7.1 for the respective priority. rev. 2.0, 08/02, page 107 of 788 operation order: if the same interrupt is selected as a dtc activation source and a cpu interrupt source, the dtc data transfer is performed first, followed by cpu interrupt exception handling. table 5.7 shows the interrupt factor clear control and selection of interrupt factors by specification of the dtce bit of dtc's dtcera to dtcerh, and the disel bit of dtc's mrb. table 5.7 interrupt source selection and clearing control settings dtc interrupt sources selection/clearing control dtce disel dtc cpu 0 * o 0 o 1 1 oo legend o : the relevant interrupt is used. interrupt source clearing is performed. (the cpu should clear the source flag in the interrupt handling routine.) o : the relevant interrupt is used. the interrupt source is not cleared. : the relevant interrupt cannot be used. * : dont care note: the sci, iic, lpc, or a/d converter interrupt source is cleared when the dtc reads or writes to the prescribed register, and is not dependent upon the disel bit. 5.7 address break 5.7.1 features this lsi can determine the specific address prefetch by the cpu to generate an address break interrupt by setting abrkcr and bar. if an address break interrupt is generated, the address break interrupt exception handling is performed. with this function, the execution start point of a program containing a bug is detected and execution is branched to the correcting program. rev. 2.0, 08/02, page 108 of 788 5.7.2 block diagram figure 5.9 shows a block diagram of the address break. abrkcr bar control logic comparator match signal address break interrupt request internal address prefetch signal (internal signal) figure 5.9 address break block diagram 5.7.3 operation if the cpu prefetches an address specified in bar by setting abrkcr and bar, an address break interrupt can be generated. this address break function generates an interrupt request to the interrupt controller at prefetch, and determines the priority by the interrupt controller. when an interrupt is accepted, an interrupt exception handling is activated after the current instruction has been completed. note that the interrupt mask control according to the i and ui bits in ccr of the cpu is invalid to an address break interrupt. to use the address break function, set each register as follows: 1. set a break address in the a23 to a1 bits in bar. 2. set the bie bit in abrkcr to 1 to enable the address break. when the bie bit is cleared to 0, an address break is not requested. when the setting conditions are satisfied, the cmf flag in abrkcr is set to 1 to request an interrupt. the interrupt source should be determined by the interrupt handling routine if necessary. rev. 2.0, 08/02, page 109 of 788 5.7.4 usage notes 1. in an address break, the break address should be an address where the first byte of the instruction exists. otherwise, a break condition will not be satisfied. 2. in normal mode, addresses a23 to a16 are not compared. 3. when the branch instructions (bcc, bsr), jump instructions (jmp, jsr), rst instruction, and rte instruction are placed immediately prior to the address specified by bar, a prefetch signal to the address may be output to request an address break by executing these instruction. it is necessary to take countermeasures: do not set a break address to an address immediately after these instructions, or determine whether interrupt handling is performed by satisfaction of a normal condition. 4. an address break interrupt is generated by combining the internal prefetch signal and an address. therefore, the timing to enter the interrupt exception handling differs according to the instructions at the specified and at prior addresses and execution cycles. figure 5.10 shows an example of address timing. rev. 2.0, 08/02, page 110 of 788 instruction fetch address bus break request signal break point nop instruction is executed at break point address h'0312 and following address h'0314. fetching is performed from address h'0316 after exception handling ends. instruction fetch instruction fetch instruction fetch instruction fetch internal operation internal operation vector fetch save to stack instruction fetch h'0310 nop execution h'0310 nop h'0312 nop h'0314 nop h'0316 nop nop execution nop execution interrupt exception handling h'0312 h'0314 h'0316 h'0318 h'0036 sp-2 sp-4 (1) when a break address specified instruction is executed for one state in the program area and on-chip memory address bus break request signal break point mov instruction is executed at break point address h'0312, and nop instruction is not executed at the following address h'0314. fetching is performed from address h'0316 after exception handling ends. instruction fetch instruction fetch instruction fetch internal operation internal operation vector fetch save to stack instruction fetch h'0310 nop execution h'0310 nop h'0312 mov.w #xx:16,rd h'0316 nop h'0318 nop mov.w execution interrupt exception handling h'0312 h'0314 h'0316 h'0318 h'0036 sp-2 sp-4 (2) when a break address specified instruction is executed for two states in the program area and on-chip memory instruction fetch instruction fetch address bus break request signal break point nop instruction is not executed at break point address h'0312. fetching is performed from address h'0312 after exception handling ends. instruction fetch internal operation instruction fetch vector fetch save to stack h'0310 nop execution h'0310 nop h'0312 nop h'0314 nop h'0316 nop interrupt exception handling h'0312 h'0314 h'0036 sp-2 sp-4 (3) when a break address specified instruction is executed for one state in the program area and external memory (2-state access, 16-bit bus access) instruction fetch instruction fetch figure 5.10 address break timing example rev. 2.0, 08/02, page 111 of 788 5.8 usage notes 5.8.1 conflict between interrupt generation and disabling when an interrupt enable bit is cleared to 0 to disable interrupt requests, the disabling becomes effective after execution of the instruction. when an interrupt enable bit is cleared to 0 by an instruction such as bclr or mov, and if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, so interrupt exception handling for that interrupt will be executed on completion of the instruction. however, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. the same rule is also applied when an interrupt source flag is cleared to 0. figure 5.11 shows an example in which the cmiea bit in the tmr's tcr register is cleared to 0. the above conflict will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. internal address bus internal write signal ? cmiea cmfa cmia interrupt signal tcr write cycle by cpu cmia exception handling tcr address figure 5.11 conflict between interrupt generation and disabling 5.8.2 instructions that disable interrupts the instructions that disable interrupts are ldc, andc, orc, and xorc. after any of these instructions are executed, all interrupts including nmi are disabled and the next instruction is rev. 2.0, 08/02, page 112 of 788 always executed. when the i bit or ui bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.8.3 interrupts during execution of eepmov instruction interrupt operation differs between the eepmov.b instruction and the eepmov.w instruction. with the eepmov.b instruction, an interrupt request (including nmi) issued during the transfer is not accepted until the move is completed. with the eepmov.w instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. the pc value saved on the stack in this case is the address of the next instruction. therefore, if an interrupt is generated during execution of an eepmov.w instruction, the following coding should be used. l1: eepmov.w mov.w r4,r4 bne l1 5.8.4 setting on product incorporating dtc when a product, in which a dtc is incorporated, is used in the following settings, the corresponding flag bit is not automatically cleared even when exception handing, which is a clear condition, is executed and the bit is held at 1. 1. when dtcea3 is set to 1(adi is set to an interrupt source), irq4f flag is not automatically cleared. 2. when dtcea2 is set to 1(icia is set to an interrupt source), irq5f flag is not automatically cleared. 3. when dtcea1 is set to 1(icib is set to an interrupt source), irq6f flag is not automatically cleared. 4. when dtcea0 is set to 1(ocia is set to an interrupt source), irq7f flag is not automatically cleared. when activation interrupt sources of dtc and irq interrupts are used with the above combinations, clear the interrupt flag by software in the interrupt handling routine of the corresponding irq. 5.8.5 irq status register (isr) according to the pin status after a reset, irqnf may be set to 1, so isr should be read after a reset to write 0. (n = 7 to 0) rev. 2.0, 08/02, page 113 of 788 section 6 bus controller (bsc) this lsi has an on-chip bus controller (bsc) that manages the bus width and the number of access states of the external address space. the bsc also has a bus arbitration function, and controls the operation of the internal bus masters C cpu, and data transfer controller (dtc). 6.1 features basic bus interface 2-state access or 3-state access can be selected for each area program wait states can be inserted for each area burst rom interface a burst rom interface can be set for basic expansion areas 1-state access or 2-state access can be selected for burst access idle cycle insertion an idle cycle can be inserted for external write cycles immediately after external read cycles bus arbitration function includes a bus arbiter that arbitrates bus mastership between the cpu and dtc bus controller external bus control signals internal control signals internal data bus wait controller bcr wscr bus mode signal bus arbiter dtc bus acknowledge signal cpu bus acknowledge signal dtc bus request signal cpu bus request signal figure 6.1 block diagram of bus controller bscs20aa_000020020700 rev. 2.0, 08/02, page 114 of 788 6.2 input/output pins table 6.1 summarizes the pins of the bus controller. table 6.1 pin configuration symbol i/o function $6 output strobe signal indicating that address output on the address bus is enabled (when the iose bit in syscr is cleared to 0). ,26 output i/o select signal (when the iose bit in syscr is set to 1). 5' output strobe signal indicating that the external address space is being read. +:5 output strobe signal indicating that the external address space is being written to, and the upper half (d15 to d8) of the data bus is enabled. /:5 output strobe signal indicating that the external address space is being written to, and the lower half (d7 to d0) of the data bus is enabled. :$,7 input wait request signal when accessing the external 3-state access space. 6.3 register descriptions the bus controller has the following registers. for details on the system control register, refer to section 3.2.2, system control register (syscr). bus control register (bcr) wait state control register (wscr) rev. 2.0, 08/02, page 115 of 788 6.3.1 bus control register (bcr) bcr is used to specify the access mode for the external address space or the i/o area range when the $6 / ,26 pin is specified as an i/o strobe pin. bit bit name initial value r/w description 7 1 r/wreserved this bit should not be written by 0. 6 icis0 1 r/w idle cycle insertion selects whether or not to insert 1-state of the idle cycle between bus cycles when the external write cycle follows the external read cycle. 0: idle cycle not inserted when the external write cycle follows the external read cycle 1: 1-state idle cycle inserted when the external write cycle follows the external read cycle 5 brstrm 0 r/w burst rom enable selects the bus interface for the external address space. 0: basic bus interface 1: burst rom interface 4 brsts1 1 r/w burst cycle select 1 selects the number of states in the burst cycle of the burst rom interface. 0: 1 state 1: 2 states 3 brsts0 0 r/w burst cycle select 0 selects the number of words that can be accessed by burst access via the burst rom interface. 0: max, 4 words 1: max, 8 words 2 ? 0r/wreserved this bit should not be written by 0. 1 0 ios1 ios0 1 1 r/w r/w ios select 1, 0 select the address range where the ,26 signal is output. for details, refer to table 6.3. rev. 2.0, 08/02, page 116 of 788 6.3.2 wait state control register (wscr) wscr is used to specify the data bus width for external address space access, the number of access states, the wait mode, and the number of wait states for access to external address spaces. the bus width and the number of access states for internal memory and internal i/o registers are fixed regardless of the wscr settings. bit bit name initial value r/w description 7 6 0 0 r/w r/w reserved these bits should not be written by 1. 5 abw 1 r/w bus width control selects 8 or 16bits for access to the external address space. 0: 16-bit access space 1: 8-bit access space 4 ast 1 r/w access state control selects 2 or 3 access states for access to the external address space. this bit also enables or disables wait- state insertion. 0: 2-state access space. wait state insertion disabled in external address space access 1: 3-state access space. wait state insertion enabled in external address space access 3 2 wms1 wms0 0 0 r/w r/w wait mode select 1, 0 select the wait mode for access to the external address space when the ast bit is set to 1. 00: program wait mode 01: wait disabled mode 10: pin wait mode 11: pin auto-wait mode 1 0 wc1 wc0 1 1 r/w r/w wait count 1, 0 select the number of program wait states to be inserted when the external address space is accessed while the ast bit is set to 1. 00: program wait state is not inserted 01: 1 program wait state is inserted 10: 2 program wait states are inserted 11: 3 program wait states are inserted rev. 2.0, 08/02, page 117 of 788 6.4 bus control 6.4.1 bus specifications the external address space bus specifications consist of three elements: bus width, the number of access states, and the wait mode and the number of program wait states. the bus width and the number of access states for on-chip memory and internal i/o registers are fixed, and are not affected by the bus controller settings. bus width: a bus width of 8 or 16 bits can be selected via the abw bit in wscr. number of access states: two or three access states can be selected via the ast bit in wscr. when the 2-state access space is designated, wait-state insertion is disabled. in the burst rom interface, the number of access states is determined regardless of the ast bit setting. wait mode and number of program wait states: when a 3-state access space is designated by the ast bit in wscr, the wait mode and the number of program wait states to be inserted automatically is selected by the wms1, wms0, wc1, and wc0 bits in wscr. from 0 to 3 program wait states can be selected. rev. 2.0, 08/02, page 118 of 788 table 6.2 shows the bus specifications for the basic bus interface of each area. table 6.2 bus specifications for basic bus interface bus specifications abw ast wms1 wms0 wc1 wc0 bus width number of access states number of program wait states 0 16 2 0 01 3 0 00 0 11 02 0 1 * * 1 1 16 3 3 0 8 2 0 01 3 0 00 0 11 02 1 1 * * 1 1 8 3 3 note: * other than wms1 = 0 and wms0 = 1 6.4.2 advanced mode the external address space is initialized as the basic bus interface and a 3-state access space. in on-chip rom enable extended mode, the address space other than on-chip rom, on-chip ram, internal i/o registers, and their reserved areas is specified as the external address space. the on- chip ram and its reserved area are enabled when the rame bit in syscr is set to 1. the on- chip ram and its reserved area are disabled and corresponding addresses are the external address space when the rame bit is cleared to 0. 6.4.3 normal mode the external address space is initialized as the basic bus interface and a 3-state access space. in on-chip rom disable extended mode, the address space other than on-chip ram and internal i/o registers is specified as the external address space. in on-chip rom enable extended mode, the address space other than on-chip rom, on-chip ram, internal i/o registers, and their reserved areas is specified as the external address space. the on-chip ram area is enabled when the rev. 2.0, 08/02, page 119 of 788 rame bit in syscr is set to 1, and disabled and specified as the external address space when the rame bit is cleared to 0. 6.4.4 i/o select signals the lsi can output i/o select signals ( ,26 ); the signal is driven low when the corresponding external address space is accessed. figure 6.2 shows an example of ,26 signal output timing. bus cycle t 1 t 2 address bus ? t 3 external addresses selected by ios figure 6.2 ,26 ,26 ,26 ,26 signal output timing enabling or disabling ,26 signal output is performed by the iose bit in syscr. in extended mode, the ,26 pin functions as an $6 pin by a reset. to use this pin as an ,26 pin, set the iose bit to 1. for details, refer to section 8, i/o ports. the address ranges of the ,26 signal output can be specified by the ios1 and ios0 bits in bcr, as shown in table 6.3. table 6.3 address range for ,26 ,26 ,26 ,26 signal output ios1 ios0 ,26 ,26 ,26 ,26 signal output range 0 h'(ff)f000 to h'(ff)f03f 0 1 h'(ff)f000 to h'(ff)f0ff 0 h'(ff)f000 to h'(ff)f3ff 1 1 h'(ff)f000 to h'(ff)f7ff (initial value) rev. 2.0, 08/02, page 120 of 788 6.5 basic bus interface the basic bus interface enables direct connection to rom and sram. for details on selection of the bus specifications when using the basic bus interface, see table 6.2 6.5.1 data size and data alignment data sizes for the cpu and other internal bus masters are byte, word, and longword. the bsc has a data alignment function, and controls whether the upper data bus (d15 to d8) or lower data bus (d7 to d0) is used when the external address space is accessed, according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space) and the data size. 8-bit access space: figure 6.3 illustrates data alignment control for the 8-bit access space. with the 8-bit access space, the upper data bus (d15 to d8) is always used for accesses. the amount of data that can be accessed at one time is one byte: a word access is performed as two byte accesses, and a longword access, as four byte accesses. d15 d8 d7 d0 upper data bus lower data bus byte size word size 1st bus cycle 2nd bus cycle longword size 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle figure 6.3 access sizes and data alignment control (8-bit access space) 16-bit access space: figure 6.4 illustrates data alignment control for the 16-bit access space. with the 16-bit access space, the upper data bus (d15 to d8) and lower data bus (d7 to d0) are used for accesses. the amount of data that can be accessed at one time is one byte or one word, and a longword access is executed as two word accesses. in byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. the upper data bus is used for an even address, and the lower data bus for an odd address. rev. 2.0, 08/02, page 121 of 788 d15 d8 d7 d0 upper data bus lower data bus byte size word size 1st bus cycle 2nd bus cycle longword size even address byte size odd address figure 6.4 access sizes and data alignment control (16-bit access space) 6.5.2 valid strobes table 6.4 shows the data buses used and valid strobes for each access space. in a read, the 5' signal is valid for both the upper and lower halves of the data bus. in a write, the +:5 signal is valid for the upper half of the data bus, and the /:5 signal for the lower half. table 6.4 data buses used and valid strobes area access size read/ write address valid strobe upper data bus (d15 to d8) lower data bus (d7 to d0) read 5' ports or others 8-bit access space byte write +:5 valid ports or others even valid invalid read odd 5' invalid valid even +:5 valid undefined byte write odd /:5 undefined valid read 5' valid valid 16-bit access space word write +:5 , /:5 valid valid note: * undefined: undefined data is output. invalid: input state with the input value ignored. ports or others: used as ports or i/o pins for on-chip peripheral modules, and are not used as the data bus. rev. 2.0, 08/02, page 122 of 788 6.5.3 basic operation timing 8-bit, 2-state access space: figure 6.5 shows the bus timing for an 8-bit, 2-state access space. when an 8-bit access space is accessed, the upper half (d15 to d8) of the data bus is used. wait states cannot be inserted. bus cycle t 1 t 2 address bus ? / (iose = 1) / (iose = 0) d15 to d8 valid d7 to d0 invalid read d15 to d8 valid write figure 6.5 bus timing for 8-bit, 2-state access space rev. 2.0, 08/02, page 123 of 788 8-bit, 3-state access space: figure 6.6 shows the bus timing for an 8-bit, 3-state access space. when an 8-bit access space is accessed, the upper half (d15 to d8) of the data bus is used. wait states can be inserted. bus cycle t 1 t 2 address bus ? / (iose = 0) d15 to d8 valid d7 to d0 invalid read d15 to d8 valid write t 3 / (iose = 1) figure 6.6 bus timing for 8-bit, 3-state access space rev. 2.0, 08/02, page 124 of 788 16-bit, 2-state access space: figures 6.7 to 6.9 show bus timings for a 16-bit, 2-state access space. when a 16-bit access space is accessed, the upper half (d15 to d8) of the data bus is used for even addresses, and the lower half (d7 to d0) for odd addresses. wait states cannot be inserted. bus cycle t 1 t 2 address bus ? / (iose = 0) d15 to d8 valid d7 to d0 invalid read d15 to d8 valid d7 to d0 undefined write high level / (iose = 1) figure 6.7 bus timing for 16-bit, 2-state access space (even byte access) rev. 2.0, 08/02, page 125 of 788 bus cycle t 1 t 2 address bus ? / (iose = 0) d15 to d8 invalid d7 to d0 valid read d15 to d8 undefined d7 to d0 valid write high level / (iose = 1) figure 6.8 bus timing for 16-bit, 2-state access space (odd byte access) rev. 2.0, 08/02, page 126 of 788 bus cycle t 1 t 2 address bus ? / (iose = 0) d15 to d8 valid d7 to d0 valid read d15 to d8 valid d7 to d0 valid write / (iose = 1) figure 6.9 bus timing for 16-bit, 2-state access space (word access) rev. 2.0, 08/02, page 127 of 788 16-bit, 3-state access space: figures 6.10 to 6.12 show bus timings for a 16-bit, 3-state access space. when a 16-bit access space is accessed, the upper half (d15 to d8) of the data bus is used for even addresses, and the lower half (d7 to d0) for odd addresses. wait states can be inserted. bus cycle t 1 t 2 address bus ? / (iose = 0) d15 to d8 valid d7 to d0 invalid read d15 to d8 valid d7 to d0 undefined write high level t 3 / (iose = 1) figure 6.10 bus timing for 16-bit, 3-state access space (even byte access) rev. 2.0, 08/02, page 128 of 788 bus cycle t 1 t 2 address bus ? / (iose = 0) d15 to d8 invalid d7 to d0 valid read d15 to d8 undefined d7 to d0 valid write high level t 3 / (iose = 1) figure 6.11 bus timing for 16-bit, 3-state access space (odd byte access) rev. 2.0, 08/02, page 129 of 788 bus cycle t 1 t 2 address bus ? / (iose = 0) d15 to d8 valid d7 to d0 valid read d15 to d8 valid d7 to d0 valid write t 3 / (iose = 1) figure 6.12 bus timing for 16-bit, 3-state access space (word access) rev. 2.0, 08/02, page 130 of 788 6.5.4 wait control when accessing the external address space, this lsi can extend the bus cycle by inserting one or more wait states (t w ). there are three ways of inserting wait states: program wait insertion, pin wait insertion using the :$,7 pin, and the combination of program wait and the :$,7 pin. program wait mode: a specified number of wait states t w can be inserted automatically between the t 2 state and t 3 state when accessing the external address space always according to the settings of the wc1 and wc0 bits in wscr. pin wait mode: a specified number of wait states t w can be inserted automatically between the t 2 state and t 3 state when accessing the external address space always according to the settings of the wc1 and wc0 bits. if the :$,7 pin is low at the falling edge of ? in the last t 2 or t w state, another t w state is inserted. if the :$,7 pin is held low, t w states are inserted until it goes high. this is useful when inserting four or more t w states, or when changing the number of t w states to be inserted for each external device. pin auto-wait mode: a specified number of wait states t w can be inserted automatically between the t 2 state and t 3 state when accessing the external address space according to the settings of the wc1 and wc0 bits if the :$,7 pin is low at the falling edge of ? in the last t 2 state. even if the :$,7 pin is held low, t w states can be inserted only up to the specified number of states. this function enables the low-speed memory interface only by inputting the chip select signal to the :$,7 pin. figure 6.13 shows an example of wait state insertion timing in pin wait mode. the settings after a reset are: 3-state access, 3 program wait insertion, and :$,7 pin input disabled. rev. 2.0, 08/02, page 131 of 788 by program wait t 1 address bus ? / (iose = 0) data bus read data read , write data write note: shown in ? clock indicates the pin sampling timing. data bus t 2 t w t w t w t 3 by pin figure 6.13 example of wait state insertion timing (pin wait mode) 6.6 burst rom interface in this lsi, the external address space can be designated as the burst rom space by setting the brstrm bit in bcr to 1, and the burst rom interface enabled. consecutive burst accesses of a maximum four or eight words can be performed only during cpu instruction fetch. 1 or 2 states can be selected for burst rom access. 6.6.1 basic operation timing the number of access states in the initial cycle (full access) of the burst rom interface is determined by the ast bit in wscr. when the ast bit is set to 1, wait states can be inserted. 1 or 2 states can be selected for burst access according to the setting of the brsts1 bit in bcr. wait states cannot be inserted in a burst cycle. burst accesses of a maximum four words is performed when the brsts0 bit in bcr is cleared to 0, and burst accesses of a maximum eight words is performed when the brsts0 bit in bcr is set to 1. the basic access timing for the burst rom space is shown in figures 6.14 and 6.15. rev. 2.0, 08/02, page 132 of 788 t 1 address bus ? / data bus t 2 t 3 t 1 t 2 t 1 full access t 2 burst access only lower address changes read data read data read data (iose = 0) figure 6.14 access timing example in burst rom space (ast = brsts1 = 1) t 1 address bus ? data bus t 2 t 1 t 1 full access burst access only lower address changes read data read data read data / (iose = 0) figure 6.15 access timing example in burst rom space (ast = brsts1 = 0) 6.6.2 wait control as with the basic bus interface, program wait insertion or pin wait insertion using the :$,7 pin can be used in the initial cycle (full access) of the burst rom interface. for details, see section 6.5.4, wait control. wait states cannot be inserted in a burst cycle. rev. 2.0, 08/02, page 133 of 788 6.7 idle cycle when this lsi accesses the external address space, it can insert a 1-state idle cycle (t i ) between bus cycles when a write cycle occurs immediately after a read cycle. by inserting an idle cycle it is possible, for example, to avoid data collisions between rom with a long output floating time, and high-speed memory and i/o interfaces. if an external write occurs after an external read while the icis0 bit is set to 1 in bcr, an idle cycle is inserted at the start of the write cycle. figure 6.16 shows examples of idle cycle operation. in these examples, bus cycle a is a read cycle for rom with a long output floating time, and bus cycle b is a cpu write cycle. in figure 6.16 (a), with no idle cycle inserted, a collision occurs in bus cycle b between the read data from rom and the cpu write data. in figure 6.16 (b), an idle cycle is inserted, thus preventing data collision. t 1 address bus ? bus cycle a data bus t 2 t 3 t 1 t 2 bus cycle b long output floating time data collision (a) no idle cycle insertion t 1 address bus ? bus cycle a data bus t 2 t 3 t i t 1 bus cycle b (b) idle cycle insertion t 2 , , figure 6.16 examples of idle cycle operation table 6.5 shows the pin states in an idle cycle. table 6.5 pin states in idle cycle pins pin state a23 to a0, ,26 contents of immediately following bus cycle d15 to d0 high impedance $6 high 5' high +:5 , /:5 high rev. 2.0, 08/02, page 134 of 788 6.8 bus arbitration the bus controller has a bus arbiter that arbitrates bus master operations. there are two bus masters C the cpu and dtc C that perform read/write operations when they have possession of the bus. 6.8.1 priority of bus masters each bus master requests the bus by means of a bus request signal. the bus arbiter detects the bus masters' bus request signals, and if a bus request occurs, it sends a bus request acknowledge signal to the bus master making the request at the designated timing. if there are bus requests from more than one bus master, the bus request acknowledge signal is sent to the one with the highest priority. when a bus master receives the bus request acknowledge signal, it takes possession of the bus until that signal is canceled. the order of priority of the bus masters is as follows: (high) dtc > cpu (low) 6.8.2 bus transfer timing when a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. each bus master can relinquish the bus at the timings given below. cpu: the cpu is the lowest-priority bus master, and if a bus request is received from the dtc, the bus arbiter transfers the bus to the dtc. dtc bus transfer timing ? the bus is transferred at a break between bus cycles. however, if a bus cycle is executed in discrete operations, as in the case of a longword-size access, the bus is not transferred between the component operations. for details, refer to the h8s/2600 series, h8s/2000 series programming manual. ? if the cpu is in sleep mode, the bus is transferred immediately. dtc: the dtc has the highest bus master priority. the dtc sends the bus arbiter a request for the bus when an activation request is generated. the dtc does not release the bus until it completes its operation. rev. 2.0, 08/02, page 135 of 788 section 7 data transfer controller (dtc) this lsi includes a data transfer controller (dtc). the dtc can be activated by an interrupt or software, to transfer data. figure 7.1 shows a block diagram of the dtc. the dtc's register information is stored in the on- chip ram. when the dtc is used, the rame bit in syscr must be set to 1. a 32-bit bus connects the dtc to addresses h'(ff)ec00 to h'(ff)efff in on-chip ram (1 kbyte), enabling 32-bit/1-state reading and writing of the dtc register information. 7.1 features transfer is possible over any number of channels three transfer modes normal, repeat, and block transfer modes are available. one activation source can trigger a number of data transfers (chain transfer) direct specification of 16-mbyte address space is possible activation by software is possible transfer can be set in byte or word units a cpu interrupt can be requested for the interrupt that activated the dtc module stop mode can be set dtch80aa_000020020700 rev. 2.0, 08/02, page 136 of 788 internal address bus dtcer a to dtcer e dtvecr interrupt controller dtc on-chip ram internal data bus cpu interrupt request mra mrb cra crb dar sar interrupt request mra, mrb cra, crb sar dar dtcera to dtcere dtvecr : dtc mode register a, b : dtc transfer count register a, b : dtc source address register : dtc destination register : dtc enable registers a to e : dtc vector register legend: dtc activation request control logic register information figure 7.1 block diagram of dtc 7.2 register descriptions the dtc has the following registers. dtc mode register a (mra) dtc mode register b (mrb) dtc source address register (sar) dtc destination address register (dar) dtc transfer count register a (cra) dtc transfer count register b (crb) these six registers cannot be directly accessed from the cpu. when a dtc activation interrupt source occurs, the dtc reads a set of register information that is stored in on-chip ram to the corresponding dtc registers and transfers data. after the data transfer, it writes a set of updated register information back to on-chip ram. dtc enable registers a to e (dtcera to dtcere) dtc vector register (dtvecr) rev. 2.0, 08/02, page 137 of 788 7.2.1 dtc mode register a (mra) mra selects the dtc operating mode. bit bit name initial value r/w description 7 6 sm1 sm0 undefined undefined source address mode 1, 0 these bits specify an sar operation after a data transfer. 0x: sar is fixed 10: sar is incremented after a transfer (by +1 when sz = 0, by +2 when sz = 1) 11: sar is decremented after a transfer (by C1 when sz = 0, by C2 when sz = 1) 5 4 dm1 dm0 undefined undefined destination address mode 1, 0 these bits specify a dar operation after a data transfer. 0x: dar is fixed 10: dar is incremented after a transfer (by +1 when sz = 0, by +2 when sz = 1) 11: dar is decremented after a transfer (by C1 when sz = 0, by C2 when sz = 1) 3 2 md1 md0 undefined undefined dtc mode these bits specify the dtc transfer mode. 00: normal mode 01: repeat mode 10: block transfer mode 11: setting prohibited 1 dts undefined dtc transfer mode select specifies whether the source side or the destination side is set to be a repeat area or block area in repeat mode or block transfer mode. 0: destination side is repeat area or block area 1: source side is repeat area or block area 0 sz undefined dtc data transfer size specifies the size of data to be transferred. 0: byte-size transfer 1: word-size transfer legend: x: don't care rev. 2.0, 08/02, page 138 of 788 7.2.2 dtc mode register b (mrb) mrb selects the dtc operating mode. bit bit name initial value r/w description 7 chne undefined dtc chain transfer enable when this bit is set to 1, a chain transfer will be performed. for details, refer to section 7.5.4, chain transfer. in data transfer with chne set to 1, determination of the end of the specified number of data transfers, clearing of the interrupt source flag, and clearing of dtcer are not performed. 6 disel undefined dtc interrupt select when this bit is set to 1, a cpu interrupt request is generated every time data transfer ends (the dtc clears the interrupt source flag for the activation source). when this bit is cleared to 0, a cpu interrupt request is generated only when the specified number of data transfer ends (the dtc does not clear the interrupt source flag for the activation source). 5 to 0 undefined reserved these bits have no effect on dtc operation. only 0 should be written to these bits. 7.2.3 dtc source address register (sar) sar is a 24-bit register that designates the source address of data to be transferred by the dtc. for word-size transfer, specify an even source address. 7.2.4 dtc destination address register (dar) dar is a 24-bit register that designates the destination address of data to be transferred by the dtc. for word-size transfer, specify an even destination address. 7.2.5 dtc transfer count register a (cra) cra is a 16-bit register that designates the number of times data is to be transferred by the dtc. in normal mode, the entire cra functions as a 16-bit transfer counter (1 to 65536). it is decremented by 1 every time data is transferred, and transfer ends when the count reaches h'0000. rev. 2.0, 08/02, page 139 of 788 in repeat mode or block transfer mode, the cra is divided into two parts; the upper 8 bits (crah) and the lower 8 bits (cral). crah holds the number of transfers while cral functions as an 8-bit transfer counter (1 to 256). cral is decremented by 1 every time data is transferred, and the contents of crah are sent when the count reaches h'00. 7.2.6 dtc transfer count register b (crb) crb is a 16-bit register that designates the number of times data is to be transferred by the dtc in block transfer mode. it functions as a 16-bit transfer counter (1 to 65536) that is decremented by 1 every time data is transferred, and transfer ends when the count reaches h'0000. 7.2.7 dtc enable registers (dtcer) dtcer specifies dtc activation interrupt sources. dtcer is comprised of five registers: dtcera to dtcere. the correspondence between interrupt sources and dtce bits is shown in table 7.1. for dtce bit setting, use bit manipulation instructions such as bset and bclr. multiple dtc activation sources can be set at one time (only at the initial setting) by masking all interrupts and writing data after executing a dummy read on the relevant register. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 dtce7 dtce6 dtce5 dtce4 dtce3 dtce2 dtce1 dtce0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w dtc activation enable setting this bit to 1 specifies a relevant interrupt source as a dtc activation source. [clearing conditions] when data transfer has ended with the disel bit in mrb set to 1. when the specified number of transfers have ended. [holding condition] when the disel bit is 0 and the specified number of transfers have not been completed. rev. 2.0, 08/02, page 140 of 788 7.2.8 dtc vector register (dtvecr) dtvecr enables or disables dtc activation by software, and sets a vector number for the software activation interrupt. bit bit name initial value r/w description 7 swdte 0 r/w dtc software activation enable setting this bit to 1 activates dtc. only 1 can always be written to this bit. 0 can be written to after reading 1 from this bit. [clearing conditions] when the disel bit is 0 and the specified number of transfers have not ended. when 0 is written to the disel bit after a software- activated data transfer end interrupt (swdtend) request has been sent to the cpu. [holding conditions] when the disel bit is 1 and data transfer has ended when the specified number of transfers have ended. during data transfer activated by software 6 5 4 3 2 1 0 dtvec6 dtvec5 dtvec4 dtvec3 dtvec2 dtvec1 dtvec0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w dtc software activation vectors 6 to 0 these bits specify a vector number for dtc software activation. the vector address is expressed as h'0400 + (vector number 2). for example, when dtvec6 to dtvec0 = h'10, the vector address is h'0420. when the swdte bit is 0, these bits can be written to. 7.3 activation sources the dtc is activated by an interrupt request or by a write to dtvecr by software. the interrupt request source to activate the dtc is selected by dtcer. at the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the interrupt flag that became the activation source or the corresponding dtcer bit is cleared. the activation source flag, in the case of rxi0, for example, is the rdrf flag in sci_0. when an interrupt has been designated as a dtc activation source, the existing cpu mask level and interrupt controller priorities have no effect. if there is more than one activation source at the same time, the dtc operates in accordance with the default priorities. figure 7.2 shows a block rev. 2.0, 08/02, page 141 of 788 diagram of dtc activation source control. for details on the interrupt controller, see section 5, interrupt controller. cpu dtc dtcer source flag cleared on-chip peripheral module irq interrupt interrupt request clear clear controller clear request interrupt controller selection circuit interrupt mask select dtvecr figure 7.2 block diagram of dtc activation source control 7.4 location of register information and dtc vector table locate the register information in the on-chip ram (addresses: h'(ff)ec00 to h'(ff)efff). register information should be located at an address that is a multiple of four within the range. the method for locating the register information in address space is shown in figure 7.3. locate mra, sar, mrb, dar, cra, and crb, in that order, from the start address of the register information. in the case of chain transfer, register information should be located in consecutive areas as shown in figure 7.3, and the register information start address should be located at the vector address corresponding to the interrupt source in the dtc vector table. the dtc reads the start address of the register information from the vector table set for each activation source, and then reads the register information from that start address. when the dtc is activated by software, the vector address is obtained from: h'0400 + (dtvecr[6:0] 2). for example, if dtvecr is h'10, the vector address is h'0420. the configuration of the vector address is the same in both normal and advanced modes; a 2-byte unit is used in both cases. specify the lower two bits of the register information start address. rev. 2.0, 08/02, page 142 of 788 mra 0123 sar mrb dar cra crb mra sar mrb dar cra crb lower address 4 bytes register information register information for 2nd transfer in chain transfer register information start address chain transfer figure 7.3 dtc register information location in address space rev. 2.0, 08/02, page 143 of 788 table 7.1 interrupt sources, dtc vector addresses, and corresponding dtces activation source origin activation source vector number dtc vector address dtce * 1 priority software write to dtvecr dtvecr h'0400 + (vector number 2) high irq0 16 h'0420 dtcea7 irq1 17 h'0422 dtcea6 irq2 18 h'0424 dtcea5 external pins irq3 19 h'0426 dtcea4 a/d converter adi 28 h'0438 dtcea3 icia 48 h0460 dtcea2 icib 49 h'0462 dtcea1 ocia 52 h'0468 dtcea0 frt ocib 53 h'046a dtceb7 cmia0 64 h'0480 dtceb2 tmr_0 cmib0 65 h'0482 dtceb1 cmia1 68 h'0488 dtceb0 tmr_1 cmib1 69 h'048a dtcec7 cmiay 72 h'0490 dtcec6 tmr_y cmiby 73 h'0492 dtcec5 ibf1 76 h'0498 dtcec4 xbs ibf2 77 h'049a dtcec3 rxi0 81 h'04a2 dtcec2 sci_0 txi0 82 h'04a4 dtcec1 rxi1 85 h'04aa dtcec0 sci_1 txi1 86 h'04ac dtced7 rxi2 89 h'04b2 dtced6 sci_2 txi2 90 h'04b4 dtced5 iic_0 iici0 92 h'04b8 dtced4 iic_1 iici1 94 h'04bc dtced3 erri 108 h'04d8 dtcee3 ibfi1 109 h'04da dtcee2 ibfi2 110 h'04dc dtcee1 lpc * 2 ibfi3 111 h'04de dtcee0 low notes: 1. dtce bits with no corresponding interrupt are reserved, and only 0 should be written to this bit. 2. not supported by the h8s/2148b. rev. 2.0, 08/02, page 144 of 788 7.5 operation the dtc stores register information in on-chip ram. when activated, the dtc reads register information in on-chip ram and transfers data. after the data transfer, the dtc writes updated register information back to on-chip ram. the pre-storage of register information in memory makes it possible to transfer data over any required number of channels. the transfer mode can be specified as normal, repeat, or block transfer mode. setting the chne bit in mrb to 1 makes it possible to perform a number of transfers with a single activation source (chain transfer). the 24-bit sar designates the dtc transfer source address, and the 24-bit dar designates the transfer destination address. after each transfer, sar and dar are independently incremented, decremented, or left fixed depending on its register information. start end read dtc vector read register information data transfer write register information clear an activation flag interrupt exception handling clear dtcer chne = 1 next transfer yes yes no transfer counter = 0 or disel = 1 no figure 7.4 dtc operation flowchart rev. 2.0, 08/02, page 145 of 788 7.5.1 normal mode in normal mode, one activation source transfers one byte or one word of data. table 7.2 lists the register functions in normal mode. from 1 to 65,536 transfers can be specified. once the specified number of transfers have been completed, a cpu interrupt can be requested. table 7.2 register functions in normal mode name abbreviation function dtc source address register sar transfer source address dtc destination address register dar transfer destination address dtc transfer count register a cra transfer counter dtc transfer count register b crb not used transfer sar dar figure 7.5 memory mapping in normal mode 7.5.2 repeat mode in repeat mode, one activation source transfers one byte or one word of data. table 7.3 lists the register functions in repeat mode. from 1 to 256 transfers can be specified. once the specified number of transfers have completed, the initial states of the transfer counter and the address register that is specified as the repeat area is restored, and transfer is repeated. in repeat mode, the transfer counter value does not reach h'00, and therefore cpu interrupts cannot be requested when the disel bit in mrb is cleared to 0. rev. 2.0, 08/02, page 146 of 788 table 7.3 register functions in repeat mode name abbreviation function dtc source address register sar transfer source address dtc destination address register dar transfer destination address dtc transfer count register ah crah holds number of transfers dtc transfer count register al cral transfer count dtc transfer count register b crb not used transfer sar or dar dar or sar repeat area figure 7.6 memory mapping in repeat mode 7.5.3 block transfer mode in block transfer mode, one activation source transfers one block of data. either the transfer source or the transfer destination is designated as a block area. table 7.4 lists the register functions in block transfer mode. the block size can be between 1 and 256. when the transfer of one block ends, the initial state of the block size counter and the address register that is specified as the block area is restored. the other address register is then incremented, decremented, or left fixed according to the register information. from 1 to 65,536 transfers can be specified. once the specified number of transfers have been completed, a cpu interrupt is requested. rev. 2.0, 08/02, page 147 of 788 table 7.4 register functions in block transfer mode name abbreviation function dtc source address register sar transfer source address dtc destination address register dar transfer destination address dtc transfer count register ah crah holds block size dtc transfer count register al cral block size counter dtc transfer count register b crb transfer counter transfer sar or dar dar or sar block area ? ? ? 1st block n th block figure 7.7 memory mapping in block transfer mode 7.5.4 chain transfer setting the chne bit in mrb to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. sar, dar, cra, crb, mra, and mrb, which define data transfers, can be set independently. figure 7.8 shows the overview of chain transfer operation. when activated, the dtc reads the register information start address stored at the dtc vector address, and then reads the first register information at that start address. after the data transfer, the chne bit will be tested. when it has been set to 1, dtc reads the next register information located in a consecutive area and performs the data transfer. these sequences are repeated until the chne bit is cleared to 0. rev. 2.0, 08/02, page 148 of 788 in the case of transfer with the chne bit set to 1, an interrupt request to the cpu is not generated at the end of the specified number of transfers or by setting of the disel bit to 1, and the interrupt source flag for the activation source is not affected. dtc vector address source destination source destination register information chne = 1 register information chne = 0 register information start address figure 7.8 chain transfer operation 7.5.5 interrupts an interrupt request is issued to the cpu when the dtc has completed the specified number of data transfers, or a data transfer for which the disel bit was set to 1. in the case of interrupt activation, the interrupt set as the activation source is generated. these interrupts to the cpu are subject to cpu mask level and priority level control by the interrupt controller. in the case of software activation, a software-activated data transfer end interrupt (swdtend) is generated. when the disel bit is 1 and one data transfer has been completed, or the specified number of transfers have been completed, after data transfer ends, the swdte bit is held at 1 and an swdtend interrupt is generated. the interrupt handling routine will then clear the swdte bit to 0. when the dtc is activated by software, an swdtend interrupt is not generated during a data transfer wait or during data transfer even if the swdte bit is set to 1. rev. 2.0, 08/02, page 149 of 788 7.5.6 operation timing dtc activation request dtc request address vector read read write transfer information read transfer information write data transfer ? figure 7.9 dtc operation timing (example in normal mode or repeat mode) dtc activation request dtc request address vector read read write read write transfer information read transfer information write data transfer ? figure 7.10 dtc operation timing (example of block transfer mode, with block size of 2) dtc activation request dtc request address vector read read write read write transfer information read transfer information write transfer information read transfer information write data transfer data transfer ? figure 7.11 dtc operation timing (example of chain transfer) rev. 2.0, 08/02, page 150 of 788 7.5.7 number of dtc execution states table 7.5 lists the execution status for a single dtc data transfer, and table 7.6 shows the number of states required for each execution status. table 7.5 dtc execution status mode vector read i register information read/write j data read k data write l internal operations m normal16 113 repeat 1 6 1 1 3 block transfer 1 6 n n 3 n: block size (initial setting of crah and cral) table 7.6 number of states required for each execution status object to be accessed on-chip ram on-chip rom on-chip i/o registers external devices bus width 32 16 8 16 8 16 access states 1 1 2 2 2 3 2 3 vector read s i 1 4 6 + 2m 2 3 + m register information read/write s j 1 byte data read s k 11 2223 + m23 + m word data read s k 11 4246 + 2m23 + m byte data write s l 11 2223 + m23 + m word data write s l 11 4246 + 2m23 + m execution status internal operation s m 1 the number of execution states is calculated from using the formula below. note that s is the sum of all transfers activated by one activation source (the number in which the chne bit is set to 1, plus 1). number of execution states = i s i + s (j s j + k s k + l s l ) + m s m rev. 2.0, 08/02, page 151 of 788 for example, when the dtc vector address table is located in on-chip rom, normal mode is set, and data is transferred from on-chip rom to an internal i/o register, then the time required for the dtc operation is 13 states. the time from activation to the end of data write is 10 states. 7.6 procedures for using dtc 7.6.1 activation by interrupt the procedure for using the dtc with interrupt activation is as follows: 1. set the mra, mrb, sar, dar, cra, and crb register information in on-chip ram. 2. set the start address of the register information in the dtc vector address. 3. set the corresponding bit in dtcer to 1. 4. set the enable bits for the interrupt sources to be used as the activation sources to 1. the dtc is activated when an interrupt used as an activation source is generated. 5. after one data transfer has been completed, or after the specified number of data transfers have been completed, the dtce bit is cleared to 0 and a cpu interrupt is requested. if the dtc is to continue transferring data, set the dtce bit to 1. 7.6.2 activation by software the procedure for using the dtc with software activation is as follows: 1. set the mra, mrb, sar, dar, cra, and crb register information in on-chip ram. 2. set the start address of the register information in the dtc vector address. 3. check that the swdte bit is 0. 4. write 1 to the swdte bit and the vector number to dtvecr. 5. check the vector number written to dtvecr. 6. after one data transfer has been completed, if the disel bit is 0 and a cpu interrupt is not requested, the swdte bit is cleared to 0. if the dtc is to continue transferring data, set the swdte bit to 1. when the disel bit is 1 or after the specified number of data transfers have been completed, the swdte bit is held at 1 and a cpu interrupt is requested. rev. 2.0, 08/02, page 152 of 788 7.7 examples of use of dtc 7.7.1 normal mode an example is shown in which the dtc is used to receive 128 bytes of data via the sci. 1. set mra to a fixed source address (sm1 = sm0 = 0), incrementing destination address (dm1 = 1, dm0 = 0), normal mode (md1 = md0 = 0), and byte size (sz = 0). the dts bit can have any value. set mrb for one data transfer by one interrupt (chne = 0, disel = 0). set the sci, rdr address in sar, the start address of the ram area where the data will be received in dar, and 128 (h'0080) in cra. crb can be set to any value. 2. set the start address of the register information at the dtc vector address. 3. set the corresponding bit in dtcer to 1. 4. set the sci to the appropriate receive mode. set the rie bit in scr to 1 to enable the reception complete (rxi) interrupt. since the generation of a receive error during the sci reception operation will disable subsequent reception, the cpu should be enabled to accept receive error interrupts. 5. each time the reception of one byte of data has been completed on the sci, the rdrf flag in ssr is set to 1, an rxi interrupt is generated, and the dtc is activated. the receive data is transferred from rdr to ram by the dtc. dar is incremented and cra is decremented. the rdrf flag is automatically cleared to 0. 6. when cra becomes 0 after 128 data transfers have been completed, the rdrf flag is held at 1, the dtce bit is cleared to 0, and an rxi interrupt request is sent to the cpu. the interrupt handling routine will perform wrap-up processing. rev. 2.0, 08/02, page 153 of 788 7.7.2 software activation an example is shown in which the dtc is used to transfer a block of 128 bytes of data by means of software activation. the transfer source address is h'1000 and the transfer destination address is h'2000. the vector number is h'60, so the vector address is h'04c0. 1. set mra to incrementing source address (sm1 = 1, sm0 = 0), incrementing destination address (dm1 = 1, dm0 = 0), block transfer mode (md1 = 1, md0 = 0), and byte size (sz = 0). the dts bit can have any value. set mrb for one block transfer by one interrupt (chne = 0). set the transfer source address (h'1000) in sar, the transfer destination address (h'2000) in dar, and 128 (h'8080) in cra. set 1 (h'0001) in crb. 2. set the start address of the register information at the dtc vector address (h'04c0). 3. check that the swdte bit in dtvecr is 0. check that there is currently no transfer activated by software. 4. write 1 to the swdte bit and the vector number (h'60) to dtvecr. the write data is h'e0. 5. read dtvecr again and check that it is set to the vector number (h'60). if it is not, this indicates that the write failed. this is presumably because an interrupt occurred between steps 3 and 4 and led to a different software activation. to activate this transfer, go back to step 3. 6. if the write was successful, the dtc is activated and a block of 128 bytes of data is transferred. 7. after the transfer, an swdtend interrupt occurs. the interrupt handling routine should clear the swdte bit to 0 and perform wrap-up processing. rev. 2.0, 08/02, page 154 of 788 7.8 usage notes 7.8.1 module stop mode setting dtc operation can be enabled or disabled by the module stop control register (mstpcr). in the initial state, dtc operation is enabled. access to dtc registers are disabled when module stop mode is set. note that when the dtc is being activated, module stop mode cannot be specified. for details, refer to section 26, power-down modes. 7.8.2 on-chip ram mra, mrb, sar, dar, cra, and crb are all located in on-chip ram. when the dtc is used, the rame bit in syscr should not be cleared to 0. 7.8.3 dtce bit setting for dtce bit setting, use bit manipulation instructions such as bset and bclr, for reading and writing. multiple dtc activation sources can be set at one time (only at the initial setting) by masking all interrupts and writing data after executing a dummy read on the relevant register. 7.8.4 setting required on entering subactive mode or watch mode set the mstp14 bit in mstpcrh to 1 to make the dtc enter module stop mode, then confirm that is set to 1 before making a transition to subactive mode or watch mode. 7.8.5 dtc activation by interrupt sources of sci, iic, lpc, or a/d converter interrupt sources of the sci, iic, lpc, or a/d converter which activate the dtc are cleared when dtc reads from or writes to the respective registers, and they cannot be cleared by the disel bit in mrb. rev. 2.0, 08/02, page 155 of 788 section 8 i/o ports 8.1 overview this lsi has ten i/o ports (ports 1 to 6, 8, 9, a, and b), and one input-only port (port 7). for additional ports c, d, e, f, and g in h8s/2160b and h8s/2161b, see section 8.13 additional overview for h8s/2160b and h8s/2161b. table 8.1 is a summary of the port functions. the pins of each port also have other functions. each port includes a data direction register (ddr) that controls input/output (not provided for the input-only port) and data registers (dr, odr) that store output data. ports 1 to 3, 6, a, and b have an on-chip input pull-up mos function. for ports a and b, the on/off status of the input pull-up mos is controlled by ddr and odr. ports 1 to 3 and 6 have an input pull-up mos control register (pcr), in addition to ddr and dr, to control the on/off status of the input pull-up mos. ports 1 to 6, 8, 9, a, and b can drive a single ttl load and 30 pf capacitive load. all the i/o ports can drive a darlington transistor when in output mode. ports 1, 2, and 3 can drive an led (10 ma sink current). port a input and output use by the vccb power supply, which is independent of the v cc power supply. when the vccb voltage is 5v, the pins on port a will be 5-v tolerant. pa4 to pa7 of port a have bus-buffer drive capability. p52 in port 5, p97 in port 9, p86 in port 8 and p42 in port 4 are nmos push-pull outputs. p52, p97, p86 and p42 are thus 5-v tolerant, with dc characteristics that are dependent on the v cc voltage. for the p42/sck2, p52/sck0, p86/sck1, and p97 outputs, connect pull-up resistors to pins to raise output-high-level voltage. rev. 2.0, 08/02, page 156 of 788 table 8.1 port functions of h8s/2140b, h8s/2141b, h8s/2145b, and h8s/2148b mode 2 mode 3 port description mode 1 (expe = 1) (expe = 0) i/o status port 1 general i/o port also functioning as address output and pwm output pins a7 a6 a5 a4 a3 a2 a1 a0 a7/p17/pw7 a6/p16/pw6 a5/p15/pw5 a4/p14/pw4 a3/p13/pw3 a2/p12/pw2 a1/p11/pw1 a0/p10/pw0 p17/pw7 p16/pw6 p15/pw5 p14/pw4 p13/pw3 p12/pw2 p11/pw1 p10/pw0 on-chip input pull-up moss port 2 general i/o port also functioning as address output pin, pwm output pin, and timer connection output pin a15 a14 a13 a12 a11 a10 a9 a8 a15/p27/pw15/ cblank a14/p26/pw14 a13/p25/pw13 a12/p24/pw12 a11/p23/pw11 a10/p22/pw10 a9/p21/pw9 a8/p20/pw8 p27/pw15 /cblank p26/pw14 p25/pw13 p24/pw12 p23/pw11 p22/pw10 p21/pw9 p20/pw8 on-chip input pull-up moss port 3 general i/o port also functioning as data bus input/output, xbs data bus input/output, and lpc input/output pins d15 d14 d13 d12 d11 d10 d9 d8 p37/ hdb7/serirq * p36/hdb6/lclk * p35/hdb5/ /5(6(7 * p34/hdb4/ /)5$0( * p33/hdb3/lad3 * p32/hdb2/lad2 * p31/hdb1/lad1 * p30/hdb0/lad0 * on-chip input pull-up moss rev. 2.0, 08/02, page 157 of 788 mode 2 mode 3 port description mode 1 (expe = 1) (expe = 0) i/o status port 4 general i/o port also functioning as pwmx output, tmr_0 and tmr_1 input/output, timer connection input/output, xbs host interrupt request output, sci_2 input/output, irda interface input/output, and iic_1 input/output pins p47/pwx1 p46/ pwx0 p45/tmri1/csynci p44/tmo1/hsynco p43/tmci1/hsynci p42/tmri0/sck2/sda1 p41/tmo0/rxd2/irrxd p40/tmci0/txd2/irtxd p47/pwx1 p46/pwx0 p45/tmri1/hirq12 /csynci p44/tmo1/hirq1/ hsynco p43/tmci1/hirq11 /hsynci p42/tmri0/sck2/ sda1 p41/tmo0/rxd2/ irrxd p40/tmci0/txd2/ irtxd port 5 general i/o port also functioning as sci_0 input/output and iic_0 input/output pins p52/sck0/scl0 p51/rxd0 p50/txd0 port 6 general i/o port also functioning as interrupt input, frt input/output, tmr_x and tmr_y input/output, timer connection input/output, key- sense interrupt input, and expansion a/d input pins p67/ ,54 : /tmox/ .,1 : /cin7 p66/ ,54 9 /ftob/ .,1 9 /cin6 p65/ftid/ .,1 8 /cin5 p64/ftic/ .,1 7 /cin4/clampo p63/ftib/ .,1 6 /cin3/vfbacki p62/ftia/tmiy/ .,1 5 /cin2/vsynci p61/ftoa/ .,1 4 /cin1/vsynco p60/ftci/tmix/ .,1 3 /cin0/hfbacki on-chip input pull-up moss rev. 2.0, 08/02, page 158 of 788 mode 2 mode 3 port description mode 1 (expe = 1) (expe = 0) i/o status port 7 general input port also functioning as a/d converter analog input and d/a converter analog output pins p77/an7/da1 p76/an6/da0 p75/an5 p74/an4 p73/an3 p72/an2 p71/an1 p70/an0 port 8 general i/o port also functioning as interrupt input, sci_1 input/output, xbs control input/output, lpc input/output, and iic_1 input/output pins p86/ ,54 8 /sck1/scl1 p85/ ,54 7 /rxd1 p84/ ,54 6 /txd1 p83 p82 p81 p80 p86/ ,54 8 /sck1/ scl1 p85/ ,54 7 /rxd1 p84/ ,54 6 /txd1 p83/ /3&3' * p82/hifsd/ &/.581 * p81/ &6 5 /ga20 p80/ha0/ 30( * port 9 general i/o port also functioning as extended data bus control input/output, iic_0 input/output, subclock input, ? output, interrupt input, xbs control input, and a/d converter external trigger input pins p97/ :$,7 2 sda0 p96/?/excl $6 / ,26 +:5 5' p92/ ,54 3 p91/ ,54 4 p90/ /:5 / ,54 5 / $'75* p97/sda0 p96/?/excl p95/ &6 4 p94/ ,2: p93/ ,25 p92/ ,54 3 p91/ ,54 4 p90/ ,54 5 / $'75* / (&6 5 rev. 2.0, 08/02, page 159 of 788 mode 2 mode 3 port description mode 1 (expe = 1) (expe = 0) i/o status port a general i/o port also functioning as address output, key-sense interrupt input, extended a/d input, and keyboard buffer controller input/output pins pa7/ .,1 48 /cin15/ ps2cd pa6/ .,1 47 /cin14/ ps2cc pa5/ .,1 46 /cin13/ ps2bd pa4/ .,1 45 /cin12/ ps2bc pa3/ .,1 44 /cin11/ ps2ad pa2/ .,1 43 /cin10/ ps2ac pa1/ .,1 < / cin9 pa0/ .,1 ; / cin8 pa7/a23/ .,1 48 / cin15/ps2cd pa6/a22/ .,1 47 / cin14/ps2cc pa5/a21/ .,1 46 / cin13/ps2bd pa4/a20/ .,1 45 / cin12/ps2bc pa3/a19/ .,1 44 / cin11/ps2ad pa2/a18/ .,1 43 / cin10/ps2ac pa1/a17/ .,1 < / cin9 pa0/a16/ .,1 ; / cin8 pa7/ .,1 48 /cin15/ ps2cd pa6/ .,1 47 /cin14/ ps2cc pa5/ .,1 46 /cin13/ ps2bd pa4/ .,1 45 /cin12/ ps2bc pa3/ .,1 44 /cin11/ ps2ad pa2/ .,1 43 /cin10/ ps2ac pa1/ .,1 < /cin9 pa0/ .,1 ; /cin8 on-chip input pull-up moss port b general i/o port also functioning as wakeup event interrupt input, data bus input/output, xbs control input/output, and lpc input/output pins pb7/d7/ :8( : * pb6/d6/ :8( 9 * pb5/d5/ :8( 8 * pb4/d4/ :8( 7 * pb3/d3/ :8( 6 * pb2/d2/ :8( 5 * pb1/d1/ :8( 4 * pb0/d0/ :8( 3 * pb7/ :8( : * pb6/ :8( 9 * pb5/ :8( 8 * pb4/ :8( 7 * pb3/ :8( 6 * / &6 7 pb2/ :8( 5 * / &6 6 pb1/ :8( 4 * /hirq4 /lsci * pb0/ :8( 3 * /hirq3 / /60, * on-chip input pull-up moss note: * not supported by the h8s/2148b. rev. 2.0, 08/02, page 160 of 788 8.2 port 1 port 1 is an 8-bit i/o port. port 1 pins also function as an address bus and pwm output pins. port 1 functions change according to the operating mode. port 1 has an on-chip input pull-up mos function that can be controlled by software. port 1 has the following registers. port 1 data direction register (p1ddr) port 1 data register (p1dr) port 1 pull-up mos control register (p1pcr) 8.2.1 port 1 data direction register (p1ddr) p1ddr specifies input or output for the pins of port 1 on a bit-by-bit basis. bit bit name initial value r/w description 7 p17ddr 0 w 6 p16ddr 0 w 5 p15ddr 0 w 4 p14ddr 0 w 3 p13ddr 0 w 2 p12ddr 0 w 1 p11ddr 0 w 0 p10ddr 0 w in mode 1: each pin of port 1 is address output regardless of the set value of p1ddr. in modes 2 and 3 (expe=1): the corresponding port 1 pins are address output or pwm output ports when p1ddr bits are set to 1, and input ports when cleared to 0. in modes 2 and 3 (expe=0): the corresponding port 1 pins are output ports or pwm outputs when the p1ddr bits are set to 1, and input ports when cleared to 0. rev. 2.0, 08/02, page 161 of 788 8.2.2 port 1 data register (p1dr) p1dr stores output data for the port 1 pins. bit bit name initial value r/w description 7 p17dr 0 r/w 6 p16dr 0 r/w 5 p15dr 0 r/w 4 p14dr 0 r/w 3 p13dr 0 r/w 2 p12dr 0 r/w 1 p11dr 0 r/w 0 p10dr 0 r/w if a port 1 read is performed while the p1ddr bits are set to 1, the p1dr values are read. if a port 1 read is performed while the p1ddr bits are cleared to 0, the pin states are read. 8.2.3 port 1 pull-up mos control register (p1pcr) p1pcr controls the on/off status of the port 1 on-chip input pull-up moss. bit bit name initial value r/w description 7 p17pcr 0 r/w 6 p16pcr 0 r/w 5 p15pcr 0 r/w 4 p14pcr 0 r/w 3 p13pcr 0 r/w 2 p12pcr 0 r/w 1 p11pcr 0 r/w 0 p10pcr 0 r/w when the pins are in input state, the corresponding input pull-up mos is turned on when a p1pcr bit is set to 1. rev. 2.0, 08/02, page 162 of 788 8.2.4 pin functions p17/a7/pw7 to p10/a0/pw0 the pin function is switched as shown below according to the combination of the oen bit in pwoera of pwm, the p1nddr bit, and operating mode. operating mode mode 1 mode 2, 3 (expe = 1) mode 2, 3 (expe = 0) p1nddr 0 1 0 1 oen 0 1 0 1 pin function a7 to a0 output pins p17 to p10 input pins a7 to a0 output pins pw7 to pw0 output pins p17 to p10 input pins p17 to p10 output pins pw7 to pw0 output pins legend n = 7 to 0 8.2.5 port 1 input pull-up mos port 1 has an on-chip input pull-up mos function that can be controlled by software. this input pull-up mos function can be specified as on or off on a bit-by-bit basis. table 8.2 summarizes the input pull-up mos states. table 8.2 input pull-up mos states (port 1) mode reset hardware standby mode software standby mode in other operations 1offoff 2, 3 off off on/off on/off legend: off: input pull-up mos is always off. on/off: on when the pin is in the input state, p1ddr = 0, and p1pcr = 1; otherwise off. rev. 2.0, 08/02, page 163 of 788 8.3 port 2 port 2 is an 8-bit i/o port. port 2 pins also function as address bus output function, 8-bit pwm output pins, and the timer connection output pin. port 2 functions change according to the operating mode. port 2 has an on-chip input pull-up mos function that can be controlled by software. port 2 has the following registers. port 2 data direction register (p2ddr) port 2 data register (p2dr) port 2 pull-up mos control register (p2pcr) 8.3.1 port 2 data direction register (p2ddr) p2ddr specifies input or output for the pins of port 2 on a bit-by-bit basis. bit bit name initial value r/w description 7 p27ddr 0 w 6 p26ddr 0 w 5 p25ddr 0 w 4 p24ddr 0 w 3 p23ddr 0 w 2 p22ddr 0 w 1 p21ddr 0 w 0 p20ddr 0 w in mode 1: the corresponding port 2 pins are address outputs, regardless of the p2ddr setting. modes 2 and 3 (expe = 1): the corresponding port 2 pins are address outputs or pwm outputs when p2ddr bits are set to 1, and input ports when cleared to 0. p27 to p24 are switched from address outputs to output ports by setting the iose bit to 1. p27 can be used as an on-chip peripheral module output pin regardless of the p27ddr setting, but to ensure normal access to external space, p27 should not be set as an on-chip peripheral module output pin when port 2 pins are used as address output pins. modes 2 and 3 (expe = 0): the corresponding port 2 pins are output ports or pwm outputs when p2ddr bits are set to 1, and input ports when cleared to 0. p27 can be used as an on-chip peripheral module output pin regardless of the p27ddr setting. rev. 2.0, 08/02, page 164 of 788 8.3.2 port 2 data register (p2dr) p2dr stores output data for port 2. bit bit name initial value r/w description 7 p27dr 0 r/w 6 p26dr 0 r/w 5 p25dr 0 r/w 4 p24dr 0 r/w 3 p23dr 0 r/w 2 p22dr 0 r/w 1 p21dr 0 r/w 0 p20dr 0 r/w if a port 2 read is performed while p2ddr bits are set to 1, the p2dr values are read directly, regardless of the actual pin states. if a port 2 read is performed while p2ddr bits are cleared to 0, the pin states are read. 8.3.3 port 2 pull-up mos control register (p2pcr) p2pcr controls the port 2 on-chip input pull-up moss. bit bit name initial value r/w description 7 p27pcr 0 r/w 6 p26pcr 0 r/w 5 p25pcr 0 r/w 4 p24pcr 0 r/w 3 p23pcr 0 r/w 2 p22pcr 0 r/w 1 p21pcr 0 r/w 0 p20pcr 0 r/w in modes 2 and 3, the input pull-up mos is turned on when a p2pcr bit is set to 1 in the input port state. rev. 2.0, 08/02, page 165 of 788 8.3.4 pin functions to ensure normal access to external space, p27 should not be set as an on-chip peripheral module output pin when port 2 pins are used as address output pins. p27/a15/pw15/cblank the pin function is switched as shown below according to the combination of the iose bit in syscr, the cboe bit in tconro of timer connection, the oe15 bit in pwoerb of pwm, the p27ddr bit, and operating mode. operating mode mode 1 mode 2, 3 (expe = 1) mode 2, 3 (expe = 0) cboe 0 1 0 1 p27ddr 0 1 0 1 oe15 0 1 0 1 iose 0 1 pin function a15 output pin p27 input pin a15 output pin p27 output pin pw15 output pin cblank output pin p27 input pin p27 output pin pw15 output pin cblank output pin p26/a14/pw14, p25/a13/pw13, p24/a12/pw12 the pin function is switched as shown below according to the combination of the iose bit in syscr, the oem bit in pwoerb of pwm, the p2nddr bit, and operating mode. operating mode mode 1 mode 2, 3 (expe = 1) mode 2, 3 (expe = 0) p2nddr 0 1 0 1 oem 0 1 0 1 iose 0 1 1 pin function a14 to a12 output pins p26 to p24 input pins a14 to a12 output pins p26 to p24 output pins pw14 to pw12 output pins p26 to p24 input pins p26 to p24 output pins pw14 to pw12 output pins legend n = 6 to 4 m = 14 to 12 rev. 2.0, 08/02, page 166 of 788 p23/a11/pw11, p22/a10/pw10, p21/a9/pw9, p20/a8/pw8 the pin function is switched as shown below according to the combination of the oem bit in pwoerb of pwm, the p2nddr bit, and operating mode. operating mode mode 1 mode 2, 3 (expe = 1) mode 2, 3 (expe = 0) p2nddr 0 1 0 1 oem 0 1 0 1 pin function a11 to a8 output pins p23 to p20 input pins a11 to a8 output pins pw11 to pw8 output pins p23 to p20 input pins p23 to p20 output pins pw11 to pw8 output pins legend n = 3 to 0 m = 11 to 8 8.3.5 port 2 input pull-up mos port 2 has an on-chip input pull-up mos function that can be controlled by software. this input pull-up mos function can be specified as on or off on a bit-by-bit basis. table 8.3 summarizes the input pull-up mos states. table 8.3 input pull-up mos states (port 2) mode reset hardware standby mode software standby mode in other operations 1offoff 2, 3 off off on/off on/off legend off: input pull-up mos is always off. on/off: on when the pin is in the input state, p2ddr = 0, and p2pcr = 1; otherwise off. rev. 2.0, 08/02, page 167 of 788 8.4 port 3 port 3 is an 8-bit i/o port. port 3 pins also function as a bidirectional data bus, xbs bidirectional data bus, and lpc input/output pins. port 3 functions change according to the operating mode. port 3 has the following registers. port 3 data direction register (p3ddr) port 3 data register (p3dr) port 3 pull-up mos control register (p3pcr) 8.4.1 port 3 data direction register (p3ddr) p3ddr specifies input or output for the pins of port 3 on a bit-by-bit basis. bit bit name initial value r/w description 7 p37ddr 0 w 6 p36ddr 0 w 5 p35ddr 0 w 4 p34ddr 0 w 3 p33ddr 0 w 2 p32ddr 0 w 1 p31ddr 0 w 0 p30ddr 0 w modes 1, 2, and 3 (expe = 1) the input/output direction specified by p3ddr is ignored, and pins automatically function as data i/o pins. modes 2 and 3 (expe = 0) the corresponding port 3 pins are output ports when p3ddr bits are set to 1, and input ports when cleared to 0. 8.4.2 port 3 data register (p3dr) p3dr stores output data of port 3. bit bit name initial value r/w description 7 p37dr 0 r/w 6 p36dr 0 r/w 5 p35dr 0 r/w 4 p34dr 0 r/w 3 p33dr 0 r/w 2 p32dr 0 r/w 1 p31dr 0 r/w 0 p30dr 0 r/w if a port 3 read is performed while p3ddr bits are set to 1, the p3dr values are read directly, regardless of the actual pin states. if a port 3 read is performed while p3ddr bits are cleared to 0, the pin states are read. rev. 2.0, 08/02, page 168 of 788 8.4.3 port 3 pull-up mos control register (p3pcr) p3pcr controls the port 3 on-chip input pull-up moss on a bit-by-bit basis. bit bit name initial value r/w description 7 p37pcr 0 r/w 6 p36pcr 0 r/w 5 p35pcr 0 r/w 4 p34pcr 0 r/w 3 p33pcr 0 r/w 2 p32pcr 0 r/w 1 p31pcr 0 r/w 0 p30pcr 0 r/w in modes 2 and 3 (when expe = 0), the input pull- up mos is turned on when a p3pcr bit is set to 1 in the input port state. the input pull-up mos function cannot be used when the host interface is enabled. 8.4.4 pin functions p37/d15/hdb7/serirq*, p36/d14/hdb6/lclk*, p35/d13/hdb5/ /5(6(7 *, p34/d12/hdb4/ /)5$0( *, p33/d11/hdb3/lad3*, p32/d10/hdb2/lad2*, p31/d9/hdb1/lad1*, p30/d8/hdb0/lad0* the pin function is switched as shown below according to the combination of the hi12e bit in syscr2, the lpc3e to lpc1e bits in hicr0 of host interface (lpc), the p3nddr bit, and operating mode. operating mode mode 1, 2, 3 (expe = 1) mode 2, 3 (expe = 0) lpcme all 0 all 0 not all 0 hi12e 0 0 1 0 p3nddr 0 1 0 pin function d15 to d8 input/output pins p37 to p30 input pins p37 to p30 output pins hdb7 to hdb0 input/output pins lpc input/output pins note: * the combination of bits not described in the above table must not be used. m = 3 to 1: lpc input/output pins (serirq, lclk, /5(6(7 , /)5$0( , lad3 to lad0) when at least one of lpc3e to lpc1e is set to 1. n = 7 to 0 * : not supported by the h8s/2148b. rev. 2.0, 08/02, page 169 of 788 8.4.5 port 3 input pull-up mos port 3 has an on-chip input pull-up mos function that can be controlled by software. this input pull-up mos function can be specified as on or off on a bit-by-bit basis. table 8.4 summarizes the input pull-up mos states. table 8.4 input pull-up mos states (port 3) mode reset hardware standby mode software standby mode in other operations 1, 2, 3 (expe = 1) off off 2, 3 (expe = 0) off off on/off on/off legend off: input pull-up mos is always off. on/off: on when the pin is in the input state, p3ddr = 0, and p3pcr = 1; otherwise off. 8.5 port 4 port 4 is an 8-bit i/o port. port 4 pins also function as pwmx output pins, tmr_0 and tmr_1 i/o pins, timer connection i/o pins, sci_2 i/o pins, irda interface i/o pins, xbs output pins, and the iic_1 i/o pin. the output type of p42 and sck2 is nmos push-pull output. the output type of sda1 is nmos open drain output. port 4 pin functions are the same in all operating modes. port 4 has the following registers. port 4 data direction register (p4ddr) port 4 data register (p4dr) rev. 2.0, 08/02, page 170 of 788 8.5.1 port 4 data direction register (p4ddr) p4ddr specifies input or output for the pins of port 4 on a bit-by-bit basis. bit bit name initial value r/w description 7 p47ddr 0 w 6 p46ddr 0 w 5 p45ddr 0 w 4 p44ddr 0 w 3 p43ddr 0 w 2 p42ddr 0 w 1 p41ddr 0 w 0 p40ddr 0 w when a bit in p4ddr is set to 1, the corresponding pin functions as an output port, and when cleared to 0, as an input port. as 14-bit pwm and sci_2 are initialized in software standby mode, the pin states are determined by the tmr_0, tmr_1, xbs, iic_1, p4ddr, and p4dr specifications. 8.5.2 port 4 data register (p4dr) p4dr stores output data for port 4. bit bit name initial value r/w description 7 p47dr 0 r/w 6 p46dr 0 r/w 5 p45dr 0 r/w 4 p44dr 0 r/w 3 p43dr 0 r/w 2 p42dr 0 r/w 1 p41dr 0 r/w 0 p40dr 0 r/w if a port 4 read is performed while p4ddr bits are set to 1, the p4dr values are read directly, regardless of the actual pin states. if a port 4 read is performed while p4ddr bits are cleared to 0, the pin states are read. rev. 2.0, 08/02, page 171 of 788 8.5.3 pin functions p47/pwx1 the pin function is switched as shown below according to the combination of the oeb bit in dacr of the 14-bit pwm and the p47ddr bit. oeb 0 1 p47ddr 0 1 pin function p47 input pin p47 output pin pwx1 output pin p46/pwx0 the pin function is switched as shown below according to the combination of the oea bit in dacr of the 14-bit pwm and the p46ddr bit. oea 0 1 p46ddr 0 1 pin function p46 input pin p46 output pin pwx0 output pin p45/tmri1/hirq12/csynci the pin function is switched as shown below according to the combination of the hi12e bit in syscr2 and the p45ddr bit. p45ddr 0 1 hi12e 0 0 1 p45 input pin p45 output pin hirq12 output pin pin function tmri1 input pin, csynci input pin * note: * when bits cclr1 and cclr0 in tcr1 of tmr_1 are set to 1, this pin is used as the tmri1 input pin. it can also be used as the csynci input pin. rev. 2.0, 08/02, page 172 of 788 p44/tmo1/hirq1/hsynco the pin function is switched as shown below according to the combination of the hi12e bit in syscr2, the os3 to os0 bits in tcsr of tmr_1, the hoe bit in tconro of the timer connection function, and the p44ddr bit. hoe 0 1 os3 to os0 all 0 not all 0 p44ddr 0 1 hi12e 0 1 pin function p44 input pin p44 output pin hirq1 output pin tmo1 output pin hsynco output pin p43/tmci1/hirq11/hsynci the pin function is switched as shown below according to the combination of the hi12e bit in syscr2 and the p43ddr bit. p43ddr 0 1 hi12e 0 1 p43 input pin p43 output pin hirq11 output pin pin function tmci1 input pin, hsynci input pin * note: * when the external clock is selected by bits cks2 to cks0 in tcr1 of tmr_1, this pin is used as the tmci1 input pin. it can also be used as the hsynci input pin. rev. 2.0, 08/02, page 173 of 788 p42/tmri0/sck2/sda1 the pin function is switched as shown below according to the combination of the ice bit in iccr of iic1, the cke1 and cke0 bits in scr of sci_2, the c/ $ bit in smr of sci_2, and the p42ddr bit. ice 0 1 cke1 0 1 0 c/ $ 010 cke0 0 1 0 p42ddr 0 1 p42 input pin p42 output pin sck2 output pin sck2 output pin sck2 input pin sda1 i/o pin pin function tmri0 input pin * note: * when this pin is used as the sda1 i/o pin, bits cke1 and cke0 in scr of sci_2 and bit c/ $ in smr of sci_2 must all be cleared to 0. sda1 is an nmos-only output, and has direct bus drive capability. when bits cclr1 and cclr0 in tcr0 of tmr_0 are set to 1, this pin is used as the tmri0 input pin. when the p42 output pin and sck2 output pin are set, the output type is nmos push-pull output. p41/tmo0/rxd2/irrxd the pin function is switched as shown below according to the combination of the os3 to os0 bits in tcsr of tmr0, the re bit in scr of sci_2 and the p41ddr bit. os3 to os0 all 0 not all 0 re 0 1 0 p41ddr 0 1 pin function p41 input pin p41 output pin rxd2/irrxd input pin tmo0 output pin note: * when this pin is used as the tmo0 output pin, bit re in scr of sci_2 must be cleared to 0. rev. 2.0, 08/02, page 174 of 788 p40/tmci0/txd2/irtxd the pin function is switched as shown below according to the combination of the te bit in scr of sci_2 and the p40ddr bit. te 0 1 p40ddr 0 1 p40 input pin p40 output pin txd2/irtxd output pin pin function tmci0 input pin * note: * when an external clock is selected with bits cks2 to cks0 in tcr0 of tmr_0, this pin is used as the tmci0 input pin. 8.6 port 5 port 5 is a 3-bit i/o port. port 5 pins also function as sci_0 i/o pins, and the iic_0 i/o pin. p52 and sck0 are nmos push-pull outputs, and scl0 is an nmos open-drain output. port 5 has the following registers. port 5 data direction register (p5ddr) port 5 data register (p5dr) 8.6.1 port 5 data direction register (p5ddr) p5ddr specifies input or output for the pins of port 5 on a bit-by-bit basis. bit bit name initial value r/w description 7 to 3 all 1 reserved the initial value must not be changed. 2 p52ddr 0 w 1 p51ddr 0 w 0 p50ddr 0 w the corresponding port 5 pins are output ports when p5ddr bits are set to 1, and input ports when cleared to 0. as sci_0 is initialized in software standby mode, the pin states are determined by the iic_0 iccr, p5ddr, and p5dr specifications. rev. 2.0, 08/02, page 175 of 788 8.6.2 port 5 data register (p5dr) p5dr stores output data for port 5 pins. bit bit name initial value r/w description 7 to 3 all 1 reserved the initial value must not be changed. 2 p52dr 0 r/w 1 p51dr 0 r/w 0 p50dr 0 r/w if a port 5 read is performed while p5ddr bits are set to 1, the p5dr values are read directly, regardless of the actual pin states. if a port 5 read is performed while p5ddr bits are cleared to 0, the pin states are read. 8.6.3 pin functions p52/sck0/scl0 the pin function is switched as shown below according to the combination of the cke1 and cke0 bits in scr of sci_0, the c/ $ bit in smr of sci_0, the ice bit in iccr of iic_0, and the p52ddr bit. ice 0 1 cke1 0 1 0 c/ $ 010 cke0 0 1 0 p52ddr0 1 pin function p52 input pin p52 output pin sck0 output pin sck0 output pin sck0 input pin scl0 i/o pin note: * when this pin is used as the scl0 i/o pin, bits cke1 and cke0 in scr of sci0 and bit c/ $ in smr of sci0 must all be cleared to 0. scl0 is an nmos open-drain output, and has direct bus drive capability. when set as the p52 output pin or sck0 output pin, this pin is an nmos push-pull output. p51/rxd0 the pin function is switched as shown below according to the combination of the re bit in scr of sci_0 and the p51ddr bit. re 0 1 p51ddr 0 1 pin function p51 input pin p51 output pin rxd0 input pin rev. 2.0, 08/02, page 176 of 788 p50/txd0 the pin function is switched as shown below according to the combination of the te bit in scr of sci_0 and the p50ddr bit. te 0 1 p50ddr 0 1 pin function p50 input pin p50 output pin txd0 output pin 8.7 port 6 port 6 is an 8-bit i/o port. port 6 pins also function as the frt i/o pins, tmr_x i/o pins, the tmr_y input pin, timer connection i/o pins, key-sense interrupt input pins, expansion a/d converter input pins, and external interrupt input pins. the port 6 input level can be switched in four stages. port 6 pin functions are the same in all operating modes. for details on the system control register 2 (syscr2), refer to section 18, host interface x-bus interface (xbs). port 6 has the following registers. port 6 data direction register (p6ddr) port 6 data register (p6dr) port 6 pull-up mos control register (kmpcr6) system control register 2 (syscr2) 8.7.1 port 6 data direction register (p6ddr) p6ddr specifies input or output for the pins of port 6 on a bit-by-bit basis. bit bit name initial value r/w description 7 p67ddr 0 w 6 p66ddr 0 w 5 p65ddr 0 w 4 p64ddr 0 w 3 p63ddr 0 w 2 p62ddr 0 w 1 p61ddr 0 w 0 p60ddr 0 w the corresponding port 6 pins are output ports when p6ddr bits are set to 1, and input ports when cleared to 0. rev. 2.0, 08/02, page 177 of 788 8.7.2 port 6 data register (p6dr) p6dr stores output data for port 6. bit bit name initial value r/w description 7 p67dr 0 r/w 6 p66dr 0 r/w 5 p65dr 0 r/w 4 p64dr 0 r/w 3 p63dr 0 r/w 2 p62dr 0 r/w 1 p61dr 0 r/w 0 p60dr 0 r/w if a port 6 read is performed while p6ddr bits are set to 1, the p6dr values are read directly, regardless of the actual pin states. if a port 6 read is performed while p6ddr bits are cleared to 0, the pin states are read. 8.7.3 port 6 pull-up mos control register (kmpcr) kmpcr controls the port 6 on-chip input pull-up moss on a bit-by-bit basis. bit bit name initial value r/w description 7 km7pcr 0 r/w 6 km6pcr 0 r/w 5 km5pcr 0 r/w 4 km4pcr 0 r/w 3 km3pcr 0 r/w 2 km2pcr 0 r/w 1 km1pcr 0 r/w 0 km0pcr 0 r/w the input pull-up mos is turned on when a kmpcr bit is set to 1 while the corresponding p6ddr bit is cleared to 0 (input port setting). 8.7.4 pin functions p67/tmox/cin7/ .,1 : / ,54 : the pin function is switched as shown below according to the combination of the os3 to os0 bits in tcsr of tmr_x and the p67ddr bit. rev. 2.0, 08/02, page 178 of 788 os3 to os0 all 0 not all 0 p67ddr 0 1 p67 input pin p67 output pin tmox output pin pin function ,54 : input pin, .,1 : input pin, cin7 input pin * note: * this pin is used as the ,54 : input pin when bit irq7e is set to 1 in ier. it can always be used as the .,1 : or cin7 input pin. p66/ftob/cin6/ .,1 9 / ,54 9 the pin function is switched as shown below according to the combination of the oeb bit in tocr of the frt and the p66ddr bit. oeb 0 1 p66ddr 0 1 p66 input pin p66 output pin ftob output pin pin function ,54 9 input pin, .,1 9 input pin, cin6 input pin * note: * this pin is used as the ,54 9 input pin when bit irq6e is set to 1 in ier while the kmimr6 bit in kmimr is 0. it can always be used as the .,1 9 or cin6 input pin. p65/ftid/cin5/ .,1 8 p65ddr 0 1 p65 input pin p65 output pin pin function ftid input pin, .,1 8 input pin, cin5 input pin * note: * this pin can always be used as the ftid, .,1 8 , or cin5 input pin. p64/ftic/cin4/ .,1 7 /clampo the pin function is switched as shown below according to the combination of the cloe bit in tconro of the timer connection function and the p64ddr bit. cloe 0 1 p64ddr 0 1 p64 input pin p64 output pin clampo output pin pin function ftic input pin, .,1 7 input pin, cin4 input pin * note: * this pin can always be used as the ftic, .,1 7 , or cin4 input pin. rev. 2.0, 08/02, page 179 of 788 p63/ftib/cin3/ .,1 6 /vfbacki p63ddr 0 1 p63 input pin p63 output pin pin function ftib input pin, vfbacki input pin, .,1 6 input pin, cin3 input pin * note: * this pin can always be used as the ftib, .,1 6 , cin3, or vfbacki input pin. p62/ftia/cin2/ .,1 5 /vsynci/tmiy p62ddr 0 1 p62 input pin p62 output pin pin function ftia input pin, vsynci input pin, tmiy input pin, .,1 5 input pin, cin2 input pin * note: * this pin can always be used as the ftia, tmiy, .,1 5 , cin2, or vsynci input pin. p61/ftoa/cin1/ .,1 4 /vsynco the pin function is switched as shown below according to the combination of the oea bit in tocr of the frt, the voe bit in tconro of the timer connection function, and the p61ddr bit. voe 0 1 oea 0 1 p61ddr 0 1 p61 input pin p61 output pin ftoa output pin vsynco output pin pin function .,1 4 input pin, cin1 input pin * note: * when this pin is used as the vsynco pin, bit oea in tocr of the frt must be cleared to 0. this pin can always be used as the .,1 4 or cin1 input pin. p60/ftci/cin0/ .,1 3 /hfbacki/tmix p60ddr 0 1 p60 input pin p60 output pin pin function ftci input pin, hfbacki input pin, tmix input pin, .,1 3 input pin, cin0 input pin * note: * this pin is used as the ftci input pin when an external clock is selected with bits cks1 and cks0 in tcr of the frt. it can always be used as the tmix, .,1 3 , cin0, or hfbacki input pin. rev. 2.0, 08/02, page 180 of 788 8.7.5 port 6 input pull-up mos port 6 has an on-chip input pull-up mos function that can be controlled by software. this input pull-up mos function can be specified as on or off on a bit-by-bit basis. the input pull-up mos current specification can be changed by means of the p6pue bit. when a pin is designated as an on-chip peripheral module output pin, the input pull-up mos is always off. table 8.5 summarizes the input pull-up mos states. table 8.5 input pull-up mos states (port 6) mode reset hardware standby mode software standby mode in other operations 1, 2, 3 off off on/off on/off legend: off: input pull-up mos is always off. on/off: on when the pin is in the input state, p6ddr = 0, and kmpcr = 1; otherwise off. 8.8 port 7 port 7 is an 8-bit input only port. port 7 pins also function as the a/d converter analog input pins and d/a converter analog output pins. port 7 functions are the same in all operating modes. port 7 has the following register. port 7 input data register (p7pin) rev. 2.0, 08/02, page 181 of 788 8.8.1 port 7 input data register (p7pin) p7pin reflects the pin states of port 7. bit bit name initial value r/w description 7 p77pin undefined * r 6 p76pin undefined * r 5 p75pin undefined * r 4 p74pin undefined * r 3 p73pin undefined * r 2 p72pin undefined * r 1 p71pin undefined * r 0 p70pin undefined * r when a p7pin read is performed, the pin states are always read. p7pin has the same address as pbddr; if a write is performed, data will be written into pbddr and the port b setting will be changed. note: * determined by the pin states of p77 to p70. 8.8.2 pin functions p77/an7/da1 the pin function is switched as shown below according to the combination of the dae bit in dacr of the d/a converter and the daoe1 bit. daoe1 0 1 dae 0 1 p77 input pin da1 input pin da1 output pin pin function an7 input pin * note: * this pin can always be used as the an7 input pin. p76/an6/da0 the pin function is switched as shown below according to the combination of the dae bit in dacr of the d/a converter and the daoe0 bit. daoe0 0 1 dae 0 1 p76 input pin da0 output pin da0 output pin pin function an6 input pin * note: * this pin can always be used as the an6 input pin. rev. 2.0, 08/02, page 182 of 788 p75/an5, p74/an4, p73/an3, p72/an2, p71/an1, p70/an0 p75 to p70 input pins pin function an5 to an0 input pin * note: * this pin can always be used as the an5 to an0 input pins. 8.9 port 8 port 8 is an 8-bit i/o port. port 8 pins also function as sci_1 i/o pins, the iic_1 i/o pin, xbs i/o pins, lpc i/o pins, and interrupt input pins. the output type of p86 and sck1 is nmos push-pull output. the output type of scl1 is nmos open drain output and direct bus driving is enabled. port 8 pin functions are the same in all operating modes except host interface function. port 8 has the following registers. port 8 data direction register (p8ddr) port 8 data register (p8dr) 8.9.1 port 8 data direction register (p8ddr) p8ddr specifies input or output for the pins of port 8 on a bit-by-bit basis. bit bit name initial value r/w description 7 1 reserved the initial value must not be changed. 6 p86ddr 0 w 5 p85ddr 0 w 4 p84ddr 0 w 3 p83ddr 0 w 2 p82ddr 0 w 1 p81ddr 0 w 0 p80ddr 0 w p8ddr has the same address as pbpin, and if read, the port b state will be returned. the corresponding port 8 pins are output ports when p8ddr bits are set to 1, and input ports when cleared to 0. rev. 2.0, 08/02, page 183 of 788 8.9.2 port 8 data register (p8dr) p8dr stores output data for the port 8 pins (p86 to p80). bit bit name initial value r/w description 7 1 reserved the initial value must not be changed. 6 p86dr 0 r/w 5 p85dr 0 r/w 4 p84dr 0 r/w 3 p83dr 0 r/w 2 p82dr 0 r/w 1 p81dr 0 r/w 0 p80dr 0 r/w if a port 8 read is performed while p8ddr bits are set to 1, the p8dr values are read directly, regardless of the actual pin states. if a port 8 read is performed while p8ddr bits are cleared to 0, the pin states are read. 8.9.3 pin functions p86/ ,54 8 / sck1/scl1 the pin function is switched as shown below according to the combination of the cke1 and cke0 bits in scr of sci_1, the c/ $ bit in smr of sci_1, the ice bit in iccr of iic_1, and the p86ddr bit. ice 0 1 cke1 0 1 0 c/ $ 010 cke0 0 1 0 p86ddr0 1 p86 input pin p86 output pin sck1 output pin sck1 output pin sck1 input pin scl1 i/o pin pin function ,54 8 input pin * note: * when the irq5e bit in ier is set to 1, this pin is used as the ,54 8 input pin. when this pin is used as the scl1 i/o pin, bits cke1 and cke0 in scr of sci_1 and bit c/ $ in smr of sci_1 must all be cleared to 0. when the p86 output pin and sck1 output pin are set, the output type is nmos push-pull output. scl1 is an nmos-only output, and has direct bus drive capability. rev. 2.0, 08/02, page 184 of 788 p85/ ,54 7 /rxd1 the pin function is switched as shown below according to the combination of the re bit in scr of sci_1 and the p85ddr bit. re 0 1 p85ddr 0 1 p85 input pin p85 output pin rxd1 input pin pin function ,54 7 input pin * note: * when the irq4e bit in ier is set to 1, this pin is used as the ,54 7 input pin. p84/ ,54 6 /txd1 the pin function is switched as shown below according to the combination of the te bit in scr of sci_1 and the p84ddr bit. te 0 1 p84ddr 0 1 p84 input pin p84 output pin txd1 output pin pin function ,54 6 input pin * note: * when the irq3e bit in ier is set to 1, this pin is used as the ,54 6 input pin. p83/ /3&3' * 2 the pin function is switched as shown below according to the p83ddr bit. p83ddr 0 1 p83 input pin p83 output pin pin function /3&3' input pin * 1 * 2 notes: 1. when at least one of bits lpc3e to lpc1e is set to 1 in hicr0, this pin is used as the /3&3' input pin. the /3&3' input pin can only be used in mode 2 or 3 (expe = 0). 2. not supported by the h8s/2148b. rev. 2.0, 08/02, page 185 of 788 p82/hifsd/ &/.581 * 2 the pin function is switched as shown below according to the combination of the hi12e and sde bits in syscr2, the lpc3e to lpc1e bits in hicr0, and the p82ddr bit. lpc3e to lpc1e all 0 not all 0 hi12e 0 1 0 * 1 sde 0 1 p82ddr01010 * 1 pin function p82 input pin p82 output pin p82 input pin p82 output pin hifsd input pin &/.581 i/o pin * 2 notes: the hifsd input pin and &/.581 i/o pin can only be used in mode 2 or 3 (expe = 0). 1. when at least one of bits lpc3e to lpc1e is set to 1, bits hi12e and p82ddr should be cleared to 0. 2. not supported by the h8s/2148b. p81/ &6 5 /ga20 the pin function is switched as shown below according to the combination of the hi12e bit in syscr2, the cs2e bit in syscr, the fga20e bit in hicr, the fga20e bit in hicr0, and the p81ddr bit. fga20e (lpc) 01 hi12e 0 1 0 * 1 fga20e (xbs) 0 1 cs2e 0 1 p81ddr 0 1 0 1 0 1 0 * 1 p81 input pin p81 output pin p81 input pin p81 output pin &6 5 input pin * 2 p81 input pin ga20 output pin ga20 output pin pin function ga20 input pin * 2 notes: 1. when bit fga20e is set to 1 in hicr0, bits hi12e and p81ddr should be cleared to 0. 2. the ga20 output pin and &6 5 input pin can only be used in mode 2 or 3 (expe = 0). rev. 2.0, 08/02, page 186 of 788 p80/ha0/ 30( * 3 the pin function is switched as shown below according to the combination of the hi12e bit in syscr2, the pmee bit in hicr0, and the p80ddr bit. pmee 0 1 hi12e 0 1 0 * 1 p80ddr 0 1 0 * 1 p80 input pin p80 output pin ha0 input pin * 2 30( output pin pin function 30( input pin * 2 * 3 notes: 1. when bit pmee is set to 1 in hicr0, bits hi12e and p80ddr should be cleared to 0. 2. the ha0 input pin can only be used in mode 2 or 3 (expe = 0). 3. not supported by the h8s/2148b. 8.10 port 9 port 9 is an 8-bit i/o port. port 9 pins also function as external interrupt input pins, the a/d converter input pin, host interface (xbs) input pins, the iic_0 i/o pin, the subclock input pin, bus control signal i/o pins, and the system clock (?) output pin. p97 is an nmos push-pull output. sda0 is an nmos open-drain output, and has direct bus drive capability. port 9 has the following registers. port 9 data direction register (p9ddr) port 9 data register (p9dr) rev. 2.0, 08/02, page 187 of 788 8.10.1 port 9 data direction register (p9ddr) p9ddr specifies input or output for the pins of port 9 on a bit-by-bit basis. bit bit name initial value r/w description 7 p97ddr 0 w 6 p96ddr 1/0 * w 5 p95ddr 0 w 4 p94ddr 0 w 3 p93ddr 0 w 2 p92ddr 0 w 1 p91ddr 0 w 0 p90ddr 0 w p9ddr is initialized to h'40 (mode 1) or h'00 (modes 2 and 3). modes 1, 2, and 3 (expe = 1): pin p97 functions as a bus control input ( :$,7 ), the iic_0 i/o pin (sda0), or an i/o port, according to the wait mode setting. when p97 functions as an i/o port, it becomes an output port when p97ddr is set to 1, and an input port when p97ddr is cleared to 0. pin p96 functions as the ? output pin when p96ddr is set to 1, and as the subclock input (excl) or an input port when p96ddr is cleared to 0. pins p95 to p93 automatically become bus control outputs ( $6 / ,26 , +:5 , 5' ), regardless of the input/output direction indicated by p95ddr to p93ddr. pins p92 and p91 become output ports when p92ddr and p91ddr are set to 1, and input ports when p92ddr and p91ddr are cleared to 0. when the abw bit in wscr is cleared to 0, pin p90 becomes a bus control output ( /:5 ), regardless of the input/output direction indicated by p90ddr. when the abw bit is 1, pin p90 becomes an output port if p90ddr is set to 1, and an input port if p90ddr is cleared to 0. modes 2 and 3 (expe = 0): when the corresponding p9ddr bits are set to 1, pin p96 functions as the ? output pin and pins p97 and p95 to p90 become output ports. when p9ddr bits are cleared to 0, the corresponding pins become input ports. note: * the initial value of p96ddr is 1 (mode 1) or 0 (modes 2 and 3). rev. 2.0, 08/02, page 188 of 788 8.10.2 port 9 data register (p9dr) p9dr stores output data for the port 9 pins. bit bit name initial value r/w description 7 p97dr 0 r/w 6 p96dr undefined * r 5 p95dr 0 r/w 4 p94dr 0 r/w 3 p93dr 0 r/w 2 p92dr 0 r/w 1 p91dr 0 r/w 0 p90dr 0 r/w with the exception of p96, if a port 9 read is performed while p9ddr bits are set to 1, the p9dr values are read directly, regardless of the actual pin states. if a port 9 read is performed while p9ddr bits are cleared to 0, the pin states are read. for p96, the pin state is always read. note: * the initial value of bit 6 is determined according to the p96 pin state. 8.10.3 pin functions p97/ :$,7 /sda0 the pin function is switched as shown below according to the combination of operating mode, the wms1 bit in wscr, the ice bit in iccr of iic_0, and the p97ddr bit. operating mode modes 1, 2, 3 (expe = 1) modes 2, 3 (expe = 0) wms1 0 1 ice 0 1 0 1 p97ddr 0 1 0 1 pin function p97 input pin p97 output pin sda0 i/o pin :$,7 input pin p97 input pin p97 output pin sda0 i/o pin note: * when this pin is set as the p97 output pin, it is an nmos push-pull output. sda0 is an nmos open-drain output, and has direct bus drive capability. rev. 2.0, 08/02, page 189 of 788 p96/?/excl the pin function is switched as shown below according to the combination of the excle bit in lpwrcr and the p96ddr bit. p96ddr 0 1 excle 0 1 0 pin function p96 input pin excl input pin ? output pin note: * when this pin is used as the excl input pin, p96ddr should be cleared to 0. p95/ $6 / ,26 / &6 4 the pin function is switched as shown below according to the combination of operating mode, the iose bit in syscr, the hi12e bit in syscr2, and the p95ddr bit. operating mode modes 1, 2, 3 (expe = 1) modes 2, 3 (expe = 0) hi12e 0 1 p95ddr 0 1 iose 0 1 pin function $6 output pin ,26 output pin p95 input pin p95 output pin &6 4 input pin p94/ +:5 / ,2: the pin function is switched as shown below according to the combination of operating mode, the hi12e bit in syscr2, and the p94ddr bit. operating mode modes 1, 2, 3 (expe = 1) modes 2, 3 (expe = 0) hi12e 0 1 p94ddr 0 1 pin function +:5 output pin p94 input pin p94 output pin ,2: input pin rev. 2.0, 08/02, page 190 of 788 p93/ 5' / ,25 the pin function is switched as shown below according to the combination of operating mode, the hi12e bit in syscr2, and the p93ddr bit. operating mode modes 1, 2, 3 (expe = 1) modes 2, 3 (expe = 0) hi12e 0 1 p93ddr 0 1 pin function 5' output pin p93 input pin p93 output pin ,25 input pin p92/ ,54 3 p92ddr 0 1 p92 input pin p92 output pin pin function ,54 3 input pin * note: * when bit irq0e in ier is set to 1, this pin is used as the ,54 3 input pin. p91/ ,54 4 p91ddr 0 1 p91 input pin p91 output pin pin function ,54 4 input pin * note: * when bit irq1e in ier is set to 1, this pin is used as the ,54 4 input pin. rev. 2.0, 08/02, page 191 of 788 p90/ /:5 / ,54 5 / $'75* / (&6 5 the pin function is switched as shown below according to the combination of operating mode, the abw bit in wscr, the hi12e and cs2e bits in syscr2, the fga20e bit in hicr, and the p90ddr bit. operating mode modes 1, 2, 3 (expe = 1) modes 2, 3 (expe = 0) abw 0 1 hi12e 1 fga20e 1 cs2e any one 0 1 p90ddr 0 1 0 1 p90 input pin p90 output pin p90 input pin p90 output pin (&6 5 input pin pin function /:5 output pin ,54 5 input pin, $'75* input pin * note: * when the irq2e bit in ier is set to 1 in mode 1, 2, or 3 (expe = 1) with the abw bit in wscr set to 1, or in mode 2 and 3 (expe = 0), this pin is used as the ,54 5 input pin. when trgs1 and trgs0 in adcr of the a/d converter are both set to 1, this pin is used as the $'75* input pin. 8.11 port a port a is an 8-bit i/o port. port a pins also function as keyboard buffer controller i/o pins, key- sense interrupt input pins, expansion a/d converter input pins, and address output pins. port a pin functions change according to the operating mode. port a input/output operates by vccb power independent from the vcc power. up to 5 v can be applied to port a pins if vccb power is 5 v. port a has the following registers. paddr and papin have the same address. port a data direction register (paddr) port a output data register (paodr) port a input data register (papin) rev. 2.0, 08/02, page 192 of 788 8.11.1 port a data direction register (paddr) paddr specifies input or output for the pins of port a on a bit-by-bit basis. bit bit name initial value r/w description 7 pa7ddr 0 w 6 pa6ddr 0 w 5 pa5ddr 0 w 4 pa4ddr 0 w 3 pa3ddr 0 w 2 pa2ddr 0 w 1 pa1ddr 0 w 0 pa0ddr 0 w in mode 1, 2 (expe = 0), or 3: the corresponding port a pins are output ports when paddr bits are set to 1, and input ports when cleared to 0. in mode 2 (expe = 1): the corresponding port a pins are address output when paddr bits are set to 1, and input ports when cleared to 0. the port a pins changes from the address i/o ports to output ports by setting the iose bit to 1. pa7 to pa2 pins are used as the keyboard buffer controller i/o pins by setting the kbioe bit to 1 regardless of the operating mode, while the i/o direction according to pa7ddr to pa2ddr is ignored. paddr has the same address as papin, if read, port a status is returned. 8.11.2 port a output data register (paodr) paodr stores output data for port a. bit bit name initial value r/w description 7 pa7odr 0 r/w 6 pa6odr 0 r/w 5 pa5odr 0 r/w 4 pa4odr 0 r/w 3 pa3odr 0 r/w 2 pa2odr 0 r/w 1 pa1odr 0 r/w 0 pa0odr 0 r/w paodr can always be read or written to, regardless of the contents of paddr. rev. 2.0, 08/02, page 193 of 788 8.11.3 port a input data register (papin) papin indicates the port a state. bit bit name initial value r/w description 7 pa7pin undefined * r 6 pa6pin undefined * r 5 pa5pin undefined * r 4 pa4pin undefined * r 3 pa3pin undefined * r 2 pa2pin undefined * r 1 pa1pin undefined * r 0 pa0pin undefined * r reading papin always returns the pin states. papin has the same address as paddr. if a write is performed, the port a settings will change. note: * the initial value is determined according to the pa7 to pa0 pin states. 8.11.4 pin functions pa7/a23/ .,1 48 /cin15/ps2cd the pin function is switched as shown below according to the combination of operating mode, the kbioe bit in kbcrh_2 of the keyboard buffer controller, the iose bit in syscr, and the pa7ddr bit. operating mode modes 1, 2 (expe = 0), 3 mode 2 (expe = 1) kbioe 0 1 0 1 pa7ddr 0 1 0 1 iose 0 1 pa7 input pin pa7 output pin ps2cd output pin pa7 input pin a23 output pin pa7 output pin ps2cd output pin pin function .,1 48 input pin, cin15 input pin, ps2cd input pin * note: * when the kbioe bit is set to 1 or the iics bit in stcr is set to 1, this pin is an nmos open-drain output, and has direct bus drive capability. this pin can always be used as the ps2cd, .,1 48 , or cin15 input pin. rev. 2.0, 08/02, page 194 of 788 pa6/a22/ .,1 47 /cin14/ps2cc the pin function is switched as shown below according to the combination of operating mode, the kbioe bit in kbcrh_2 of the keyboard buffer controller, the iose bit in syscr, and the pa6ddr bit. operating mode modes 1, 2 (expe = 0), 3 mode 2 (expe = 1) kbioe 0 1 0 1 pa6ddr 0 1 0 1 iose 0 1 pa6 input pin pa6 output pin ps2cc output pin pa6 input pin a22 output pin pa6 output pin ps2cc output pin pin function .,1 47 input pin, cin14 input pin, ps2cc input pin * note: * when the kbioe bit is set to 1 or the iics bit in stcr is set to 1, this pin is an nmos open-drain output, and has direct bus drive capability. this pin can always be used as the ps2cc, .,1 47 , or cin14 input pin. pa5/a21/ .,1 46 /cin13/ps2bd the pin function is switched as shown below according to the combination of operating mode, the kbioe bit in kbcrh_1 of the keyboard buffer controller, the iose bit in syscr, and the pa5ddr bit. operating mode modes 1, 2 (expe = 0), 3 mode 2 (expe = 1) kbioe 0 1 0 1 pa5ddr 0 1 0 1 iose 0 1 pa5 input pin pa5 output pin ps2bd output pin pa5 input pin a21 output pin pa5 output pin ps2bd output pin pin function .,1 46 input pin, cin13 input pin, ps2bd input pin * note: * when the kbioe bit is set to 1 or the iics bit in stcr is set to 1, this pin is an nmos open-drain output, and has direct bus drive capability. this pin can always be used as the ps2bd, .,1 46 , or cin13 input pin. rev. 2.0, 08/02, page 195 of 788 pa4/a20/ .,1 45 /cin12/ps2bc the pin function is switched as shown below according to the combination of operating mode, the kbioe bit in kbcrh_1 of the keyboard buffer controller, the iose bit in syscr, and the pa4ddr bit. operating mode modes 1, 2 (expe = 0), 3 mode 2 (expe = 1) kbioe 0 1 0 1 pa4ddr 0 1 0 1 iose 0 1 pa4 input pin pa4 output pin ps2bc output pin pa4 input pin a20 output pin pa4 output pin ps2bc output pin pin function .,1 45 input pin, cin12 input pin, ps2bc input pin * note: * when the kbioe bit is set to 1 or the iics bit in stcr is set to 1, this pin is an nmos open-drain output, and has direct bus drive capability. this pin can always be used as the ps2bc, .,1 45 , or cin12 input pin. pa3/a19/ .,1 44 /cin11/ps2ad the pin function is switched as shown below according to the combination of operating mode, the kbioe bit in kbcrh_0 of the keyboard buffer controller, the iose bit in syscr, and the pa3ddr bit. operating mode modes 1, 2 (expe = 0), 3 mode 2 (expe = 1) kbioe 0 1 0 1 pa3ddr 0 1 0 1 iose 0 1 pa3 input pin pa3 output pin ps2ad output pin pa3 input pin a19 output pin pa3 output pin ps2ad output pin pin function .,1 44 input pin, cin11 input pin, ps2ad input pin * note: * when the kbioe bit is set to 1, this pin is an nmos open-drain output, and has direct bus drive capability. this pin can always be used as the ps2ad, .,1 44 , or cin11 input pin. rev. 2.0, 08/02, page 196 of 788 pa2/a18/ .,1 43 /cin10/ps2ac the pin function is switched as shown below according to the combination of operating mode, the kbioe bit in kbcrh_0 of the keyboard buffer controller, the iose bit in syscr, and the pa2ddr bit. operating mode modes 1, 2 (expe = 0), 3 mode 2 (expe = 1) kbioe 0 1 0 1 pa2ddr 0 1 0 1 iose 0 1 pa2 input pin pa2 output pin ps2ac output pin pa2 input pin a18 output pin pa2 output pin ps2ac output pin pin function .,1 43 input pin, cin10 input pin, ps2ac input pin * note: * when the kbioe bit is set to 1, this pin is an nmos open-drain output, and has direct bus drive capability. this pin can always be used as the ps2ac, .,1 43 , or cin10 input pin. pa1/a17/ .,1 < /cin9 the pin function is switched as shown below according to the combination of operating mode, the iose bit in syscr and the pa1ddr bit. operating mode modes 1, 2 (expe = 0), 3 mode 2 (expe = 1) pa1ddr 0 1 0 1 iose 0 1 pa1 input pin pa1 output pin pa1 input pin a17 output pin pa1 output pin pin function .,1 < input pin, cin9 input pin * note: * this pin can always be used as the .,1 < or cin9 input pin. rev. 2.0, 08/02, page 197 of 788 pa0/a16/ # .,1 ; /cin8 the pin function is switched as shown below according to the combination of operating mode, the iose bit in syscr and the pa0ddr bit. operating mode modes 1, 2 (expe = 0), 3 mode 2 (expe = 1) pa0ddr 0 1 0 1 iose 0 1 pa0 input pin pa0 output pin pa0 input pin a16 output pin pa0 output pin pin function .,1 ; input pin, cin8 input pin * note: * this pin can always be used as the .,1 ; or cin8 input pin. 8.11.5 port a input pull-up mos port a has an on-chip input pull-up mos function that can be controlled by software. this input pull-up mos function can be specified as on or off on a bit-by-bit basis. the input pull-up mos for pins pa7 to pa4 is always off when iics is set to 1. when the keyboard buffer control pin function is selected for pins pa7 to pa2, the input pull-up mos is always off. table 8.6 summarizes the input pull-up mos states. table 8.6 input pull-up mos states (port a) mode reset hardware standby mode software standby mode in other operations 1, 2, 3 off off on/off on/off legend off: input pull-up mos is always off. on/off: on when the pin is in the input state, paddr = 0, and paodr = 1; otherwise off. rev. 2.0, 08/02, page 198 of 788 8.12 port b port b is an 8-bit i/o port. port b pins also have xbs input/output pins, lpc input/output pins, wakeup event interrupt input pins, and a data bus input/output function. the pin functions depend on the operating mode. port b has the following registers. port b data direction register (pbddr) port b output data register (pbodr) port b input data register (pbpin) 8.12.1 port b data direction register (pbddr) pbddr specifies input or output for the pins of port b on a bit-by-bit basis. bit bit name initial value r/w description 7 pb7ddr 0 w 6 pb6ddr 0 w 5 pb5ddr 0 w 4 pb4ddr 0 w 3 pb3ddr 0 w 2 pb2ddr 0 w 1 pb1ddr 0 w 0 pb0ddr 0 w pbddr has the same address as p7pin, and if read, the port 7 pin states will be returned. modes 1, 2, and 3 (expe = 1) when the abw bit in wscr is cleared to 0, port b pins automatically become data i/o pins (d7 to d0), regardless of the input/output direction indicated by pbddr. when the abw bit is 1, a port b pin becomes an output port if the corresponding pbddr bit is set to 1, and an input port if the bit is cleared to 0. modes 2 and 3 (expe = 0) a port b pin becomes an output port if the corresponding pbddr bit is set to 1, and an input port if the bit is cleared to 0. rev. 2.0, 08/02, page 199 of 788 8.12.2 port b output data register (pbodr) pbodr stores output data for port b. bit bit name initial value r/w description 7 pb7odr 0 r/w 6 pb6odr 0 r/w 5 pb5odr 0 r/w 4 pb4odr 0 r/w 3 pb3odr 0 r/w 2 pb2odr 0 r/w 1 pb1odr 0 r/w 0 pb0odr 0 r/w pbodr can always be read or written to, regardless of the contents of pbddr. 8.12.3 port b input data register (pbpin) pbpin indicates the port b state. bit bit name initial value r/w description 7 pb7pin undefined * r 6 pb6pin undefined * r 5 pb5pin undefined * r 4 pb4pin undefined * r 3 pb3pin undefined * r 2 pb2pin undefined * r 1 pb1pin undefined * r 0 pb0pin undefined * r reading pbpin always returns the pin states. pbpin has the same address as p8ddr. if a write is performed, data will be written to p8ddr and the port 8 settings will change. note: * the initial value is determined according to the pb7 to pb0 pin states. rev. 2.0, 08/02, page 200 of 788 8.12.4 pin functions pb7/d7/ :8( : * 2 , pb6/d6/ :8( 9 * 2 , pb5/d5/ :8( 8 * 2 , pb4/d4/ :8( 7 * 2 the pin function is switched as shown below according to the combination of the operating mode, the pbnddr bit, and the abw bit in wscr. operating mode mode 1 and modes 2, 3 (expe = 1) modes 2, 3 (expe = 0) abw 0 1 pbnddr 0 1 0 1 pbn input pin pbn output pin pbn input pin pbn output pin pin function dn i/o pin :8(q input pin * 1 notes: 1. except when used as a data bus pin, this pin can always be used as the :8(q input pin. (n = 7 to 4) 2. not supported by the h8s/2148b. pb3/d3/ :8( 6 * 2 / &6 7 the pin function is switched as shown below according to the combination of the operating mode, the hi12e and cs4e bits in syscr2, the abw bit in wscr, and the pb3ddr bit. operating mode mode 1 and modes 2, 3 (expe = 1) modes 2, 3 (expe = 0) hi12e 1 cs4e either cleared to 0 1 abw 0 1 pb3ddr 0 1 0 1 pb3 input pin pb3 output pin pb3 input pin pb3 output pin &6 7 input pin pin function d3 i/o pin :8( 6 input pin * 1 notes: 1. except when used as a data bus pin, this pin can always be used as the :8( 6 input pin. the &6 7 input pin can only be used in mode 2 or 3 (expe = 0). 2. not supported by the h8s/2148b. rev. 2.0, 08/02, page 201 of 788 pb2/d2/ :8( 5 * 2 / &6 6 the pin function is switched as shown below according to the combination of the operating mode, the hi12e and cs3e bits in syscr2, the abw bit in wscr, and the pb2ddr bit. operating mode mode 1 and modes 2, 3 (expe = 1) modes 2, 3 (expe = 0) hi12e 1 cs3e either cleared to 0 1 abw 0 1 pb2ddr 0 1 0 1 pb2 input pin pb2 output pin pb2 input pin pb2 output pin &6 6 input pin pin function d2 i/o pin :8( 5 input pin * 1 notes: 1. except when used as a data bus pin, this pin can always be used as the :8( 5 input pin. the &6 6 input pin can only be used in mode 2 or 3 (expe = 0). 2. not supported by the h8s/2148b. pb1/d1/ :8( 4 /hirq4/lsci* 4 the pin function is switched as shown below according to the combination of the operating mode, the hi12e and cs4e bits in syscr2, the lscie bits in hicr0 of host interface (lpc), the abw bit in wscr, and the pb1ddr bit. operating mode modes 1, 2, 3 (expe = 1) mode 2, 3 (expe = 0) lscie 0 * 3 01 hi12e 1 0 * 1 cs4e either cleared to 0 1 abw 0 1 pb1ddr 0 1 0 1 0 * 1 pb1 input pin pb1 output pin hirq4 output pin lsci * 4 output pin pb1 input pin pb1 output pin lsci input pin * 2 pin function d1 i/o pin :8( 4 input pin * 2 * 4 notes: 1. when bit lscie is set to 1 in hicr0, bits hi12e and pb1ddr should be cleared to 0. 2. except when used as a data bus pin, this pin can always be used as the :8( 4 input pin. the hirq4 output pin and lsci i/o pin can only be used in mode 2 or 3 (expe = 0). 3. in mode 1, 2, 3 (expe = 1), clear the lscie bit to 0. 4. not supported by the h8s/2148b. rev. 2.0, 08/02, page 202 of 788 pb0/d0/ :8( 3 /hirq3/ /60, * 4 the pin function is switched as shown below according to the combination of the operating mode, the hi12e and cs3e bits in syscr2, the lsmie bits in hicr0 of host interface (lpc), the abw bit in wscr, and the pb0ddr bit. operating mode modes 1, 2, 3 (expe = 1) mode 2, 3 (expe = 0) lsmie 0 * 3 01 hi12e 1 0 * 1 cs3e either cleared to 0 1 abw 0 1 pb0ddr 0 1 0 1 0 * 1 pb0 input pin pb0 output pin hirq3 output pin /60, * 4 output pin pb0 input pin pb0 output pin /60, input pin * 2 pin function d0 i/o pin :8( 3 input pin * 2 notes: 1. when bit lsmie is set to 1 in hicr0, bits hi12e and pb0ddr should be cleared to 0. 2. except when used as a data bus pin, this pin can always be used as the :8( 3 input pin. the hirq3 output pin and /60, i/o pin can only be used in mode 2 or 3 (expe = 0). 3. in mode 1, 2, 3 (expe = 1), clear the lsmie bit to 0. 4. not supported by the h8s/2148b. 8.12.5 port b input pull-up mos port b has an on-chip input pull-up mos function that can be controlled by software. this input pull-up mos function can be specified as on or off on a bit-by-bit basis. when a pin is designated as an on-chip peripheral module output pin, the input pull-up mos is always off. rev. 2.0, 08/02, page 203 of 788 table 8.7 summarizes the input pull-up mos states. table 8.7 input pull-up mos states (port b) mode reset hardware standby mode software standby mode in other operations 1, 2, 3 (expe = 1) with abw in wscr = 0 off off 1, 2, 3 (expe = 1) with abw in wscr = 1, or 2, 3 (expe = 0) off off on/off on/off legend off: input pull-up mos is always off. on/off: on when the pin is in the input state, pbddr = 0, and pbodr = 1; otherwise off. 8.13 additional overview for h8s/2160b and h8s/2161b the h8s/2160b and h8s/2161b has fifteen i/o ports (ports 1 to 6, 8, 9, a, b, c, d, e, f, g), and one input-only port (port 7). table 8.8 is a summary of the additional port functions. as the functions of ports 1 to 9, a, and b are the same on the h8s/2140b, h8s/2141b, h8s/2148b, and h8s/2145b, table 8.1 provides a summary. each extra port includes a data direction register (ddr) that controls input/output, and data registers (odr) for storing output data. ports c, d, e, and f have an on-chip input pull-up mos function. on ports c, d, e, and f, whether the input pull-up mos is on or off is controlled by the corresponding ddr and odr. ports c, d, e, f, and g can drive a single-ttl load and 30-pf-capacitive load. all i/o port pins are capable of driving a darlington transistor when they are in output. the output type on port g is nmos push-pull output. port g can be 5-v tolerant. when port g is used as an output pin, connect a pull-up resistor to the pin for raise an output high- level voltage. rev. 2.0, 08/02, page 204 of 788 table 8.8 h8s/2160b, h8s/2161b additional port functions mode 2, 3 port description mode 1 (expe = 1) (expe = 0) i/o status port c 8-bit i/o port pc7 to pc0 on-chip input pull-up moss port d 8-bit i/o port pd7 to pd0 on-chip input pull-up moss port e 8-bit i/o port pe7 to pe0 on-chip input pull-up moss port f 8-bit i/o port pf7 to pf0 on-chip input pull-up moss port g 8-bit i/o port pg7 to pg0 8.14 ports c, d port c and port d are two sets of 8-bit i/o ports. the pin functions are the same in all operating modes. port c data direction register (pcddr) port c output data register (pcodr) port c input data register (pcpin) port c nch-od control register (pcnocr) port d data direction register (pdddr) port d output data register (pdodr) port d input data register (pdpin) port d nch-od control register (pdnocr) rev. 2.0, 08/02, page 205 of 788 8.14.1 port c and port d data direction registers (pcddr, pdddr) pcddr and pdddr select input or output for the pins of port c and port d on a bit-by-bit basis. bit bit name initial value r/w description 7 pc7ddr 0 w 6 pc6ddr 0 w 5 pc5ddr 0 w 4 pc4ddr 0 w 3 pc3ddr 0 w 2 pc2ddr 0 w 1 pc1ddr 0 w 0 pc0ddr 0 w 0: port c pin is an input pin 1: port c pin is an output pin pcddr has the same address as pcpin, and if read, the port c pin states will be returned. bit bit name initial value r/w description 7 pd7ddr 0 w 6 pd6ddr 0 w 5 pd5ddr 0 w 4 pd4ddr 0 w 3 pd3ddr 0 w 2 pd2ddr 0 w 1 pd1ddr 0 w 0 pd0ddr 0 w 0: port d pin is an input pin 1: port d pin is an output pin pdddr has the same address as pdpin, and if read, the port d pin states will be returned. rev. 2.0, 08/02, page 206 of 788 8.14.2 port c and port d output data registers (pcodr, pdodr) pcodr and pdodr store output data for the pins on ports c and d. bit bit name initial value r/w description 7 pc7odr 0 r/w 6 pc6odr 0 r/w 5 pc5odr 0 r/w 4 pc4odr 0 r/w 3 pc3odr 0 r/w 2 pc2odr 0 r/w 1 pc1odr 0 r/w 0 pc0odr 0 r/w pcodr can always be read or written to, regardless of the contents of pcddr. bit bit name initial value r/w description 7 pd7odr 0 r/w 6 pd6odr 0 r/w 5 pd5odr 0 r/w 4 pd4odr 0 r/w 3 pd3odr 0 r/w 2 pd2odr 0 r/w 1 pd1odr 0 r/w 0 pd0odr 0 r/w pdodr can always be read or written to, regardless of the contents of pdddr. rev. 2.0, 08/02, page 207 of 788 8.14.3 port c and port d input data registers (pcpin, pdpin) reading pcpin and pdpin always returns the pin states. bit bit name initial value r/w description 7 pc7pin undefined * r 6 pc6pin undefined * r 5 pc5pin undefined * r 4 pc4pin undefined * r 3 pc3pin undefined * r 2 pc2pin undefined * r 1 pc1pin undefined * r 0 pc0pin undefined * r pcpin indicates the port c state. pcpin has the same address as pcddr. if a write is performed, the port c settings will change. note: * the initial value is determined according to the pc7 to pc0 pin states. bit bit name initial value r/w description 7 pd7pin undefined * r 6 pd6pin undefined * r 5 pd5pin undefined * r 4 pd4pin undefined * r 3 pd3pin undefined * r 2 pd2pin undefined * r 1 pd1pin undefined * r 0 pd0pin undefined * r pdpin indicates the port d state. pdpin has the same address as pdddr. if a write is performed, the port d settings will change. note: * the initial value is determined according to the pd7 to pd0 pin states. rev. 2.0, 08/02, page 208 of 788 8.14.4 port c and port d nch-od control register (pcnocr, pdnocr) pcnocr and pdnocr specify the output driver type for pins on ports c and d which are configured as outputs on a bit-by-bit basis. bit bit name initial value r/w description 7 pc7nocr 0 r/w 6 pc6nocr 0 r/w 5 pc5nocr 0 r/w 4 pc4nocr 0 r/w 3 pc3nocr 0 r/w 2 pc2nocr 0 r/w 1 pc1nocr 0 r/w 0 pc0nocr 0 r/w 0: cmos (p-channel driver enabled) 1: n-channel open drain (p-channel driver disabled) bit bit name initial value r/w description 7 pd7nocr 0 r/w 6 pd6nocr 0 r/w 5 pd5nocr 0 r/w 4 pd4nocr 0 r/w 3 pd3nocr 0 r/w 2 pd2nocr 0 r/w 1 pd1nocr 0 r/w 0 pd0nocr 0 r/w 0: cmos (p-channel driver enabled) 1: n-channel open drain (p-channel driver disabled) 8.14.5 pin functions ddr 0 1 nocr 0 1 odr 010101 n-ch. driver off on off on off p-ch. driver off off on off input pull-up mos off on off pin function input pin output pin rev. 2.0, 08/02, page 209 of 788 8.14.6 input pull-up mos in ports c and d port c and port d have an on-chip input pull-up mos function that can be controlled by software. this input pull-up mos function can be switched on or off on a bit-by-bit basis. table 8.9 is a summary of the input pull-up mos states. table 8.9 input pull-up mos states (port c and port d) mode reset hardware standby mode software standby mode other operations 1, 2, 3 off off on/off on/off legend off: input pull-up mos is always off. on/off: on when pcddr = 0 and pcodr = 1 (pdddr = 0 and pdodr = 1); otherwise off. 8.15 ports e, f port e and port f are two sets of 8-bit i/o ports. the pins of ports e and f have the same functions in all operating modes. port e data direction register (peddr) port e output data register (peodr) port e input data register (pepin) port e nch-od control register (penocr) port f data direction register (pfddr) port f output data register (pfodr) port f input data register (pfpin) port f nch-od control register (pfnocr) rev. 2.0, 08/02, page 210 of 788 8.15.1 port e and port f data direction registers (peddr, pfddr) peddr and pfddr select input or output for the pins of port e and port f on a bit-by-bit basis. bit bit name initial value r/w description 7 pe7ddr 0 w 6 pe6ddr 0 w 5 pe5ddr 0 w 4 pe4ddr 0 w 3 pe3ddr 0 w 2 pe2ddr 0 w 1 pe1ddr 0 w 0 pe0ddr 0 w 0: port e pin is an input pin 1: port e pin is an output pin peddr has the same address as pepin, and if read, the port e pin states will be returned. bit bit name initial value r/w description 7 pf7ddr 0 w 6 pf6ddr 0 w 5 pf5ddr 0 w 4 pf4ddr 0 w 3 pf3ddr 0 w 2 pf2ddr 0 w 1 pf1ddr 0 w 0 pf0ddr 0 w 0: port f pin is an input pin 1: port f pin is an output pin pfddr has the same address as pfpin, and if read, the port f pin states will be returned. rev. 2.0, 08/02, page 211 of 788 8.15.2 port e and port f output data registers (peodr, pfodr) peodr and pfodr store output data for the pins on ports e and f. bit bit name initial value r/w description 7 pe7odr 0 r/w 6 pe6odr 0 r/w 5 pe5odr 0 r/w 4 pe4odr 0 r/w 3 pe3odr 0 r/w 2 pe2odr 0 r/w 1 pe1odr 0 r/w 0 pe0odr 0 r/w peodr can always be read or written to, regardless of the contents of peddr. bit bit name initial value r/w description 7pf7odr0 r/w 6pf6odr0 r/w 5pf5odr0 r/w 4pf4odr0 r/w 3pf3odr0 r/w 2pf2odr0 r/w 1pf1odr0 r/w 0pf0odr0 r/w pfodr can always be read or written to, regardless of the contents of pfddr. rev. 2.0, 08/02, page 212 of 788 8.15.3 port e and port f input data registers (pepin, pfpin) reading pepin and pfpin always returns the pin states. bit bit name initial value r/w description 7 pe7pin undefined * r 6 pe6pin undefined * r 5 pe5pin undefined * r 4 pe4pin undefined * r 3 pe3pin undefined * r 2 pe2pin undefined * r 1 pe1pin undefined * r 0 pe0pin undefined * r pepin indicates the port e state. pepin has the same address as peddr. if a write is performed, the port e settings will change. note: * the initial value is determined according to the pe7 to pe0 pin states. bit bit name initial value r/w description 7 pf7pin undefined * r 6 pf6pin undefined * r 5 pf5pin undefined * r 4 pf4pin undefined * r 3 pf3pin undefined * r 2 pf2pin undefined * r 1 pf1pin undefined * r 0 pf0pin undefined * r pfpin indicates the port f state. pfpin has the same address as pfddr. if a write is performed, the port f settings will change. note: * the initial value is determined according to the pf7 to pf0 pin states. rev. 2.0, 08/02, page 213 of 788 8.15.4 port e and port f nch-od control register (penocr, pfnocr) penocr and pfnocr specify the output driver type for pins on ports e and f which are configured as outputs on a bit-by-bit basis. bit bit name initial value r/w description 7 pe7nocr 0 r/w 6 pe6nocr 0 r/w 5 pe5nocr 0 r/w 4 pe4nocr 0 r/w 3 pe3nocr 0 r/w 2 pe2nocr 0 r/w 1 pe1nocr 0 r/w 0 pe0nocr 0 r/w 0: cmos (p-channel driver enabled) 1: n-channel open drain (p-channel driver disabled) bit bit name initial value r/w description 7 pf7nocr 0 r/w 6 pf6nocr 0 r/w 5 pf5nocr 0 r/w 4 pf4nocr 0 r/w 3 pf3nocr 0 r/w 2 pf2nocr 0 r/w 1 pf1nocr 0 r/w 0 pf0nocr 0 r/w 0: cmos (p-channel driver enabled) 1: n-channel open drain (p-channel driver disabled) 8.15.5 pin functions ddr 0 1 nocr 0 1 odr 010101 n-ch. driver off on off on off p-ch. driver off off on off input pull-up mos off on off pin function input pin output pin rev. 2.0, 08/02, page 214 of 788 8.15.6 input pull-up mos in ports e and f port e and port f have an on-chip input pull-up mos function that can be controlled by software. this input pull-up mos function can be switched on or off on a bit-by-bit basis. table 8.10 is a summary of the input pull-up mos states. table 8.10 input pull-up mos states (port e and port f) mode reset hardware standby mode software standby mode other operations 1, 2, 3 off off on/off on/off legend off: input pull-up mos is always off. on/off: on when peddr = 0 and peodr = 1 (pfddr = 0 and pfodr = 1); otherwise off. 8.16 port g port g is an 8-bit i/o port. port g pin functions are the same in all operating modes. the output type of port g is nmos open-drain. port g data direction register (pgddr) port g output data register (pgodr) port g input data register (pgpin) port g nch-od control register (pgnocr) 8.16.1 port g data direction register (pgddr) pgddr selects input or output for the pins of port g on a bit-by-bit basis. bit bit name initial value r/w description 7 pg7ddr 0 w 6 pg6ddr 0 w 5 pg5ddr 0 w 4 pg4ddr 0 w 3 pg3ddr 0 w 2 pg2ddr 0 w 1 pg1ddr 0 w 0 pg0ddr 0 w 0: port g pin is an input pin 1: port g pin is an output pin pgddr has the same address as pgpin, and if read, the port g pin states will be returned. rev. 2.0, 08/02, page 215 of 788 8.16.2 port g output data register (pgodr) pgodr stores output data for the pins on port g. bit bit name initial value r/w description 7 pg7odr 0 r/w 6 pg6odr 0 r/w 5 pg5odr 0 r/w 4 pg4odr 0 r/w 3 pg3odr 0 r/w 2 pg2odr 0 r/w 1 pg1odr 0 r/w 0 pg0odr 0 r/w pgodr can always be read or written to, regardless of the contents of pgddr. 8.16.3 port g input data register (pgpin) reading pgpin always returns the pin states. bit bit name initial value r/w description 7 pg7pin undefined * r 6 pg6pin undefined * r 5 pg5pin undefined * r 4 pg4pin undefined * r 3 pg3pin undefined * r 2 pg2pin undefined * r 1 pg1pin undefined * r 0 pg0pin undefined * r pgpin indicates the port g state. pgpin has the same address as pgddr. if a write is performed, the port g settings will change. note: * the initial value is determined according to the pg7 to pg0 pin states. rev. 2.0, 08/02, page 216 of 788 8.16.4 port g nch-od control register (pgnocr) pgnocr specifies the output driver type for pins on port g which are configured as outputs on a bit-by-bit basis. bit bit name initial value r/w description 7 pg7nocr 0 r/w 6 pg6nocr 0 r/w 5 pg5nocr 0 r/w 4 pg4nocr 0 r/w 3 pg3nocr 0 r/w 2 pg2nocr 0 r/w 1 pg1nocr 0 r/w 0 pg0nocr 0 r/w 0: nmos push-pull (vcc-side n-channel driver enabled) 1: vss-side n-channel open drain (vcc-side n- channel driver disabled) 8.16.5 pin functions ddr 0 1 nocr 0 1 odr 010101 v ss -side n-ch. driver off on off on off v cc -side n-ch. driver off off on off pin function input pin output pin rev. 2.0, 08/02, page 217 of 788 section 9 8-bit pwm timer (pwm) this lsi has an on-chip pulse width modulation (pwm) timer with sixteen outputs. sixteen output waveforms are generated from a common time base, enabling pwm output with a high carrier frequency to be produced using pulse division. 9.1 features operable at a maximum carrier frequency of 625 khz using pulse division (at 10 mhz operation) duty cycles from 0 to 100% with 1/256 resolution (100% duty realized by port output) direct or inverted pwm output, and pwm output enable/disable control pwm0800a_010020020700 rev. 2.0, 08/02, page 218 of 788 figure 9.1 shows a block diagram of the pwm timer. p10/pw0 p11/pw1 p12/pw2 p13/pw3 p14/pw4 p15/pw5 p16/pw6 p17/pw7 p20/pw8 p21/pw9 p22/pw10 p23/pw11 p24/pw12 p25/pw13 p26/pw14 p27/pw15 comparator 0 comparator 1 comparator 2 comparator 3 comparator 4 comparator 5 comparator 6 comparator 7 comparator 8 comparator 9 comparator 10 comparator 11 comparator 12 comparator 13 comparator 14 comparator 15 pwdr0 pwdr1 pwdr2 pwdr3 pwdr4 pwdr5 pwdr6 pwdr7 pwdr8 pwdr9 pwdr10 pwdr11 pwdr12 pwdr13 pwdr14 pwdr15 tcnt pwsl ? ?/8 pwdprb pwoerb p2ddr p2dr pwdpra pwoera p1ddr p1dr legend pwsl pwdr pwdpra pwdprb pwoera pwoerb pcsr p1ddr p2ddr p1dr p2dr : pwm register select : pwm data register : pwm data polarity register a : pwm data polarity register b : pwm output enable register a : pwm output enable register b : peripheral clock select register : port 1 data direction register : port 2 data direction register : port 1 data register : port 2 data register pcsr ?/2 ?/4 ?/16 port/pwm output control module data bus internal data bus bus interface select clock internal clock figure 9.1 block diagram of pwm timer rev. 2.0, 08/02, page 219 of 788 9.2 input/output pin table 9.1 shows the pwm output pins. table 9.1 pin configuration name abbreviation i/o function pwm output 15 to 0 pw15 to pw0 output pwm timer pulse output 15 to 0 9.3 register descriptions the pwm has the following registers. to access pcsr, the flshe bit in the serial timer control register (stcr) must be cleared to 0. for details on the serial timer control register (stcr), see section 3.2.3, serial timer control register (stcr). pwm register select (pwsl) pwm data registers 0 to 15 (pwdr0 to pwdr15) pwm data polarity register a (pwdpra) pwm data polarity register b (pwdprb) pwm output enable register a (pwoera) pwm output enable register b (pwoerb) peripheral clock select register (pcsr) rev. 2.0, 08/02, page 220 of 788 9.3.1 pwm register select (pwsl) pwsl is used to select the input clock and the pwm data register. bit bit name initial value r/w description 7 6 pwcke pwcks 0 0 r/w r/w pwm clock enable pwm clock select these bits, together with bits pwckb and pwcka in pcsr, select the internal clock input to tcnt in the pwm. for details, see table 9.2. the resolution, pwm conversion period, and carrier frequency depend on the selected internal clock, and can be obtained from the following equations. resolution (minimum pulse width) = 1/internal clock frequency pwm conversion period = resolution 256 carrier frequency = 16/pwm conversion period with a 10 mhz system clock (?), the resolution, pwm conversion period, and carrier frequency are as shown in table 9.3. 5 1 r reserved this bit is always read as 1 and cannot be modified. 4 0 r reserved this bit is always read as 0 and cannot be modified. rev. 2.0, 08/02, page 221 of 788 bit bit name initial value r/w description 3 2 1 0 rs3 rs2 rs1 rs0 0 0 0 0 r/w r/w r/w r/w register select these bits select the pwm data register. 0000: pwdr0 selected 0001: pwdr1 selected 0010: pwdr2 selected 0011: pwdr3 selected 0100: pwdr4 selected 0101: pwdr5 selected 0110: pwdr6 selected 0111: pwdr7 selected 1000: pwdr8 selected 1001: pwdr9 selected 1010: pwdr10 selected 1011: pwdr11 selected 1100: pwdr12 selected 1101: pwdr13 selected 1110: pwdr14 selected 1111: pwdr15 selected table 9.2 internal clock selection pwsl pcsr pwcke pwcks pwckb pwcka description 0 clock input is disabled (initial value) 0 ? (system clock) is selected 0 ?/2 is selected 0 1 ?/4 is selected 0 ?/8 is selected 1 1 1 1 ?/16 is selected rev. 2.0, 08/02, page 222 of 788 table 9.3 resolution, pwm conversion period and carrier frequency when ? = 10 mhz internal clock frequency resolution pwm conversion period carrier frequency ? 100 ns 25.6 m s 625 khz ?/2 200 ns 51.2 m s 312.5 khz ?/4 400 ns 102.4 m s 156.3 khz ?/8 800 ns 204.8 m s 78.1 khz ?/16 1600 ns 409.6 m s 39.1 khz 9.3.2 pwm data registers (pwdr0 to pwdr15) pwdr are 8-bit readable/writable registers. the pwm has sixteen pwm data registers. each pwdr specifies the duty cycle of the basic pulse to be output, and the number of additional pulses. the value set in pwdr corresponds to a 0 or 1 ratio in the conversion period. the upper four bits specify the duty cycle of the basic pulse as 0/16 to 15/16 with a resolution of 1/16. the lower four bits specify how many extra pulses are to be added within the conversion period comprising 16 basic pulses. thus, a specification of 0/256 to 255/256 is possible for 0/1 ratios within the conversion period. for 256/256 (100%) output, port output should be used. pwdr0 to pwdr15 are initialized to h00. 9.3.3 pwm data polarity registers a and b (pwdpra, pwdprb) each pwdpr selects the pwm output phase. pwdpra bit bit name initial value r/w description 7 6 5 4 3 2 1 0 os7 os6 os5 os4 os3 os2 os1 os0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w output select 7 to 0 these bits select the pwm output phase. bits os7 to os0 correspond to outputs pw7 to pw0. 0: pwm direct output (pwdr value corresponds to high width of output) 1: pwm inverted output (pwdr value corresponds to low width of output) rev. 2.0, 08/02, page 223 of 788 pwdprb bit bit name initial value r/w description 7 6 5 4 3 2 1 0 os15 os14 os13 os12 os11 os10 os9 os8 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w output select 15 to 8 these bits select the pwm output phase. bits os15 to os8 correspond to outputs pw15 to pw8. 0: pwm direct output (pwdr value corresponds to high width of output) 1: pwm inverted output (pwdr value corresponds to low width of output) 9.3.4 pwm output enable registers a and b (pwoera, pwoerb) each pwoer switches between pwm output and port output. pwoera bit bit name initial value r/w description 7 6 5 4 3 2 1 0 oe7 oe6 oe5 oe4 oe3 oe2 oe1 oe0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w output enable 7 to 0 these bits, together with p1ddr, specify the p1n/pwn pin state. bits oe7 to oe0 correspond to outputs pw7 to pw0. p1nddr oen: pin state 0x: port input 10: port output or pwm 256/256 output 11: pwm output (0 to 255/256 output) legend x: don't care rev. 2.0, 08/02, page 224 of 788 pwoerb bit bit name initial value r/w description 7 6 5 4 3 2 1 0 oe15 oe14 oe13 oe12 oe11 oe10 oe9 oe8 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w output enable 15 to 8 these bits, together with p2ddr, specify the p2n/pwn pin state. bits oe15 to oe8 correspond to outputs pw15 to pw8. p2nddr oen: pin state 0x: port input 10: port output or pwm 256/256 output 11: pwm output (0 to 255/256 output) legend x: don't care to perform pwm 256/256 output when ddr = 1 and oe = 0, the corresponding pin should be set to port output. the corresponding pin can be set as port output in single-chip mode or when iose = 1 and cs256e = 0 in syscr in extended mode with on-chip rom. otherwise, it should be noted that an address bus is output to the corresponding pin. dr data is output when the corresponding pin is used as port output. a value corresponding to pwm 256/256 output is determined by the os bit, so the value should have been set to dr beforehand. 9.3.5 peripheral clock select register (pcsr) pcsr selects the pwm input clock. bit bit name initial value r/w description 3 0 r reserved this bit is always read as 0. the initial value should not be changed. 2 1 pwckb pwcka 0 0 r/w r/w pwm clock select b, a together with bits pwcke and pwcks in pwsl, these bits select the internal clock input to tcnt in the pwm. for details, see table 9.2. 0 0 r reserved this bit is always read as 0. the initial value should not be changed. rev. 2.0, 08/02, page 225 of 788 9.4 operation the upper four bits of pwdr specify the duty cycle of the basic pulse as 0/16 to 15/16 with a resolution of 1/16. table 9.4 shows the duty cycles of the basic pulse. table 9.4 duty cycle of basic pulse 0123456789abcdef0 upper 4 bits basic pulse waveform (internal) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 the lower four bits of pwdr specify the position of pulses added to the 16 basic pulses. an additional pulse adds a high period (when os = 0) with a width equal to the resolution before the rising edge of a basic pulse. when the upper four bits of pwdr are 0000, there is no rising edge of the basic pulse, but the timing for adding pulses is the same. table 9.5 shows the positions of the additional pulses added to the basic pulses, and figure 9.2 shows an example of additional pulse timing. rev. 2.0, 08/02, page 226 of 788 table 9.5 position of pulses added to basic pulses basic pulse no. lower 4 bits0123456789101112131415 0000 0001 yes 0010 yes yes 0011 yes yes yes 0100 yes yes yes yes 0101 yes yes yes yes yes 0110 yes yes yes yes yes yes 0111 yes yes yes yes yes yes yes 1000 yes yes yes yes yes yes yes yes 1001 yes yes yes yes yes yes yes yes yes 1010 yes yes yes yes yes yes yes yes yes yes 1011 yes yes yes yes yes yes yes yes yes yes yes 1100 yes yes yes yes yes yes yes yes yes yes yes yes 1101 yes yes yes yes yes yes yes yes yes yes yes yes yes 1110 yes yes yes yes yes yes yes yes yes yes yes yes yes yes 1111 yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes no additional pulse with additional pulse resolution width basic pulse figure 9.2 example of additional pulse timing (when upper 4 bits of pwdr = 1000) 9.5 usage note 9.5.1 module stop mode setting pwm operation can be enabled or disabled using the module stop control register. the initial setting is for pwm operation to be halted. register access is enabled by canceling the module stop mode. for details, refer to section 26, power-down modes. rev. 2.0, 08/02, page 227 of 788 section 10 14-bit pwm timer (pwmx) this lsi has an on-chip 14-bit pulse-width modulator (pwm) timer with two output channels. it can be connected to an external low-pass filter to operate as a 14-bit d/a converter. 10.1 features division of pulse into multiple base cycles to reduce ripple two resolution settings the resolution can be set equal to one or two system clock cycles. two base cycle settings the base cycle can be set equal to t 64 or t 256, where t is the resolution. four operating speeds four operation clocks (by combination of two resolution settings and two base cycle settings) figure 10.1 shows a block diagram of the pwm (d/a) module. select clock bus interface clock internal data bus comparator a comparator b dadra dadrb pwx1 internal clock ? ?/2 pwx0 fineCadjustment pulse addition fineCadjustment pulse addition legend dacr dadra dadrb dacnt : pwm d/a control register : pwm d/a data register a : pwm d/a data register b : pwm d/a counter dacnt dacr control logic base cycle compare match a base cycle compare match b base cycle overflow module data bus figure 10.1 pwm (d/a) block diagram pwm1411a_010020020700 rev. 2.0, 08/02, page 228 of 788 10.2 input/output pins table 10.1 lists the pwm (d/a) module input and output pins. table 10.1 pin configuration name abbreviation i/o function pwm output pin x0 pwx0 output pwm output of pwmx channel a pwm output pin x1 pwx1 output pwm output of pwmx channel b 10.3 register descriptions the pwm (d/a) module has the following registers. the pwm (d/a) registers are assigned to the same addresses with other registers. the registers are selected by the iice bit in the serial timer control register (stcr). for details on stcr, see section 3.2.3, serial timer control register (stcr). pwm (d/a) counter h (dacnth) pwm (d/a) counter l (dacntl) pwm (d/a) data register ah (dadrah) pwm (d/a) data register al (dadral) pwm (d/a) data register bh (dadrbh) pwm (d/a) data register bl (dadrbl) pwm (d/a) control register (dacr) note: the same addresses are shared by dadra and dacr, and by dadrb and dacnt. switching is performed by the regs bit in dacnt or dadrb. 10.3.1 pwm (d/a) counters h and l (dacnth, dacntl) dacnt is a 14-bit readable/writable up-counter. the input clock is selected by the clock select bit (cks) in dacr. dacnt functions as the time base for both pwm (d/a) channels. when a channel operates with 14-bit precision, it uses all dacnt bits. when a channel operates with 12- bit precision, it uses the lower 12 bits and ignores the upper two bits. since dacnt consists of 16-bit data, dacnt transfers data to the cpu via the temporary register (temp). for details, refer to section 10.4, bus master interface. rev. 2.0, 08/02, page 229 of 788 15 7 dacnth dacntl 14 6 13 5 12 4 11 3 10 2 9 1 8 0 7 8 6 9 5 10 4 11 3 12 2 13 1 - 0 - bit (cpu) bit (counter) : : - regs dacnth bit bit name initial value r/w description 7 to 0 uc7 to uc0 all 0 r/w upper up-counter dacntl bit bit name initial value r/w description 7 to 2 uc8 to uc13 all 0 r/w lower up-counter 1 1 r reserved this bit is always read as 1 and cannot be modified. 0 regs 1 r/w register select dadra and dacr, and dadrb and dacnt, are located at the same addresses. the regs bit specifies which registers can be accessed. 0: dadra and dadrb can be accessed 1: dacr and dacnt can be accessed rev. 2.0, 08/02, page 230 of 788 10.3.2 pwm (d/a) data registers a and b (dadra, dadrb) dadra corresponds to pwm (d/a) channel a, and dadrb to pwm (d/a) channel b. since dadr consists of 16-bit data, dadr transfers data to the cpu via the temporary register (temp). for details, refer to section 10.4, bus master interface. dadra bit bit name initial value r/w description 15 14 13 12 11 10 9 8 7 6 5 4 3 2 da13 da12 da11 da10 da9 da8 da7 da6 da5 da4 da3 da2 da1 da0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w d/a data 13 to 0 these bits set a digital value to be converted to an analog value. in each base cycle, the dacnt value is continually compared with the dadr value to determine the duty cycle of the output waveform, and to decide whether to output a fine-adjustment pulse equal in width to the resolution. to enable this operation, this register must be set within a range that depends on the cfs bit. if the dadr value is outside this range, the pwm output is held constant. a channel can be operated with 12-bit precision by keeping the two lowest data bits (da1 and da0) cleared to 0. the two lowest data bits correspond to the two highest bits in dacnt. 1 cfs 1 r/w carrier frequency select 0: base cycle = resolution (t) 64 dadr range = h'0401 to h'fffd 1: base cycle = resolution (t) 256 dadr range = h'0103 to h'ffff 0 1 r reserved this bit is always read as 1 and cannot be modified. rev. 2.0, 08/02, page 231 of 788 dadrb bit bit name initial value r/w description 15 14 13 12 11 10 9 8 7 6 5 4 3 2 da13 da12 da11 da10 da9 da8 da7 da6 da5 da4 da3 da2 da1 da0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w d/a data 13 to 0 these bits set a digital value to be converted to an analog value. in each base cycle, the dacnt value is continually compared with the dadr value to determine the duty cycle of the output waveform, and to decide whether to output a fine-adjustment pulse equal in width to the resolution. to enable this operation, this register must be set within a range that depends on the cfs bit. if the dadr value is outside this range, the pwm output is held constant. a channel can be operated with 12-bit precision by keeping the two lowest data bits (da1 and da0) cleared to 0. the two lowest data bits correspond to the two highest bits in dacnt. 1 cfs 1 r/w carrier frequency select 0: base cycle = resolution (t) 64 dadr range = h'0401 to h'fffd 1: base cycle = resolution (t) 256 dadr range = h'0103 to h'ffff 0 regs 1 r/w register select dadra and dacr, and dadrb and dacnt, are located at the same addresses. the regs bit specifies which registers can be accessed. 0: dadra and dadrb can be accessed 1: dacr and dacnt can be accessed rev. 2.0, 08/02, page 232 of 788 10.3.3 pwm (d/a) control register (dacr) dacr selects test mode, enables the pwm outputs, and selects the output phase and operating speed. bit bit name initial value r/w description 7 test 0 r/w test mode selects test mode, which is used in testing this lsi. normally this bit should be cleared to 0. 0: pwm (d/a) in user state: normal operation 1: pwm (d/a) in test state: correct conversion results unobtainable 6 pwme 0 r/w pwm enable starts or stops the pwm d/a counter (dacnt). 0: dacnt operates as a 14-bit up-counter 1: dacnt halts at h'0003 5 4 1 1 r r reserved these bits are always read as 1 and cannot be modified. 3 oeb 0 r/w output enable b enables or disables output on pwm (d/a) channel b. 0: pwm (d/a) channel b output (at the pwx1 pin) is disabled 1: pwm (d/a) channel b output (at the pwx1 pin) is enabled rev. 2.0, 08/02, page 233 of 788 bit bit name initial value r/w description 2 oea 0 r/w output enable a enables or disables output on pwm (d/a) channel a. 0: pwm (d/a) channel a output (at the pwx0 pin) is disabled 1: pwm (d/a) channel a output (at the pwx0 pin) is enabled 1 os 0 r/w output select selects the phase of the pwm (d/a) output. 0: direct pwm (d/a) output 1: inverted pwm (d/a) output 0 cks 0 r/w clock select selects the pwm (d/a) resolution. if the system clock (?) frequency is 10 mhz, resolutions of 100 ns and 200 ns, can be selected. 0: operates at resolution (t) = system clock cycle time (t cyc ) 1: operates at resolution (t) = system clock cycle time (t cyc ) 2 10.4 bus master interface dacnt, dadra, and dadrb are 16-bit registers. the data bus linking the bus master and the on-chip peripheral modules, however, is only 8 bits wide. when the bus master accesses these registers, it therefore uses an 8-bit temporary register (temp). these registers are written to and read from as follows. write: when the upper byte is written to, the upper-byte write data is stored in temp. next, when the lower byte is written to, the lower-byte write data and temp value are combined, and the combined 16-bit value is written in the register. read: when the upper byte is read from, the upper-byte value is transferred to the cpu and the lower-byte value is transferred to temp. next, when the lower byte is read from, the lower-byte value in temp is transferred to the cpu. these registers should always be accessed 16 bits at a time with a mov instruction, and the upper byte should always be accessed before the lower byte. correct data will not be transferred if only the upper byte or only the lower byte is accessed. also note that a bit manipulation instruction cannot be used to access these registers. example 1: write to dacnt rev. 2.0, 08/02, page 234 of 788 mov.w r0, @dacnt ; write r0 contents to dacnt example 2: read dadra mov.w @dadra, r0 ; copy contents of dadra to r0 table 10.2 read and write access methods for 16-bit registers read write register name word byte word byte dadra and dadrb yes yes yes dacnt yes yes legend yes: permitted type of access. word access includes successive byte accesses to the upper byte (first) and lower byte (second). : this type of access may give incorrect results. 10.5 operation a pwm waveform like the one shown in figure 10.2 is output from the pwmx pin. the value in dadr corresponds to the total width (t l ) of the low (0) pulses output in one conversion cycle (256 pulses when cfs = 0, 64 pulses when cfs = 1). when os = 0, this waveform is directly output. when os = 1, the output waveform is inverted, and the dadr value corresponds to the total width (t h ) of the high (1) output pulses. figures 10.3 and 10.4 show the types of waveform output available. t f t l t: resolution t l = t ln (os = 0) (when cfs = 0, m = 256 when cfs = 1, m = 64) m n = 1 1 conversion cycle (t 2 14 (= 16384)) base cycle (t 64 or t 256) figure 10.2 pwm d/a operation rev. 2.0, 08/02, page 235 of 788 table 10.3 summarizes the relationships between the cks, cfs, and os bit settings and the resolution, base cycle, and conversion cycle. the pwm output remains fixed unless dadr contains at least a certain minimum value. table 10.3 settings and operation (examples when ? = 10 mhz) fixed dadr bits bit data cks resolution t (s) cfs base cycle (s) conversion cycle (s) t l (if os = 0) t h (if os = 1) precisi- on (bits) 3210 conversion cycle * (s) 14 1638.4 12 0 0 409.6 06.4 1. always low (or high) (dadr = h'0001 to h'03fd) 2. (data value) t (dadr = h'0401 to h'fffd) 10 0 0 0 0 102.4 14 1638.4 12 0 0 409.6 00.1 1 25.6 1638.4 1. always low (or high) (dadr = h'0003 to h'00ff) 2. (data value) t (dadr = h'0103 to h'ffff) 10 0 0 0 0 102.4 14 3276.8 12 0 0 819.2 0 12.8 1. always low (or high) (dadr = h'0001 to h'03fd) 2. (data value) t (dadr = h'0401 to h'fffd) 10 0 0 0 0 204.8 14 3276.8 12 0 0 819.2 10.2 1 51.2 3276.8 1. always low (or high) (dadr = h'0003 to h'00ff) 2. (data value) t (dadr = h'0103 to h'ffff) 10 0 0 0 0 204.8 note: * this column indicates the conversion cycle when specific dadr bits are fixed. rev. 2.0, 08/02, page 236 of 788 t f1 t f2 t f255 t f256 t l1 t l2 t l3 t l255 t l256 1 conversion cycle t f1 = t f2 = t f3 = = t f255 = t f256 = t 64 t l1 + t l2 + t l3 + + t l255 + t l256 = t l t f1 t f2 t f63 t f64 t l1 t l2 t l3 t l63 t l64 1 conversion cycle t f1 = t f2 = t f3 = = t f63 = t f64 = t 256 t l1 + t l2 + t l3 + + t l63 + t l64 = t l a. cfs = 0 [base cycle = resolution (t) 64] b. cfs = 1 [base cycle = resolution (t) 256] figure 10.3 output waveform (os = 0, dadr corresponds to t l ) rev. 2.0, 08/02, page 237 of 788 t f1 t f2 t f255 t f256 t h1 t h2 t h3 t h255 t h256 1 conversion cycle t f1 = t f2 = t f3 = = t f255 = t f256 = t 64 t h1 + t h2 + t h3 + + t h255 + t h256 = t h t f1 t f2 t f63 t f64 t h1 t h2 t h3 t h63 t h64 1 conversion cycle t f1 = t f2 = t f3 = = t f63 = t f64 = t 256 t h1 + t h2 + t h3 + + t h63 + t h64 = t h a. cfs = 0 [base cycle = resolution (t) 64] b. cfs = 1 [base cycle = resolution (t) 256] figure 10.4 output waveform (os = 1, dadr corresponds to t h ) an example of setting cfs to 1 (basic cycle = resolution (t) 256) and os to 1 (pwmx inverted output) is shown as an additional pulse. when cfs is set to 1, the duty ratio of the basic pulse is determined by the upper eight bits (da13 to da6) in dadr, and the position of the additional pulse is determined by the following six bits (da5 to da0) as shown in figure 10.5. table 10.4 shows the position of the additional pulse. basic pulse duty ratio da13 da12 da11 da10 da9 da8 da7 da6 da5 da4 da3 da2 da1 da0 cfs 11 additional pulse position figure 10.5 d/a data register configuration when cfs = 1 here, the case of dadr = h0207 (b0000 0010 0000 0111) is considered. figure 10.6 shows an output waveform. because cfs = 1 and the value of upper eight bits is b0000 0010, the duty ratio of the basic pulse is 2/256 (t) of high width. since the value of the following six bits is b0000 01, the additional pulse is output at the position of basic pulse no. 63 as shown in table 10.4. only 1/256 (t) of the additional pulse is added to the basic pulse. rev. 2.0, 08/02, page 238 of 788 one conversion cycle no.1 no.0 basic cycle no.63 basic cycle basic cycle basic pulse 2/256 (t) additional pulse 1/256 (t) additional pulse output position basic pulse high width: 2/256 (t) figure 10.6 output waveform when dadr = h0207 (os = 1) note that the case of cfs = 0 (basic cycle = resolution (t) 64) is similar other than the duty ratio of the basic pulse is determined by the upper six bits, and the position of the additional pulse is determined by the following eight bits. rev. 2.0, 08/02, page 239 of 788 table 10.4 position of pulse to be added to basic pulse (cfs = 1) lower 6 bits basic pulse no. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 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s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s rev. 2.0, 08/02, page 240 of 788 10.6 usage note 10.6.1 module stop mode setting pwmx operation can be enabled or disabled using the module stop control register. the initial setting is for pwmx operation to be halted. register access is enabled by canceling the module stop mode. for details, refer to section 26, power-down modes. rev. 2.0, 08/02, page 241 of 788 section 11 16-bit free-running timer (frt) this lsi has an on-chip 16-bit free-running timer (frt). the frt operates on the basis of the 16- bit free-running counter (frc), and outputs two independent waveforms, and measures the input pulse width and external clock periods. 11.1 features selection of four clock sources one of the three internal clocks (?/2, ?/8, or ?/32), or an external clock input can be selected (enabling use as an external event counter). two independent comparators two independent waveforms can be output. four independent input capture channels the rising or falling edge can be selected. buffer modes can be specified. counter clearing the free-running counters can be cleared on compare-match a. seven independent interrupts two compare-match interrupts, four input capture interrupts, and one overflow interrupt can be requested independently. special functions provided by automatic addition function the contents of ocrar and ocraf can be added to the contents of ocra automatically, enabling a periodic waveform to be generated without software intervention. the contents of icrd can be added automatically to the contents of ocrdm 2, enabling input capture operations in this interval to be restricted. tim8fr1a_010020020700 rev. 2.0, 08/02, page 242 of 788 figure 11.1 shows a block diagram of the frt. clock selector clock compare-match a ocra (h/l) comparator a internal data bus frc (h/l) comparator b ocrb (h/l) icra (h/l) icrb (h/l) icrc (h/l) icrd (h/l) tcsr ftci ftob ftia external clock internal clock ?/2 ?/8 ?/32 ftib ftic ftid ftoa compare-match b overflow clear input capture tier tcr tocr icia icib icic icid interrupt signal legend ocra, ocrb ocrar,ocraf ocrdm frc icra to d tcsr tier tcr tocr : output compare register a, b (16-bit) : output compare register ar, af (16-bit) : output compare register dm (16-bit) : free-running counter (16-bit) : input capture registers a to d (16-bit) : timer control/status register (8-bit) : timer interrupt enable register (8-bit) : timer control register (8-bit) : timer output compare control register (8-bit) ocia ocib fovi ocrar/f (h/l) ocrdm l comparator m compare-match m 1 2 control logic module data bus bus interface figure 11.1 block diagram of 16-bit free-running timer rev. 2.0, 08/02, page 243 of 788 11.2 input/output pins table 11.1 lists the frt input and output pins. table 11.1 pin configuration name abbreviation i/o function counter clock input pin ftci input frc counter clock input output compare a output pin ftoa output output compare a output output compare b output pin ftob output output compare b output input capture a input pin ftia input input capture a input input capture b input pin ftib input input capture b input input capture c input pin ftic input input capture c input input capture d input pin ftid input input capture d input 11.3 register descriptions the frt has the following registers. free-running counter (frc) output compare register a (ocra) output compare register b (ocrb) input capture register a (icra) input capture register b (icrb) input capture register c (icrc) input capture register d (icrd) output compare register ar (ocrar) output compare register af (ocraf) output compare register dm (ocrdm) timer interrupt enable register (tier) timer control/status register (tcsr) timer control register (tcr) timer output compare control register (tocr) note: ocra and ocrb share the same address. register selection is controlled by the ocrs bit in tocr. icra, icrb, and icrc share the same addresses with ocrar, ocraf, and ocrdm. register selection is controlled by the icrs bit in tocr. rev. 2.0, 08/02, page 244 of 788 11.3.1 free-running counter (frc) frc is a 16-bit readable/writable up-counter. the clock source is selected by bits cks1 and cks0 in tcr. frc can be cleared by compare-match a. when frc overflows from h'ffff to h'0000, the overflow flag bit (ovf) in tcsr is set to 1. frc should always be accessed in 16-bit units; cannot be accessed in 8-bit units. frc is initialized to h'0000. 11.3.2 output compare registers a and b (ocra, ocrb) the frt has two output compare registers, ocra and ocrb, each of which is a 16-bit readable/writable register whose contents are continually compared with the value in frc. when a match is detected (compare-match), the corresponding output compare flag (ocfa or ocfb) is set to 1 in tcsr. if the oea or oeb bit in tocr is set to 1, when the ocr and frc values match, the output level selected by the olvla or olvlb bit in tocr is output at the output compare output pin (ftoa or ftob). following a reset, the ftoa and ftob output levels are 0 until the first compare-match. ocr should always be accessed in 16-bit units; cannot be accessed in 8-bit units. ocr is initialized to h'ffff. 11.3.3 input capture registers a to d (icra to icrd) the frt has four input capture registers, icra to icrd, each of which is a 16-bit read-only register. when the rising or falling edge of the signal at an input capture input pin (ftia to ftid) is detected, the current frc value is transferred to the corresponding input capture register (icra to icrd). at the same time, the corresponding input capture flag (icfa to icfd) in tcsr is set to 1. the frc contents are transferred to icr regardless of the value of icf. the input capture edge is selected by the input edge select bits (iedga to iedgd) in tcr. icrc and icrd can be used as icra and icrb buffer registers, respectively, by means of buffer enable bits a and b (bufea and bufeb) in tcr. for example, if an input capture occurs when icrc is specified as the icra buffer register, the frc contents are transferred to icra, and then transferred to the buffer register icrc. to ensure input capture, the input capture pulse width should be at least 1.5 system clocks (?) for a single edge. when triggering is enabled on both edges, the input capture pulse width should be at least 2.5 system clocks (?). icra to icrd should always be accessed in 16-bit units; cannot be accessed in 8-bit units. icr is initialized to h'0000. rev. 2.0, 08/02, page 245 of 788 11.3.4 output compare registers ar and af (ocrar, ocraf) ocrar and ocraf are 16-bit readable/writable registers. when the ocrams bit in tocr is set to 1, the operation of ocra is changed to include the use of ocrar and ocraf. the contents of ocrar and ocraf are automatically added alternately to ocra, and the result is written to ocra. the write operation is performed on the occurrence of compare-match a. in the 1st compare-match a after setting the ocrams bit to 1, ocraf is added. the operation due to compare-match a varies according to whether the compare-match follows addition of ocrar or ocraf. the value of the olvla bit in tocr is ignored, and 1 is output on a compare-match a following addition of ocraf, while 0 is output on a compare-match a following addition of ocrar. when using the ocra automatic addition function, do not select internal clock ?/2 as the frc input clock together with a set value of h'0001 or less for ocrar (or ocraf). ocrar and ocraf should always be accessed in 16-bit units; cannot be accessed in 8-bit units. ocrar and ocraf are initialized to h'ffff. 11.3.5 output compare register dm (ocrdm) ocrdm is a 16-bit readable/writable register in which the upper 8 bits are fixed at h'00. when the icrdms bit in tocr is set to 1 and the contents of ocrdm are other than h'0000, the operation of icrd is changed to include the use of ocrdm. the point at which input capture d occurs is taken as the start of a mask interval. next, twice the contents of ocrdm is added to the contents of icrd, and the result is compared with the frc value. the point at which the values match is taken as the end of the mask interval. new input capture d events are disabled during the mask interval. a mask interval is not generated when the contents of ocrdm are h'0000 while the icrdms bit is set to 1. ocrdm should always be accessed in 16-bit units; cannot be accessed in 8-bit units. ocrdm is initialized to h'0000. rev. 2.0, 08/02, page 246 of 788 11.3.6 timer interrupt enable register (tier) tier enables and disables interrupt requests. bit bit name initial value r/w description 7 iciae 0 r/w input capture interrupt a enable selects whether to enable input capture interrupt a request (icia) when input capture flag a (icfa) in tcsr is set to 1. 0: icia requested by icfa is disabled 1: icia requested by icfa is enabled 6 icibe 0 r/w input capture interrupt b enable selects whether to enable input capture interrupt b request (icib) when input capture flag b (icfb) in tcsr is set to 1. 0: icib requested by icfb is disabled 1: icib requested by icfb is enabled 5 icice 0 r/w input capture interrupt c enable selects whether to enable input capture interrupt c request (icic) when input capture flag c (icfc) in tcsr is set to 1. 0: icic requested by icfc is disabled 1: icic requested by icfc is enabled 4 icide 0 r/w input capture interrupt d enable selects whether to enable input capture interrupt d request (icid) when input capture flag d (icfd) in tcsr is set to 1. 0: icid requested by icfd is disabled 1: icid requested by icfd is enabled 3 ociae 0 r/w output compare interrupt a enable selects whether to enable output compare interrupt a request (ocia) when output compare flag a (ocfa) in tcsr is set to 1. 0: ocia requested by ocfa is disabled 1: ocia requested by ocfa is enabled rev. 2.0, 08/02, page 247 of 788 bit bit name initial value r/w description 2 ocibe 0 r/w output compare interrupt b enable selects whether to enable output compare interrupt b request (ocib) when output compare flag b (ocfb) in tcsr is set to 1. 0: ocib requested by ocfb is disabled 1: ocib requested by ocfb is enabled 1 ovie 0 r/w timer overflow interrupt enable selects whether to enable a free-running timer overflow request interrupt (fovi) when the timer overflow flag (ovf) in tcsr is set to 1. 0: fovi requested by ovf is disabled 1: fovi requested by ovf is enabled 0 0 r reserved this bit is always read as 1 and cannot be modified. 11.3.7 timer control/status register (tcsr) tcsr is used for counter clear selection and control of interrupt request signals. bit bit name initial value r/w description 7 icfa 0 r/(w) * input capture flag a this status flag indicates that the frc value has been transferred to icra by means of an input capture signal. when bufea = 1, icfa indicates that the old icra value has been moved into icrc and the new frc value has been transferred to icra. only 0 can be written to this bit to clear the flag. [setting condition] when an input capture signal causes the frc value to be transferred to icra [clearing condition] read icfa when icfa = 1, then write 0 to icfa rev. 2.0, 08/02, page 248 of 788 bit bit name initial value r/w description 6 icfb 0 r/(w) * input capture flag b this status flag indicates that the frc value has been transferred to icrb by means of an input capture signal. when bufeb = 1, icfb indicates that the old icrb value has been moved into icrd and the new frc value has been transferred to icrb. only 0 can be written to this bit to clear the flag. [setting condition] when an input capture signal causes the frc value to be transferred to icrb [clearing condition] read icfb when icfb = 1, then write 0 to icfb 5 icfc 0 r/(w) * input capture flag c this status flag indicates that the frc value has been transferred to icrc by means of an input capture signal. when bufea = 1, on occurrence of an input capture signal specified by the iedgc bit at the ftic input pin, icfc is set but data is not transferred to icrc. in buffer operation, icfc can be used as an external interrupt signal by setting the icice bit to 1. only 0 can be written to this bit to clear the flag. [setting condition] when an input capture signal is received [clearing condition] read icfc when icfc = 1, then write 0 to icfc 4 icfd 0 r/(w) * input capture flag d this status flag indicates that the frc value has been transferred to icrd by means of an input capture signal. when bufeb = 1, on occurrence of an input capture signal specified by the iedgd bit at the ftid input pin, icfd is set but data is not transferred to icrd. in buffer operation, icfd can be used as an external interrupt signal by setting the icide bit to 1. only 0 can be written to this bit to clear the flag. [setting condition] when an input capture signal is received [clearing condition] read icfd when icfd = 1, then write 0 to icfd rev. 2.0, 08/02, page 249 of 788 bit bit name initial value r/w description 3 ocfa 0 r/(w) * output compare flag a this status flag indicates that the frc value matches the ocra value. only 0 can be written to this bit to clear the flag. [setting condition] when frc = ocra [clearing condition] read ocfa when ocfa = 1, then write 0 to ocfa 2 ocfb 0 r/(w) * output compare flag b this status flag indicates that the frc value matches the ocrb value. only 0 can be written to this bit to clear the flag. [setting condition] when frc = ocrb [clearing condition] read ocfb when ocfb = 1, then write 0 to ocfb 1ovf 0 r/(w) * timer overflow this status flag indicates that the frc has overflowed. only 0 can be written to this bit to clear the flag. [setting condition] when frc overflows (changes from h'ffff to h'0000) [clearing condition] read ovf when ovf = 1, then write 0 to ovf 0 cclra 0 r/w counter clear a this bit selects whether the frc is to be cleared at compare-match a (when the frc and ocra values match). 0: frc clearing is disabled 1: frc is cleared at compare-match a note: * only 0 can be written to clear the flag. rev. 2.0, 08/02, page 250 of 788 11.3.8 timer control register (tcr) tcr selects the rising or falling edge of the input capture signals, enables the input capture buffer mode, and selects the frc clock source. bit bit name initial value r/w description 7 iedga 0 r/w input edge select a selects the rising or falling edge of the input capture a signal (ftia). 0: capture on the falling edge of ftia 1: capture on the rising edge of ftia 6 iedgb 0 r/w input edge select b selects the rising or falling edge of the input capture b signal (ftib). 0: capture on the falling edge of ftib 1: capture on the rising edge of ftib 5 iedgc 0 r/w input edge select c selects the rising or falling edge of the input capture c signal (ftic). 0: capture on the falling edge of ftic 1: capture on the rising edge of ftic 4 iedgd 0 r/w input edge select d selects the rising or falling edge of the input capture d signal (ftid). 0: capture on the falling edge of ftid 1: capture on the rising edge of ftid 3 bufea 0 r/w buffer enable a selects whether icrc is to be used as a buffer register for icra. 0: icrc is not used as a buffer register for icra 1: icrc is used as a buffer register for icra 2 bufeb 0 r/w buffer enable b selects whether icrd is to be used as a buffer register for icrb. 0: icrd is not used as a buffer register for icrb 1: icrd is used as a buffer register for icrb rev. 2.0, 08/02, page 251 of 788 bit bit name initial value r/w description 1 0 cks1 cks0 0 0 r/w clock select 1, 0 select clock source for frc. 00: ?/2 internal clock source 01: ?/8 internal clock source 10: ?/32 internal clock source 11: external clock source (counting at ftci rising edge) 11.3.9 timer output compare control register (tocr) tocr enables output from the output compare pins, selects the output levels, switches access between output compare registers a and b, controls the icrd and ocra operating modes, and switches access to input capture registers a, b, and c. bit bit name initial value r/w description 7 icrdms 0 r/w input capture d mode select specifies whether icrd is used in the normal operating mode or in the operating mode using ocrdm. 0: the normal operating mode is specified for icrd 1: the operating mode using ocrdm is specified for icrd 6 ocrams 0 r/w output compare a mode select specifies whether ocra is used in the normal operating mode or in the operating mode using ocrar and ocraf. 0: the normal operating mode is specified for ocra 1: the operating mode using ocrar and ocraf is specified for ocra 5 icrs 0 r/w input capture register select the same addresses are shared by icra and ocrar, by icrb and ocraf, and by icrc and ocrdm. the icrs bit determines which registers are selected when the shared addresses are read from or written to. the operation of icra, icrb, and icrc is not affected. 0: icra, icrb, and icrc are selected 1: ocrar, ocraf, and ocrdm are selected rev. 2.0, 08/02, page 252 of 788 bit bit name initial value r/w description 4 ocrs 0 r/w output compare register select ocra and ocrb share the same address. when this address is accessed, the ocrs bit selects which register is accessed. the operation of ocra or ocrb is not affected. 0: ocra is selected 1: ocrb is selected 3 oea 0 r/w output enable a enables or disables output of the output compare a output pin (ftoa). 0: output compare a output is disabled 1: output compare a output is enabled 2 oeb 0 r/w output enable b enables or disables output of the output compare b output pin (ftob). 0: output compare b output is disabled 1: output compare b output is enabled 1 olvla 0 r/w output level a selects the level to be output at the output compare a output pin (ftoa) in response to compare-match a (signal indicating a match between the frc and ocra values). when the ocrams bit is 1, this bit is ignored. 0: 0 is output at compare-match a 1: 1 is output at compare-match a 0 olvlb 0 r/w output level b selects the level to be output at the output compare b output pin (ftob) in response to compare-match b (signal indicating a match between the frc and ocrb values). 0: 0 is output at compare-match b 1: 1 is output at compare-match b rev. 2.0, 08/02, page 253 of 788 11.4 operation 11.4.1 pulse output figure 11.2 shows an example of 50%-duty pulses output with an arbitrary phase difference. when a compare match occurs while the cclra bit in tcsr is set to 1, the olvla and olvlb bits are inverted by software. h'ffff ocra ocrb h'0000 ftoa ftob counter clear frc figure 11.2 example of pulse output 11.5 operation timing 11.5.1 frc increment timing figure 11.3 shows the frc increment timing with an internal clock source. figure 11.4 shows the increment timing with an external clock source. the pulse width of the external clock signal must be at least 1.5 system clocks (?). the counter will not increment correctly if the pulse width is shorter than 1.5 system clocks (?). ? internal clock frc input clock frc n C 1 n + 1 n figure 11.3 increment timing with internal clock source rev. 2.0, 08/02, page 254 of 788 ? external clock input pin frc input clock frc n + 1 n figure 11.4 increment timing with external clock source 11.5.2 output compare output timing a compare-match signal occurs at the last state when the frc and ocr values match (at the timing when the frc updates the counter value). when a compare-match signal occurs, the level selected by the olvl bit in tocr is output at the output compare pin (ftoa or ftob). figure 11.5 shows the timing of this operation for compare-match a. ? frc ocra nn n + 1 n + 1 nn compare-match a signal olvla output compare a output pin ftoa clear * note : * indicates instruction execution by software. figure 11.5 timing of output compare a output rev. 2.0, 08/02, page 255 of 788 11.5.3 frc clear timing frc can be cleared when compare-match a occurs. figure 11.6 shows the timing of this operation. ? frc n h'0000 compare-match a signal figure 11.6 clearing of frc by compare-match a signal 11.5.4 input capture input timing the rising or falling edge can be selected for the input capture input timing by the iedga to iedgd bits in tcr. figure 11.7 shows the usual input capture timing when the rising edge is selected. ? input capture input pin input capture signal figure 11.7 input capture input signal timing (usual case) rev. 2.0, 08/02, page 256 of 788 if icra to icrad are read when the corresponding input capture signal arrives, the internal input capture signal is delayed by one system clock (?). figure 11.8 shows the timing for this case. t 1 t 2 read cycle of icra to icrd ? input capture input pin input capture signal figure 11.8 input capture input signal timing (when icra to icrd are read) 11.5.5 buffered input capture input timing icrc and icrd can operate as buffers for icra and icrb, respectively. figure 11.9 shows how input capture operates when icrc is used as icra's buffer register (bufea = 1) and iedga and iedgc are set to different values (iedga = 0 and iedgc = 1, or iedga = 1 and iedgc = 0), so that input capture is performed on both the rising and falling edges of ftia. input capture signal ? ftia frc icra icrc n n + 1 n + 1 n mn m m n m n n figure 11.9 buffered input capture timing even when icrc or icrd is used as a buffer register, its input capture flag is set by the selected transition of its input capture signal. for example, if icrc is used to buffer icra, when the edge transition selected by the iedgc bit occurs on the ftic input capture line, icfc will be set, and if the icice bit is set at this time, an interrupt will be requested. the frc value will not be transferred to icrc, however. in buffered input capture, if either set of two registers to which data rev. 2.0, 08/02, page 257 of 788 will be transferred (icra and icrc, or icrb and icrd) is being read when the input capture input signal arrives, input capture is delayed by one system clock (?). figure 11.10 shows the timing when bufea = 1. input capture signal ftia ? t 1 t 2 cpu read cycle of icra or icrc figure 11.10 buffered input capture timing (bufea = 1) 11.5.6 timing of input capture flag (icf) setting the input capture flag, icfa, icfb, icfc, or icfd, is set to 1 by the input capture signal. the frc value is simultaneously transferred to the corresponding input capture register (icra, icrb, icrc, or icrd). figure 11.11 shows the timing of setting the icfa to icfd flag. input capture signal ? icfa to icfd icra to icrd frc n n figure 11.11 timing of input capture flag (icfa, icfb, icfc, or icfd) setting rev. 2.0, 08/02, page 258 of 788 11.5.7 timing of output compare flag (ocf) setting the output compare flag, ocfa or ocfb, is set to 1 by a compare-match signal generated when the frc value matches the ocra or ocrb value. this compare-match signal is generated at the last state in which the two values match, just before frc increments to a new value. when the frc and ocra or ocrb value match, the compare-match signal is not generated until the next cycle of the clock source. figure 11.12 shows the timing of setting the ocfa or ocfb flag. compare-match signal ocfa, ocfb ocra, ocrb n frc n n + 1 ? figure 11.12 timing of output compare flag (ocfa or ocfb) setting 11.5.8 timing of frc overflow flag setting the frc overflow flag (ovf) is set to 1 when frc overflows (changes from h'ffff to h'0000). figure 11.13 shows the timing of setting the ovf flag. overflow signal frc h'ffff h'0000 ovf ? figure 11.13 timing of overflow flag (ovf) setting rev. 2.0, 08/02, page 259 of 788 11.5.9 automatic addition timing when the ocrams bit in tocr is set to 1, the contents of ocrar and ocraf are automatically added to ocra alternately, and when an ocra compare-match occurs a write to ocra is performed. figure 11.14 shows the ocra write timing. compare-match signal ocrar, ocraf a ocra n n + a frc n n +1 ? figure 11.14 ocra automatic addition timing 11.5.10 mask signal generation timing when the icrdms bit in tocr is set to 1 and the contents of ocrdm are other than h'0000, a signal that masks the icrd input capture signal is generated. the mask signal is set by the input capture signal. the mask signal is cleared by the sum of the icrd contents and twice the ocrdm contents, and an frc compare-match. figure 11.15 shows the timing of setting the mask signal. figure 11.16 shows the timing of clearing the mask signal. input capture signal input capture mask signal ? figure 11.15 timing of input capture mask signal setting rev. 2.0, 08/02, page 260 of 788 compare-match signal input capture mask signal icrd + ocrdm 2 n frc n n + 1 ? figure 11.16 timing of input capture mask signal clearing 11.6 interrupt sources the free-running timer can request seven interrupts: icia to icid, ocia, ocib, and fovi. each interrupt can be enabled or disabled by an enable bit in tier. independent signals are sent to the interrupt controller for each interrupt. table 11.2 lists the sources and priorities of these interrupts. the icia, icib, ocia, and ocib interrupts can be used as the on-chip dtc activation sources. table 11.2 frt interrupt sources interrupt interrupt source interrupt flag dtc activation priority icia input capture of icra icfa enabled high icib input capture of icrb icfb enabled icic input capture of icrc icfc disabled icid input capture of icrd icfd disabled ocia compare match of ocra ocfa enabled ocib compare match of ocrb ocfb enabled fovi overflow of frc ovf disabled low rev. 2.0, 08/02, page 261 of 788 11.7 usage notes 11.7.1 conflict between frc write and clear if an internal counter clear signal is generated during the state after an frc write cycle, the clear signal takes priority and the write is not performed. figure 11.17 shows the timing for this type of conflict. ? address frc address internal write signal counter clear signal frc n h'0000 t 1 t 2 write cycle of frc figure 11.17 frc write-clear conflict rev. 2.0, 08/02, page 262 of 788 11.7.2 conflict between frc write and increment if an frc increment pulse is generated during the state after an frc write cycle, the write takes priority and frc is not incremented. figure 11.18 shows the timing for this type of conflict. ? address frc address internal write signal frc input clock write data frc n m t 1 t 2 write cycle of frc figure 11.18 frc write-increment conflict 11.7.3 conflict between ocr write and compare-match if a compare-match occurs during the state after an ocra or ocrb write cycle, the write takes priority and the compare-match signal is disabled. figure 11.19 shows the timing for this type of conflict. if automatic addition of ocrar and ocraf to ocra is selected, and a compare-match occurs in the cycle following the ocra, ocrar, and ocraf write cycle, the ocra, ocrar and ocraf write takes priority and the compare-match signal is disabled. consequently, the result of the automatic addition is not written to ocra. figure 11.20 shows the timing for this type of conflict. rev. 2.0, 08/02, page 263 of 788 ? address ocr address internal write signal compare-match signal frc write data disabled ocr n m n n + 1 t 1 t 2 write cycle of ocr figure 11.19 conflict between ocr write and compare-match (when automatic addition function is not used) rev. 2.0, 08/02, page 264 of 788 ? address ocrar (ocraf) address internal write signal compare-match signal frc automatic addition is not performed because compare-match signals are disabled. disabled ocra n n n+1 ocrar (ocraf) old data new data t 1 t 2 write cycle of ocrar/ocraf figure 11.20 conflict between ocrar/ocraf write and compare-match (when automatic addition function is used) 11.7.4 switching of internal clock and frc operation when the internal clock is changed, the changeover may cause frc to increment. this depends on the time at which the clock is switched (bits cks1 and cks0 are rewritten), as shown in table 11.3. when an internal clock is used, the frc clock is generated on detection of the falling edge of the internal clock scaled from the system clock (?). if the clock is changed when the old source is high and the new source is low, as in case no. 3 in table 11.3, the changeover is regarded as a falling edge that triggers the frc clock, and frc is incremented. switching between an internal clock and external clock can also cause frc to increment. rev. 2.0, 08/02, page 265 of 788 table 11.3 switching of internal clock and frc operation no. timing of switchover by means of cks1 and cks0 bits frc operation 1 switching from low to low clock before switchover clock after switchover frc clock frc cks bit rewrite n n + 1 2 switching from low to high clock before switchover clock after switchover frc clock frc n n + 1 n + 2 cks bit rewrite rev. 2.0, 08/02, page 266 of 788 no. timing of switchover by means of cks1 and cks0 bits frc operation 3 switching from high to low clock before switchover clock after switchover frc clock frc cks bit rewrite n n + 2 n + 1 * 4 switching from high to high clock before switchover clock after switchover frc clock frc n n + 1 cks bit rewrite n + 2 note: * generated on the assumption that the switchover is a falling edge; frc is incremented. 11.7.5 module stop mode setting frt operation can be enabled or disabled using the module stop control register. the initial setting is for frt operation to be halted. register access is enabled by canceling the module stop mode. for details, refer to section 26, power-down modes. rev. 2.0, 08/02, page 267 of 788 section 12 8-bit timer (tmr) this lsi has an on-chip 8-bit timer module (tmr_0 and tmr_1) with two channels operating on the basis of an 8-bit counter. the 8-bit timer module can count external events, and can also be used as a multifunction timer in a variety of applications, such as generation of counter reset, interrupt requests, and pulse output with an arbitrary duty cycle using a compare-match signal with two registers. this lsi also has a similar on-chip 8-bit timer module (tmr_y and tmr_x) with two channels, which can be used through connection to the timer connection. 12.1 features selection of clock sources ? tmr_0, tmr_1: the counter input clock can be selected from six internal clocks and an external clock ? tmr_y, tmr_x: the counter input clock can be selected from three internal clocks and an external clock selection of three ways to clear the counters ? the counters can be cleared on compare-match a or compare-match b, or by an external reset signal. timer output controlled by two compare-match signals ? the timer output signal in each channel is controlled by two independent compare-match signals, enabling the timer to be used for various applications, such as the generation of pulse output or pwm output with an arbitrary duty cycle. (the tmr_y does not have a timer output pin.) cascading of tmr_0 and tmr_1 ? (tmr_y and tmr_x cannot be cascaded.) operation as a 16-bit timer can be performed using tmr_0 as the upper half and tmr_1 as the lower half (16-bit count mode). tmr_1 can be used to count tmr_0 compare-match occurrences (compare-match count mode). multiple interrupt sources for each channel ? tmr_0, tmr_1, and tmr_y: three types of interrupts: compare-match a, compare- match b, and overflow ? tmr_x: input capture timh261a_010020020700 rev. 2.0, 08/02, page 268 of 788 figures 12.1 and 12.2 show block diagrams of the 8-bit timer module. tmr_x and tmr_y have a similar configuration, but cannot be cascaded. tmr_x also has an input capture function. for details, see section 13, timer connection. external clock sources internal clock sources tmr_0 ?/2, ?/8 ?/32, ?/64 ?/256, ?/1024 clock 1 clock 0 compare-match a1 compare-match a0 clear 1 interrupt signals cmia0 cmib0 ovi0 cmia1 cmib1 ovi1 tmo0 tmri0 internal bus tcora_0 comparator a_0 comparator b_0 tcorb_0 tcsr_0 tcr_0 tcora_1 comparator a_1 tcnt_1 comparator b_1 tcorb_1 tcsr_1 tcr_1 tmci0 tmci1 tcnt_0 overflow 1 overflow 0 compare-match b1 compare-match b0 tmo1 tmri1 clock select control logic clear 0 tmr_1 ?/2, ?/8 ?/64, ?/128 ?/1024, ?/2048 legend tcora_0 tcorb_0 tcnt_0 tcsr_0 tcr_0 : time constant register a_0 : time constant register b_0 : timer counter_0 : timer control/status register_0 : timer control register_0 tcora_1 tcorb_1 tcnt_1 tcsr_1 tcr_1 : time constant register a_1 : time constant register b_1 : timer counter_1 : timer control/status register_1 : timer control register_1 figure 12.1 block diagram of 8-bit timers (tmr_0 and tmr_1) rev. 2.0, 08/02, page 269 of 788 external clock sources internal clock sources tmr_x ? ?/2 ?/4 clock x clock y compare-match a x compare-match a y clear x cmiay cmiby oviy icix tmriy ivg signal tcora_y comparator a_y comparator b_y tcorb_y tcsr_y tcr_y tcora_x comparator a_x tcnt_x comparator b_x comparator c tcorb_x tcorc ticrr ticrf ticr tcsr_x tcr_x tmciy tmcix tisr tcnt_y overflow x overflow y compare- match b x compare-match b y compare-match c input capture tmox tmrix clock select internal bus control logic legend tcora_x: time constant register a_x tcorb_x: time constant register b_x tcnt_x: timer counter_x tcsr_x: timer control/status register_x tcr_x: timer control register_x ticr: input capture register tcorc: time constant register c ticrr: input capture register r ticrf: input capture register f tcora_y: time constant register a_y tcorb_y: time constant register b_y tcnt_y: timer counter_y tcsr_y: timer control/status register_y tcr_y: timer control register_y tisr: timer input select register clear y tmr_y ?/4 ?/256 ?/2048 interrupt signals + figure 12.2 block diagram of 8-bit timers (tmr_y and tmr_x) rev. 2.0, 08/02, page 270 of 788 12.2 input/output pins table 12.1 summarizes the input and output pins of the tmr. table 12.1 pin configuration channel name symbol i/o function timer output tmo0 output output controlled by compare-match timer clock input tmci0 input external clock input for the counter tmr_0 timer reset input tmri0 input external reset input for the counter timer output tmo1 output output controlled by compare-match timer clock input tmci1 input external clock input for the counter tmr_1 timer reset input tmri1 input external reset input for the counter tmr_y timer clock/reset input vsynci/tmiy (tmciy/tmriy) input external clock input/external reset input for the counter timer output tmox output output controlled by compare-match tmr_x timer clock/reset input hfbacki/tmix (tmcix/tmrix) input external clock input/external reset input for the counter 12.3 register descriptions the tmr has the following registers. for details on the serial timer control register, refer to section 3.2.3, serial timer control register (stcr). for details on timer connection register s, refer to section 13.3.3, timer connection register s (tconrs). timer counter (tcnt) time constant register a (tcora) time constant register b (tcorb) timer control register (tcr) timer control/status register (tcsr) timer input select register (tisr)* 1 time constant register c (tcorc)* 2 input capture register r (ticrr)* 2 input capture register f (ticrf)* 2 notes: 1. tisr is only for the tmr_y. 2. tcorc, ticrr, and ticrf are only for the tmr_x. rev. 2.0, 08/02, page 271 of 788 12.3.1 timer counter (tcnt) each tcnt is an 8-bit readable/writable up-counter. tcnt_0 and tcnt_1 comprise a single 16- bit register, so they can be accessed together by word access. the clock source is selected by the cks2 to cks0 bits in tcr. tcnt can be cleared by an external reset input signal, compare- match a signal or compare-match b signal. the method of clearing can be selected by the cclr1 and cclr0 bits in tcr. when tcnt overflows (changes from h'ff to h'00), the ovf bit in tcsr is set to 1. tcnt is initialized to h'00. 12.3.2 time constant register a (tcora) tcora is an 8-bit readable/writable register. tcora_0 and tcora_1 comprise a single 16-bit register, so they can be accessed together by word access. tcora is continually compared with the value in tcnt. when a match is detected, the corresponding compare-match flag a (cmfa) in tcsr is set to 1. note however that comparison is disabled during the t2 state of a tcora write cycle. the timer output from the tmo pin can be freely controlled by these compare-match a signals and the settings of output select bits os1 and os0 in tcsr. tcora is initialized to h'ff. 12.3.3 time constant register b (tcorb) tcorb is an 8-bit readable/writable register. tcorb_0 and tcorb_1 comprise a single 16-bit register, so they can be accessed together by word access. tcorb is continually compared with the value in tcnt. when a match is detected, the corresponding compare-match flag b (cmfb) in tcsr is set to 1. note however that comparison is disabled during the t2 state of a tcorb write cycle. the timer output from the tmo pin can be freely controlled by these compare-match b signals and the settings of output select bits os3 and os2 in tcsr. tcorb is initialized to h'ff. rev. 2.0, 08/02, page 272 of 788 12.3.4 timer control register (tcr) tcr selects the tcnt clock source and the condition by which tcnt is cleared, and enables/disables interrupt requests. bit bit name initial value r/w description 7 cmieb 0 r/w compare-match interrupt enable b selects whether the cmfb interrupt request (cmib) is enabled or disabled when the cmfb flag in tcsr is set to 1. note that a cmib interrupt is not generated by tmr_x, regardless of the cmieb value. 0: cmfb interrupt request (cmib) is disabled 1: cmfb interrupt request (cmib) is enabled 6 cmiea 0 r/w compare-match interrupt enable a selects whether the cmfa interrupt request (cmia) is enabled or disabled when the cmfa flag in tcsr is set to 1. note that a cmia interrupt is not generated by tmr_x, regardless of the cmiea value. 0: cmfa interrupt request (cmia) is disabled 1: cmfa interrupt request (cmia) is enabled 5 ovie 0 r/w timer overflow interrupt enable selects whether the ovf interrupt request (ovi) is enabled or disabled when the ovf flag in tcsr is set to 1. note that an ovi interrupt is not generated by tmr_x, regardless of the ovie value. 0: ovf interrupt request (ovi) is disabled 1: ovf interrupt request (ovi) is enabled rev. 2.0, 08/02, page 273 of 788 bit bit name initial value r/w description 4 3 cclr1 cclr0 0 0 r/w r/w counter clear 1, 0 these bits select the method by which the timer counter is cleared. 00: clearing is disabled 01: cleared on compare-match a 10: cleared on compare-match b 11: cleared on rising edge of external reset input 2 1 0 cks2 cks1 cks0 0 0 0 r/w r/w r/w clock select 2 to 0 these bits select the clock input to tcnt and count condition, together with the icks1 and icks0 bits in stcr. for details, see table 12.2. table 12.2 clock input to tcnt and count condition tcr stcr channel cks2 cks1 cks0 icks1 icks0 description 0 0 0 disables clock input 0 0 1 0 increments at falling edge of internal clock ?/8 0 0 1 1 increments at falling edge of internal clock ?/2 0 1 0 0 increments at falling edge of internal clock ?/64 0 1 0 1 increments at falling edge of internal clock ?/32 0 1 1 0 increments at falling edge of internal clock ?/1024 0 1 1 1 increments at falling edge of internal clock ?/256 tmr_0 1 0 0 increments at overflow signal from tcnt_1 * rev. 2.0, 08/02, page 274 of 788 tcr stcr channel cks2 cks1 cks0 icks1 icks0 description 0 0 0 disables clock input 0 0 1 0 increments at falling edge of internal clock ?/8 0 0 1 1 increments at falling edge of internal clock ?/2 0 1 0 0 increments at falling edge of internal clock ?/64 0 1 0 1 increments at falling edge of internal clock ?/128 0 1 1 0 increments at falling edge of internal clock ?/1024 0 1 1 1 increments at falling edge of internal clock ?/2048 tmr_1 1 0 0 increments at compare-match a from tcnt_0 * 0 0 0 disables clock input 001 increments at falling edge of internal clock ?/4 0 1 0 increments at falling edge of internal clock ?/256 011 increments at falling edge of internal clock ?/2048 tmr_y 1 0 0 disables clock input 0 0 0 disables clock input 0 0 1 increments at falling edge of internal clock ? 0 1 0 increments at falling edge of internal clock ?/2 0 1 1 increments at falling edge of internal clock ?/4 tmr_x 1 0 0 disables clock input 1 0 1 increments at rising edge of external clock 110 increments at falling edge of external clock common 1 1 1 increments at both rising and falling edges of external clock. note: * if the tmr_0 clock input is set as the tcnt_1 overflow signal and the tmr_1 clock input is set as the tcnt_0 compare-match signal simultaneously, a count-up clock cannot be generated. rev. 2.0, 08/02, page 275 of 788 12.3.5 timer control/status register (tcsr) tcsr indicates the status flags and controls compare-match output. tcsr_0 bit bit name initial value r/w description 7 cmfb 0 r/(w) * compare-match flag b [setting condition] when the values of tcnt_0 and tcorb_0 match [clearing conditions] read cmfb when cmfb = 1, then write 0 in cmfb when the dtc is activated by a cmib interrupt 6 cmfa 0 r/(w) * compare-match flag a [setting condition] when the values of tcnt_0 and tcora_0 match [clearing conditions] read cmfa when cmfa = 1, then write 0 in cmfa when the dtc is activated by a cmia interrupt 5ovf0 r/(w) * timer overflow flag [setting condition] when tcnt_0 overflows from h'ff to h'00 [clearing condition] read ovf when ovf = 1, then write 0 in ovf 4 adte 0 r/w a/d trigger enable enables or disables a/d converter start requests by compare-match a. 0: a/d converter start requests by compare-match a are disabled 1: a/d converter start requests by compare-match a are enabled rev. 2.0, 08/02, page 276 of 788 bit bit name initial value r/w description 3 2 os3 os2 0 0 r/w r/w output select 3, 2 these bits specify how the tmo0 pin output level is to be changed by compare-match b of tcorb_0 and tcnt_0. 00: no change 01: 0 is output 10: 1 is output 11: output is inverted (toggle output) 1 0 os1 os0 0 0 r/w r/w output select 1, 0 these bits specify how the tmo0 pin output level is to be changed by compare-match a of tcora_0 and tcnt_0. 00: no change 01: 0 is output 10: 1 is output 11: output is inverted (toggle output) note: * only 0 can be written, for flag clearing. rev. 2.0, 08/02, page 277 of 788 tcsr_1 bit bit name initial value r/w description 7 cmfb 0 r/(w) * compare-match flag b [setting condition] when the values of tcnt_1 and tcorb_1 match [clearing conditions] read cmfb when cmfb = 1, then write 0 in cmfb when the dtc is activated by a cmib interrupt 6 cmfa 0 r/(w) * compare-match flag a [setting condition] when the values of tcnt_1 and tcora_1 match [clearing conditions read cmfa when cmfa = 1, then write 0 in cmfa when the dtc is activated by a cmia interrupt 5ovf0 r/(w) * timer overflow flag [setting condition] when tcnt_1 overflows from h'ff to h'00 [clearing condition] read ovf when ovf = 1, then write 0 in ovf 4 1 rreserved this bit is always read as 1 and cannot be modified. 3 2 os3 os2 0 0 r/w r/w output select 3, 2 these bits specify how the tmo1 pin output level is to be changed by compare-match b of tcorb_1 and tcnt_1. 00: no change 01: 0 is output 10: 1 is output 11: output is inverted (toggle output) rev. 2.0, 08/02, page 278 of 788 bit bit name initial value r/w description 1 0 os1 os0 0 0 r/w r/w output select 1, 0 these bits specify how the tmo1 pin output level is to be changed by compare-match a of tcora_1 and tcnt_1. 00: no change 01: 0 is output 10: 1 is output 11: output is inverted (toggle output) note: * only 0 can be written, for flag clearing. tcsr_y bit bit name initial value r/w description 7 cmfb 0 r/(w) * 1 compare-match flag b [setting condition] when the values of tcnt_y and tcorb_y match [clearing conditions] read cmfb when cmfb = 1, then write 0 in cmfb when the dtc is activated by a cmib interrupt 6 cmfa 0 r/(w) * 1 compare-match flag a [setting condition] when the values of tcnt_y and tcora_y match [clearing conditions] read cmfa when cmfa = 1, then write 0 in cmfa when the dtc is activated by a cmia interrupt 5ovf0 r/(w) * 1 timer overflow flag [setting condition] when tcnt_y overflows from h'ff to h'00 [clearing condition] read ovf when ovf = 1, then write 0 in ovf 4 icie 0 r/w input capture interrupt enable enables or disables the icf interrupt request (icix) when the icf bit in tcsr_x is set to 1. 0: icf interrupt request (icix) is disabled 1: icf interrupt request (icix) is enabled rev. 2.0, 08/02, page 279 of 788 bit bit name initial value r/w description 3 2 os3 os2 0 0 r/w r/w output select 3, 2 these bits specify how the tmoy pin * 2 output level is to be changed by compare-match b of tcorb_y and tcnt_y. 00: no change 01: 0 is output 10: 1 is output 11: output is inverted (toggle output) 1 0 os1 os0 0 0 r/w r/w output select 1, 0 these bits specify how the tmoy pin * 2 output level is to be changed by compare-match a of tcora_y and tcnt_y. 00: no change 01: 0 is output 10: 1 is output 11: output is inverted (toggle output) notes: 1. only 0 can be written, for flag clearing. 2. this product does not have a tmoy external output pin. rev. 2.0, 08/02, page 280 of 788 tcsr_x bit bit name initial value r/w description 7 cmfb 0 r/(w) * compare-match flag b [setting condition] when the values of tcnt_x and tcorb_x match [clearing conditions] read cmfb when cmfb = 1, then write 0 in cmfb when the dtc is activated by a cmib interrupt 6 cmfa 0 r/(w) * compare-match flag a [setting condition] when the values of tcnt_x and tcora_x match [clearing conditions] read cmfa when cmfa = 1, then write 0 in cmfa when the dtc is activated by a cmia interrupt 5ovf0 r/(w) * timer overflow flag [setting condition] when tcnt_x overflows from h'ff to h'00 [clearing condition] read ovf when ovf = 1, then write 0 in ovf 4icf 0 r/(w) * input capture flag [setting condition] when a rising edge and falling edge is detected in the external reset signal in that order, after the icst bit in tconri of the timer connection is set to 1 [clearing condition] read icf when icf = 1, then write 0 in icf 3 2 os3 os2 0 0 r/w r/w output select 3, 2 these bits specify how the tmox pin output level is to be changed by compare-match b of tcorb_x and tcnt_x. 00: no change 01: 0 is output 10: 1 is output 11: output is inverted (toggle output) rev. 2.0, 08/02, page 281 of 788 bit bit name initial value r/w description 1 0 os1 os0 0 0 r/w r/w output select 1, 0 these bits specify how the tmox pin output level is to be changed by compare-match a of tcora_x and tcnt_x. 00: no change 01: 0 is output 10: 1 is output 11: output is inverted (toggle output) note: * only 0 can be written, for flag clearing. 12.3.6 input capture register (ticr) ticr is an 8-bit register. the contents of tcnt are transferred to ticr at the rising edge of the external reset input. ticr cannot be directly accessed by the cpu. the ticr function is used for the timer connection. for details, refer to section 13, timer connection. 12.3.7 time constant register (tcorc) tcorc is an 8-bit readable/writable register. the sum of contents of tcorc and ticr is always compared with tcnt. when a match is detected, a compare-match c signal is generated. however, comparison at the t2 state in the write cycle to tcorc and at the input capture cycle of ticr is disabled. tcorc is initialized to h'ff. the tcorc function is used for the timer connection. for details, refer to section 13, timer connection. 12.3.8 input capture registers r and f (ticrr, ticrf) ticrr and ticrf are 8-bit read-only registers. the contents of tcnt are transferred at the rising edge and falling edge of the external reset input in that order, when the icst bit in tconri of the timer connection is set to 1. the icst bit is cleared to 0 when one capture operation ends. ticrr and ticrf are initialized to h'00. the ticrr and ticrf functions are used for timer connection. for details, refer to section 13, timer connection. rev. 2.0, 08/02, page 282 of 788 12.3.9 timer input select register (tisr) tisr selects a signal source of external clock/reset input for the counter. bit bit name initial value r/w description 7 to 1 all 1 r/(w) reserved the initial values should not be modified. 0 is 0 r/w input select selects an internal synchronization signal (ivg signal) or timer clock/reset input pin vsynci/tmiy (tmciy/tmriy) as the signal source of external clock/reset input for the tmr_y counter. 0: ivg signal is selected 1: vsynci/tmiy (tmciy/tmriy) is selected 12.4 operation 12.4.1 pulse output figure 12.3 shows an example for outputting an arbitrary duty pulse. 1. clear the cclr1 bit in tcr to 0 so that tcnt is cleared according to the compare match of tcora, and then set the cclr0 bit to 1. 2. set the os3 to os0 bits in tcsr to b'0110 so that 1 is output according to the compare match of tcora and 0 is output according to the compare match of tcorb. according to the above settings, the waveforms with the tcora cycle and tcorb pulse width can be output without the intervention of software. tcnt h'ff counter clear tcora tcorb h'00 tmo figure 12.3 pulse output example rev. 2.0, 08/02, page 283 of 788 12.5 operation timing 12.5.1 tcnt count timing figure 12.4 shows the tcnt count timing with an internal clock source. figure 12.5 shows the tcnt count timing with an external clock source. the pulse width of the external clock signal must be at least 1.5 system clocks (?) for a single edge and at least 2.5 system clocks (?) for both edges. the counter will not increment correctly if the pulse width is less than these values. ? internal clock tcnt input clock tcnt n C 1 n n + 1 figure 12.4 count timing for internal clock input ? external clock input pin tcnt input clock tcnt n C 1 n n + 1 figure 12.5 count timing for external clock input (both edges) rev. 2.0, 08/02, page 284 of 788 12.5.2 timing of cmfa and cmfb setting at compare-match the cmfa and cmfb flags in tcsr are set to 1 by a compare-match signal generated when the tcnt and tcor values match. the compare-match signal is generated at the last state in which the match is true, just when the timer counter is updated. therefore, when tcnt and tcor match, the compare-match signal is not generated until the next tcnt input clock. figure 12.6 shows the timing of cmf flag setting. ? tcnt n n + 1 tcor n compare-match signal cmf figure 12.6 timing of cmf setting at compare-match 12.5.3 timing of timer output at compare-match when a compare-match signal occurs, the timer output changes as specified by the os3 to os0 bits in tcsr. figure 12.7 shows the timing of timer output when the output is set to toggle by a compare-match a signal. ? compare-match a signal timer output pin figure 12.7 timing of toggled timer output by compare-match a signal rev. 2.0, 08/02, page 285 of 788 12.5.4 timing of counter clear at compare-match tcnt is cleared when compare-match a or compare-match b occurs, depending on the setting of the cclr1 and cclr0 bits in tcr. figure 12.8 shows the timing of clearing the counter by a compare-match. ? n h'00 compare-match signal tcnt figure 12.8 timing of counter clear by compare-match 12.5.5 tcnt external reset timing tcnt is cleared at the rising edge of an external reset input, depending on the settings of the cclr1 and cclr0 bits in tcr. the width of the clearing pulse must be at least 1.5 states. figure 12.9 shows the timing of clearing the counter by an external reset input. ? clear signal external reset input pin tcnt n h'00 n C 1 figure 12.9 timing of counter clear by external reset input rev. 2.0, 08/02, page 286 of 788 12.5.6 timing of overflow flag (ovf) setting the ovf bit in tcsr is set to 1 when the tcnt overflows (changes from h'ff to h'00). figure 12.10 shows the timing of ovf flag setting. ? ovf overflow signal tcnt h'ff h'00 figure 12.10 timing of ovf flag setting 12.6 operation with cascaded connection if bits cks2 to cks0 in either tcr_0 or tcr_1 are set to b'100, the 8-bit timers of the two channels are cascaded. with this configuration, a single 16-bit timer can be used (16-bit count mode) or the compare-matches of the 8-bit timer of channel 0 can be counted by the 8-bit timer of channel 1 (compare-match count mode). 12.6.1 16-bit count mode when bits cks2 to cks0 in tcr_0 are set to b'100, the timer functions as a single 16-bit timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits. setting of compare-match flags: the cmf flag in tcsr_0 is set to 1 when a 16-bit compare-match occurs. the cmf flag in tcsr_1 is set to 1 when a lower 8-bit compare-match occurs. counter clear specification: if the cclr1 and cclr0 bits in tcr_0 have been set for counter clear at compare-match, the 16-bit counter (tcnt_0 and tcnt_1 together) is cleared when a 16-bit compare-match occurs. the 16-bit counter (tcnt_0 and tcnt_1 together) is also cleared when counter clear by the tmi0 pin has been set. the settings of the cclr1 and cclr0 bits in tcr_1 are ignored. the lower 8 bits cannot be cleared independently. rev. 2.0, 08/02, page 287 of 788 pin output: control of output from the tmo0 pin by bits os3 to os0 in tcsr_0 is in accordance with the 16-bit compare-match conditions. control of output from the tmo1 pin by bits os3 to os0 in tcsr_1 is in accordance with the lower 8-bit compare-match conditions. 12.6.2 compare-match count mode when bits cks2 to cks0 in tcr_1 are b'100, tcnt_1 counts the occurrence of compare-match a for channel 0. channels 0 and 1 are controlled independently. conditions such as setting of the cmf flag, generation of interrupts, output from the tmo pin, and counter clearing are in accordance with the settings for each channel. 12.7 input capture operation tmr_x has input capture registers (ticr, ticrr and ticrf). a narrow pulse width can be measured with ticrr and ticrf, using a single capture operation controlled by the icst bit in tconri of the timer connection. if the falling edge of tmrix is detected after its rising edge has been detected while the icst bit is set to 1, the value of tcnt at that time is transferred to both ticrr and ticrf, and the icst bit is cleared to 0. the input signal to tmrix can be switched by the setting of the other bits in tconri. rev. 2.0, 08/02, page 288 of 788 input capture signal input timing: figure 12.11 shows the timing of the input capture operation. ? tmrix input capture signal tcntx n nn m m m n + 1 n n n + 1 ticrr ticrf figure 12.11 timing of input capture operation if the input capture signal is input while ticrr and ticrf are being read, the input capture signal is delayed by one system clock ( ?) cycle. figure 12.12 shows the timing of this operation. ? tmrix ticrr, ticrf read cycle t 1 t 2 input capture signal figure 12.12 timing of input capture signal (input capture signal is input during ticrr and ticrf read) rev. 2.0, 08/02, page 289 of 788 selection of input capture signal input: input capture input signal of tmr_x (tmrix) is switched according to the setting of the bits in tconri of the timer connection. input capture signal selections are shown in figure 12.13 and table 12.3. for details, see section 13.3.1, timer connection register i (tconri). tmix pin tmri1 pin tmci1 pin polarity inversion polarity inversion polarity inversion signal selector tmrix tmr_x hfinv, hiinv simod1, simod0 icst figure 12.13 input capture signal selection table 12.3 input capture signal selection tconri bit 4 bit 7 bit 6 bit 3 bit 1 icst simod1 simod0 hfinv hiinv description 0 i nput capture function not used 0 tmix pin input selection 0 1 inverted tmix pin input selection 0 tmri1 pin input selection 0 1 1 inverted tmri1 pin input selection 0 tmci1 pin input selection 1 11 1 inverted tmci1 pin input selection rev. 2.0, 08/02, page 290 of 788 12.8 interrupt sources tmr_0, tmr_1, and tmr_y can generate three types of interrupts: cmia, cmib, and ovi. tmr_x can generate an icix interrupt. table 12.4 shows the interrupt sources and priorities. each interrupt source can be enabled or disabled independently by interrupt enable bits in tcr or tcsr. independent signals are sent to the interrupt controller for each interrupt. the cmia and cmib interrupts can be used as dtc activation interrupt sources. table 12.4 interrupt sources of 8-bit timers tmr_0, tmr_1, tmr_y, and tmr_x channel name interrupt source interrupt flag dtc activation interrupt priority cmia0 tcora_0 compare-match cmfa enabled high cmib0 tcorb_0 compare-match cmfb enabled tmr_0 ovi0 tcnt_0 overflow ovf disabled cmia1 tcora_1 compare-match cmfa enabled cmib1 tcorb_1 compare-match cmfb enabled tmr_1 ovi1 tcnt_1 overflow ovf disabled cmiay tcora_y compare-match cmfa enabled cmiby tcorb_y compare-match cmfb enabled tmr_y oviy tcnt_y overflow ovf disabled tmr_x icix input capture icf disabled low rev. 2.0, 08/02, page 291 of 788 12.9 usage notes 12.9.1 conflict between tcnt write and clear if a counter clear signal is generated during the t2 state of a tcnt write cycle as shown in figure 12.14, clearing takes priority, so that the counter is cleared and the write is not performed. ? address tcnt address internal write signal tcnt input clock tcnt n h'00 t 1 t 2 tcnt write cycle by cpu figure 12.14 conflict between tcnt write and clear rev. 2.0, 08/02, page 292 of 788 12.9.2 conflict between tcnt write and increment if a tcnt input clock is generated during the t2 state of a tcnt write cycle as shown in figure 12.15, the write takes priority and the counter is not incremented. ? address tcnt address internal write signal tcnt input clock tcnt nm t 1 t 2 tcnt write cycle by cpu counter write data figure 12.15 conflict between tcnt write and increment rev. 2.0, 08/02, page 293 of 788 12.9.3 conflict between tcor write and compare-match if a compare-match occurs during the t2 state of a tcor write cycle as shown in figure 12.16, the tcor write takes priority and the compare-match signal is disabled. with tmr_x, a ticr input capture conflicts with a compare-match in the same way as with a write to tcorc. in this case also, the input capture takes priority and the compare-match signal is disabled. ? address tcor address internal write signal tcnt tcor nm t 1 t 2 tcor write cycle by cpu tcor write data n n + 1 compare-match signal disabled figure 12.16 conflict between tcor write and compare-match rev. 2.0, 08/02, page 294 of 788 12.9.4 conflict between compare-matches a and b if compare-matches a and b occur at the same time, the 8-bit timer operates in accordance with the priorities for the output states set for compare-match a and compare-match b, as shown in table 12.5. table 12.5 timer output priorities output setting priority toggle output high 1 output 0 output no change low 12.9.5 switching of internal clocks and tcnt operation tcnt may increment erroneously when the internal clock is switched over. table 12.6 shows the relationship between the timing at which the internal clock is switched (by writing to the cks1 and cks0 bits) and the tcnt operation. when the tcnt clock is generated from an internal clock, the falling edge of the internal clock pulse is detected. if clock switching causes a change from high to low level, as shown in no. 3 in table 12.6, a tcnt clock pulse is generated on the assumption that the switchover is a falling edge, and tcnt is incremented. erroneous incrementation can also happen when switching between internal and external clocks. rev. 2.0, 08/02, page 295 of 788 table 12.6 switching of internal clocks and tcnt operation no. timing of switchover by means of cks1 and cks0 bits tcnt clock operation 1 clock switching from low to low level * 1 clock before switchover clock after switchover tcnt clock tcnt cks bit rewrite n n + 1 2 clock switching from low to high level * 2 clock before switchover clock after switchover tcnt clock tcnt cks bit rewrite n n + 1 n + 2 rev. 2.0, 08/02, page 296 of 788 no. timing of switchover by means of cks1 and cks0 bits tcnt clock operation 3 clock switching from high to low level * 3 clock before switchover clock after switchover tcnt clock tcnt cks bit rewrite n n + 1 n + 2 * 4 4 clock switching from high to high level clock before switchover clock after switchover tcnt clock tcnt cks bit rewrite n n + 1 n + 2 notes: 1. includes switching from low to stop, and from stop to low. 2. includes switching from stop to high. 3. includes switching from high to stop. 4. generated on the assumption that the switchover is a falling edge; tcnt is incremented. 12.9.6 mode setting with cascaded connection if the 16-bit count mode and compare-match count mode are set simultaneously, the input clock pulses for tcnt_0 and tcnt_1 are not generated, and thus the counters will stop operating. simultaneous setting of these two modes should therefore be avoided. 12.9.7 module stop mode setting tmr operation can be enabled or disabled using the module stop control register. the initial setting is for tmr operation to be halted. register access is enabled by canceling the module stop mode. for details, refer to section 26, power-down modes. rev. 2.0, 08/02, page 297 of 788 section 13 timer connection this lsi allows interconnection between a 16-bit free-running timer (frt) and three 8-bit timer channels (tmr_1, tmr_x, and tmr_y). this capability can be used to implement complex functions such as pwm decoding and clamp waveform output. 13.1 features five input pins and four output pins, all of which can be designated for phase inversion. positive logic is assumed for all signals used within the timer connection facility. an edge-detection circuit is connected to the input pins, simplifying signal input detection. tmr_x can be used for pwm input signal decoding. tmr_x can be used for clamp waveform generation. an external clock signal divided by tmr_1 can be used as the frt capture input signal. an internal synchronization signal can be generated using the frt and tmr_y. a signal generated/modified using an input signal and timer connection can be selected and output. timc0n01_010020020700 rev. 2.0, 08/02, page 298 of 788 figure 13.1 shows a block diagram of the timer connection facility. edge detection edge detection vsynci/ ftia/tmiy vfbacki/ ftib ftic ftid phase inversion phase inversion phase inversion phase inversion phase inversion phase inversion ivi signal selection read flag edge detection edge detection edge detection phase inversion phase inversion phase inversion read flag ivi signal frt input selec- tion set sync res vsync modify ftia ftib ftic ftid 16-bit frt ocra +vr, +vf icrd +1m, +2m compare match ftoa cma(r) cma(f) ftob cm2m cm1m res set 2f h mask generation 2f h mask/flag cblank waveform generation tmr1 input selection tmci 8-bit tmr1 tmri cmb tmo set ivg signal ivo signal res vsync generation ivo signal selection tmiy signal selection frt output selection vsynco/ ftoa tmri/tmci tmo 8-bit tmry ihg signal cblank hsynco/ tmo1 tmox tmo1 output selection iho signal selection cl4 generation cl4 signal clampo/ ftic cl signal selection pdc signal pwm decoding 8-bit tmrx cmb tmo cma icr icr +1c compare match clamp waveform generation tmci tmri cm1c cl1 signal cl2 signal cl3 signal ihi signal ihi signal selection hsynci/ tmci1 csynci/ tmri1 hfbacki/ ftci/tmix figure 13.1 block diagram of timer connection rev. 2.0, 08/02, page 299 of 788 13.2 input/output pins table 13.1 lists the timer connection input and output pins. table 13.1 pin configuration name abbreviation input/ output function vertical synchronization signal input pin vsynci input vertical synchronization signal input pin or ftia input pin/tmiy input pin horizontal synchronization signal input pin hsynci input horizontal synchronization signal input pin or tmci1 input pin composite synchronization signal input pin csynci input composite synchronization signal input pin or tmri1 input pin spare vertical synchronization signal input pin vfbacki input spare vertical synchronization signal input pin or ftib input pin spare horizontal synchronization signal input pin hfbacki input spare horizontal synchronization signal input pin or ftci input pin/tmix input pin vertical synchronization signal output pin vsynco output vertical synchronization signal output pin or ftoa output pin horizontal synchronization signal output pin hsynco output horizontal synchronization signal output pin or tmo1 output pin clamp waveform output pin clampo output clamp waveform output pin or ftic input pin blanking waveform output pin cblank output blanking waveform output pin 13.3 register descriptions the timer connection has the following registers. timer connection register i (tconri) timer connection register o (tconro) timer connection register s (tconrs) edge sense register (sedgr) rev. 2.0, 08/02, page 300 of 788 13.3.1 timer connection register i (tconri) tconri controls connection between timers, the signal source for synchronization signal input, phase inversion, etc. bit bit name initial value r/w description 7 6 simod1 simod0 0 0 r/w r/w input synchronization mode select 1, 0 these bits select the signal source of the ihi and ivi signals. mode 00: no signal 01: s-on-g mode 10: composite mode 11: separate mode ihi signal 00: hfbacki input 01: csynci input 1x: hsynci input ivi signal 00: vfbacki input 01: pdc input 10: pdc input 11: vsynci input 5 scone 0 r/w synchronization signal connection enable selects the signal source of the frt fti input and the tmr_1 tmi1 input and tmci1/tmri1 input. for details, see table 13.2. rev. 2.0, 08/02, page 301 of 788 bit bit name initial value r/w description 4 icst 0 r/w input capture start bit the tmr_x external reset input (tmrix) is connected to the ihi signal. tmr_x has input capture registers (ticr, ticrr, and ticrf). ticrr and ticrf can measure the width of a pulse by means of a single capture operation under the control of the icst bit. when a rising edge followed by a falling edge is detected on tmrix after the icst bit is set to 1, the contents of tcnt at those points are captured into ticrr and ticrf, respectively, and the icst bit is cleared to 0. [clearing condition] when a rising edge followed by a falling edge is detected on tmrix [setting condition] when 1 is written in icst after reading icst = 0 rev. 2.0, 08/02, page 302 of 788 bit bit name initial value r/w description 3 2 1 0 hfinv vfinv hiinv viinv 0 0 0 0 r/w r/w r/w r/w input synchronization signal inversion these bits select inversion of the input phase of the spare horizontal synchronization signal (hfbacki), the spare vertical synchronization signal (vfbacki), the horizontal synchronization signal (hsynci), composite synchronization signal (csynci), and the vertical synchronization signal (vsynci). hfinv 0: the hfbacki pin state is used directly as the hfbacki input 1: the hfbacki pin state is inverted before use as the hfbacki input vfinv 0: the vfbacki pin state is used directly as the vfbacki input 1: the vfbacki pin state is inverted before use as the vfbacki input hiinv 0: the hsynci and csynci pin states are used directly as the hsynci and csynci inputs 1: the hsynci and csynci pin states are inverted before use as the hsynci and csynci inputs viinv 0: the vsynci pin state is used directly as the vsynci input 1: the vsynci pin state is inverted before use as the vsynci input legend x: dont care table 13.2 synchronization signal connection enable bit 5 description scone mode ftia ftib ftic ftid tmci1 tmri1 0 normal connection (initial value) ftia input ftib input ftic input ftid input tmci1 input tmri1 input 1 synchronization signal connection mode ivi signal tmo1 signal vfbacki input ihi signal ihi signal ivi inverse signal rev. 2.0, 08/02, page 303 of 788 13.3.2 timer connection register o (tconro) tconro controls output signal output, phase inversion, etc. bit bit name initial value r/w description 7 6 5 4 hoe voe cloe cboe 0 0 0 0 r/w r/w r/w r/w output enable these bits control enabling/disabling of output of horizontal synchronization signal (hsynco), vertical synchronization signal (vsynco), clamp waveform (clampo), and blanking waveform (cblank). when output is disabled, the state of the relevant pin is determined by port dr and ddr, frt, tmr, and pwm settings. output enabling/disabling control does not affect the port, frt, or tmr input functions, but some frt and tmr input signal sources are determined by the scone bit in tconri. hoe: 0: the p44/tmo1/hirq1/hsynco pin functions as the p44/tmo1/hirq1 pin 1: the p44/tmo1/hirq1/hsynco pin functions as the hsynco pin voe: 0: the p61/ftoa/cin1/ .,1 4 /vsynco pin functions as the p61/ftoa/cin1/ .,1 4 pin 1: the p61/ftoa/cin1/ .,1 4 /vsynco pin functions as the vsynco pin cloe: 0: the p64/ftic/cin4/ .,1 7 /clampo pin functions as the p64/ftic/cin4/ .,1 7 pin 1: the p64/ftic/cin4/ .,1 7 /clampo pin functions as the clampo pin cboe: 0: the p27/a15/pw15/cblank pin functions as the p27/a15/pw15 pin in mode 1: 1: the p27/a15/pw15/cblank pin functions as the a15 pin in modes 2 and 3: 1: the p27/a15/pw15/cblank pin functions as the cblank pin rev. 2.0, 08/02, page 304 of 788 bit bit name initial value r/w description 3 2 1 0 hoinv voinv cloinv cboinv 0 0 0 0 r/w r/w r/w r/w output synchronization signal inversion these bits select inversion of the output phase of the horizontal synchronization signal (hsynco), the vertical synchronization signal (vsynco), the clamp waveform (clampo), and the blanking waveform (cblank). hoinv: 0: the iho signal is used directly as the hsynco output 1: the iho signal is inverted before use as the hsynco output voinv: 0: the ivo signal is used directly as the vsynco output 1: the ivo signal is inverted before use as the vsynco output cloinv: 0: the clo signal (cl1, cl2, cl3, or cl4 signal) is used directly as the clampo output 1: the clo signal (cl1, cl2, cl3, or cl4 signal) is inverted before use as the clampo output cboinv: 0: the cblank signal is used directly as the cblank output 1: the cblank signal is inverted before use as the cblank output rev. 2.0, 08/02, page 305 of 788 13.3.3 timer connection register s (tconrs) tconrs selects whether to access tmr_x or tmr_y registers, and the synchronization signal output signal source and generation method. bit bit name initial value r/w description 7 tmrx/y 0 r/w tmr_x/tmr_y access select for details, see table 13.3. 0: the tmr_x registers are accessed at addresses h'(ff)fff0 to h'(ff)fff5 1: the tmr_y registers are accessed at addresses h'(ff)fff0 to h'(ff)fff5 6 isgene 0 r/w internal synchronization signal selects internal synchronization signals (ihg, ivg, and cl4 signals) as the signal sources for the iho, ivo, and clo signals together with the homod1, homod0, vomod1, vomod0, clmod1, and clmod0 bits. 5 4 homod1 homod0 0 0 r/w r/w horizontal synchronization output mode select 1, 0 these bits select the signal source and generation method for the iho signal. isgene = 0 00: the ihi signal (without 2fh modification) is selected 01: the ihi signal (with 2fh modification) is selected 1x: the cl1 signal is selected isgene = 1 xx: the ihg signal is selected rev. 2.0, 08/02, page 306 of 788 bit bit name initial value r/w description 3 2 vomod1 vomod0 0 0 r/w r/w vertical synchronization output mode select 1, 0 these bits select the signal source and generation method for the ivo signal. isgene = 0 00: the ivi signal (without fall modification or ihi synchronization) is selected 01: the ivi signal (without fall modification, with ihi synchronization) is selected 10: the ivi signal (with fall modification, without ihi synchronization) is selected 11: the ivi signal (with fall modification and ihi synchronization) is selected isgene = 1 xx: the ivg signal is selected 1 0 clmod1 clmod0 0 0 r/w r/w clamp waveform mode select 1, 0 these bits select the signal source for the clo signal (clamp waveform). isgene = 0 00: the cl1 signal is selected 01: the cl2 signal is selected 1x: the cl3 signal is selected isgene = 1 xx: the cl4 signal is selected legend x: dont care table 13.3 registers accessible by tmr_x/tmr_y tmrx/y h'fff0 h'fff1 h'fff2 h'fff3 h'fff4 h'fff5 h'fff6 h'fff7 0tmr_x tcr_x tmr_x tcsr_x tmr_x ticrr tmr_x ticrf tmr_x tcnt_x tmr_x tcorc 1tmr_y tcr_y tmr_y tcsr_y tmr_y tcora_y tmr_y tcorb_y tmr_y tcnt_y tmr_y tisr tmr_x tcora_x tmr_x tcorb_x rev. 2.0, 08/02, page 307 of 788 13.3.4 edge sense register (sedgr) sedgr detects a rising edge on the timer connection input pins and the occurrence of 2fh modification, and determines the phase of the ivi and ihi signals. bit bit name initial value r/w description 7 vedg 0 r/(w) * 1 vsynci edge detects a rising edge on the vsynci pin. [clearing condition] when 0 is written in vedg after reading vedg = 1 [setting condition] when a rising edge is detected on the vsynci pin 6 hedg 0 r/(w) * 1 hsynci edge detects a rising edge on the hsynci pin. [clearing condition] when 0 is written in hedg after reading hedg = 1 [setting condition] when a rising edge is detected on the hsynci pin 5 cedg 0 r/(w) * 1 csynci edge detects a rising edge on the csynci pin. [clearing condition] when 0 is written in cedg after reading cedg = 1 [setting condition] when a rising edge is detected on the csynci pin 4 hfedg 0 r/(w) * 1 hfbacki edge detects a rising edge on the hfbacki pin. [clearing condition] when 0 is written in hfedg after reading hfedg = 1 [setting condition] when a rising edge is detected on the hfbacki pin 3 vfedg 0 r/(w) * 1 vfbacki edge detects a rising edge on the vfbacki pin. [clearing condition] when 0 is written in vfedg after reading vfedg = 1 [setting condition] when a rising edge is detected on the vfbacki pin rev. 2.0, 08/02, page 308 of 788 bit bit name initial value r/w description 2preqf0 r/(w) * 1 pre-equalization flag detects the occurrence of an ihi signal 2fh modification condition. the generation of a falling/rising edge in the ihi signal during a mask interval is expressed as the occurrence of a 2fh modification condition. for details, see section 13.4.4, 2fh modification of ihi signal. [clearing condition] when 0 is written in preqf after reading preqf = 1 [setting condition] when an ihi signal 2fh modification condition is detected 1 ihi undefined * 2 r ihi signal level indicates the current level of the ihi signal. signal source and phase inversion selection for the ihi signal depends on the contents of tconri. read this bit to determine whether the input signal is positive or negative, then maintain the ihi signal at positive phase by modifying tconri. 0: the ihi signal is low 1: the ihi signal is high 0 ivi undefined * 2 r ivi signal level indicates the current level of the ivi signal. signal source and phase inversion selection for the ivi signal depends on the contents of tconri. read this bit to determine whether the input signal is positive or negative, then maintain the ivi signal at positive phase by modifying tconri. 0: the ivi signal is low 1: the ivi signal is high notes: 1. only 0 can be written, to clear the flag. 2. the initial value is undefined since it depends on the pin state. rev. 2.0, 08/02, page 309 of 788 13.4 operation 13.4.1 pwm decoding (pdc signal generation) the timer connection facility and tmr_x can be used to decode a pwm signal in which 0 and 1 are represented by the pulse width. to do this, a signal in which a rising edge is generated at regular intervals must be selected as the ihi signal. the timer counter (tcnt) in tmr_x is set to count the internal clock pulses and to be cleared on the rising edge of the external reset signal (ihi signal). the value to be used as the threshold for deciding the pulse width is written in tcorb. the pwm decoder contains a delay latch which uses the ihi signal as data and compare-match signal b (cmb) as a clock, and the state of the ihi signal (the result of the pulse width decision) at the first compare-match signal b timing after tcnt is reset by the rise of the ihi signal is output as the pdc signal. the pulse width setting using ticrr and ticrf of tmr_x can be used to determine the pulse width decision threshold. examples of tcr and tcorb settings of tmr_x are shown in tables 13.4 and 13.5, and the pwm decoding timing chart is shown in figure 13.2. table 13.4 examples of tcr settings bit abbreviation contents description 7 cmieb 0 6 cmiea 0 5ovie 0 interrupts due to compare-match and overflow are disabled 4 and 3 cclr1 and cclr0 11 tcnt is cleared by the rising edge of the external reset signal (ihi signal) 2 to 0 cks2 to cks0 001 incremented on internal clock (?) table 13.5 examples of tcorb (pulse width threshold) settings ?: 10 mhz ?: 12 mhz ?: 16 mhz ?: 20 mhz h'07 0.8 s 0.67 s 0.5 s 0.4 s h'0f 1.6 s 1.33 s 1 s 0.8 s h'1f 3.2 s 2.67 s 2 s 1.6 s h'3f 6.4 s 5.33 s 4 s 3.2 s h'7f 12.8 s 10.67 s 8 s 6.4 s rev. 2.0, 08/02, page 310 of 788 ihi signal ihi signal is tested at compare-match counter reset caused by ihi signal counter clear caused by tcnt overflow at the 2nd compare-match, ihi signal is not tested pdc signal tcnt tcorb (threshold) figure 13.2 timing chart for pwm decoding 13.4.2 clamp waveform generation (cl1/cl2/cl3 signal generation) the timer connection facility and tmr_x can be used to generate signals with different duty cycles and rising/falling edges (clamp waveforms) in synchronization with the input signal (ihi signal). three clamp waveforms can be generated: the cl1, cl2, and cl3 signals. in addition, the cl4 signal can be generated using tmr_y. the cl1 signal rises simultaneously with the rise of the ihi signal, and when the cl1 signal is high, the cl2 signal rises simultaneously with the fall of the ihi signal. the fall of both the cl1 and cl2 signals can be specified by tcora. the rise of the cl3 signal can be specified as simultaneous with the sampling of the fall of the ihi signal using the system clock, and the fall of the cl3 signal can be specified by tcorc. the cl3 signal can also fall when the ihi signal rises. tcnt in tmr_x is set to count internal clock pulses and to be cleared on the rising edge of the external reset signal (ihi signal). the value to be used as the cl1 signal pulse width is written in tcora. write a value of h'02 or more in tcora when internal clock ? is selected as the tmr_x counter clock, and a value or h'01 or more when ?/2 is selected. when internal clock ? is selected, the cl1 signal pulse width is (tcora set value + 3 0.5). when the cl2 signal is used, the setting must be made so that this pulse width is greater than the ihi signal pulse width. the value to be used as the cl3 signal pulse width is written in tcorc. ticr in tmr_x captures the value of tcnt at the inverse of the external reset signal edge (in this case, the falling edge of the ihi signal). the timing of the fall of the cl3 signal is determined by the sum of the contents of ticr and tcorc. caution is required if the rising edge of the ihi signal precedes the fall timing set by the contents of tcorc, since the ihi signal will cause the cl3 signal to fall. rev. 2.0, 08/02, page 311 of 788 examples of tcr settings of tmr_x are the same as those in table 13.4. the clamp waveform timing charts are shown in figures 13.3 and 13.4. since the rise of the cl1 and cl2 signals is synchronized with the edge of the ihi signal, and their fall is synchronized with the system clock, the pulse width variation is equivalent to the resolution of the system clock. both the rise and the fall of the cl3 signal are synchronized with the system clock and the pulse width is fixed, but there is a variation in the phase relationship with the ihi signal equivalent to the resolution of the system clock. ihi signal cl1 signal cl2 signal tcnt tcora figure 13.3 timing chart for clamp waveform generation (cl1 and cl2 signals) ihi signal cl3 signal tcnt ticr + tcorc ticr figure 13.4 timing chart for clamp waveform generation (cl3 signal) rev. 2.0, 08/02, page 312 of 788 13.4.3 measurement of 8-bit timer divided waveform period the timer connection facility, tmr_1, and the free-running timer (frt) can be used to measure the period of an ihi signal divided waveform. since tmr_1 can be cleared by a rising edge of the inverted ivi signal, the rise and fall of the ihi signal divided waveform can be synchronized with the ivi signal. this enables period measurement to be carried out efficiently. to measure the period of an ihi signal divided waveform, tcnt in tmr_1 is set to count the external clock (ihi signal) pulses and to be cleared on the rising edge of the external reset signal (inverse of the ivi signal). the value to be used as the division factor is written in tcora, and the tmo output method is specified by the os bits in tcsr. examples of tcr and tcsr settings in tmr_1, and tcr and tcsr settings in the frt are shown in table 13.6, and the timing chart for measurement of the ivi signal and ihi signal divided waveform periods is shown in figure 13.5. the period of the ihi signal divided waveform is given by (icrd(3) C icrd(2)) resolution. rev. 2.0, 08/02, page 313 of 788 table 13.6 examples of tcr and tcsr settings register bit abbreviation contents description 7 cmieb 0 6 cmiea 0 5ovie 0 interrupts due to compare-match and overflow are disabled 4 and 3 cclr1 and cclr0 11 tcnt is cleared by the rising edge of the external reset signal (inverse of the ivi signal) tcr in tmr_1 2 to 0 cks2 to cks0 101 tcnt is incremented on the rising edge of the external clock (ihi signal) 0011 not changed by compare-match b; output inverted by compare-match a (toggle output): division by 512 tcsr in tmr_1 3 to 0 os3 to os0 1001 when tcorb < tcora, 1 output on compare-match b, and 0 output on compare-match a: division by 256 6 iedgb 0/1 0: frc value is transferred to icrb on falling edge of input capture input b (ihi divided signal waveform) 1: frc value is transferred to icrb on rising edge of input capture input b (ihi divided signal waveform) tcr in frt 1 and 0 cks1 and cks0 01 frc is incremented on internal clock: ?/8 tcsr in frt 0 cclra 0 frc clearing is disabled rev. 2.0, 08/02, page 314 of 788 ivi signal ihi signal divided waveform frc icrb icrb(1) icrb(2) icrb(3) icrb(4) figure 13.5 timing chart for measurement of ivi signal and ihi signal divided waveform periods 13.4.4 2fh modification of ihi signal by using the timer connection facility and frt, even if there is a part of the ihi signal with twice the frequency, this can be eliminated. in order for this function to operate properly, the duty cycle of the ihi signal must be approximately 30% or less, or approximately 70% or above. the 8-bit ocrdm contents or twice the ocrdm contents can be added automatically to the data captured in icrd in the frt, and compare-matches generated at these points. the interval between the two compare-matches is called a mask interval. a value equivalent to approximately 1/3 the ihi signal period is written in ocrdm. icrd is set so that capture is performed on the rise of the ihi signal. since the ihi signal supplied to the iho signal selection circuit is normally set on the rise of the ihi signal and reset on the fall, its waveform is the same as that of the original ihi signal. when 2fh modification is selected, ihi signal edge detection is disabled during mask intervals. capture is also disabled during these intervals. examples of tcr, tcsr, tocr, and ocrdm settings in the frt are shown in table 13.7, and the 2fh modification timing chart is shown in figure 13.6. rev. 2.0, 08/02, page 315 of 788 table 13.7 examples of tcr, tcsr, tocr, and ocrdm settings register bit abbreviation contents description 4 iedgd 1 frc value is transferred to icrd on the rising edge of input capture input d (ihi signal) tcr in frt 1 and 0 cks1 and cks0 01 frc is incremented on internal clock: ?/8 tcsr in frt 0 cclra 0 frc clearing is disabled tocr in frt 7 icrdms 1 icrd is set to the operating mode in which ocrdm is used ocrdm in frt 7 to 0 ocrdm7 to ocrdm0 h'01 to h'ff specifies the period during which icrd operation is masked ihi signal (without 2fh modification) ihi signal (with 2fh modification) mask interval icrd + ocrdm 2 icrd + ocrdm frc icrd figure 13.6 2fh modification timing chart rev. 2.0, 08/02, page 316 of 788 13.4.5 ivi signal fall modification and ihi synchronization by using the timer connection facility and tmr_1, the fall of the ivi signal can be shifted backward by the specified number of ihi signal waveforms. also, the fall of the ivi signal can be synchronized with the rise of the ihi signal. to perform 8-bit timer divided waveform period measurement, tcnt in tmr_1 is set to count external clock (ihi signal) pulses, and to be cleared on the rising edge of the external reset signal (inverse of the ivi signal). the number of ihi signal pulses until the fall of the ivi signal is written in tcorb. since the ivi signal supplied to the ivo signal selection circuit is normally set on the rise of the ivi signal and reset on the fall, its waveform is the same as that of the original ivi signal. when fall modification is selected, a reset is performed on a tmr_1 tcorb compare-match in tmr_1. the fall of the waveform generated in this way can be synchronized with the rise of the ihi signal, regardless of whether or not fall modification is selected. examples of tcr, tcsr, and tcorb settings in tmr_1 are shown in table 13.8, and the fall modification/ihi synchronization timing chart is shown in figure 13.7. table 13.8 examples of tcr, tcsr, and tcorb settings register bit abbreviation contents description 7 cmieb 0 6 cmiea 0 5ovie 0 interrupts due to compare-match and overflow are disabled 4 and 3 cclr1 and cclr0 11 tcnt is cleared by the rising edge of the external reset signal (inverse of the ivi signal) tcr in tmr_1 2 to 0 cks2 to cks0 101 tcnt is incremented on the rising edge of the external clock (ihi signal) 0011 not changed by compare-match b; output inverted by compare-match a (toggle output) tcsr in tmr_1 3 to 0 os3 to os0 1001 when tcorb < tcora, 1 output on compare-match b, 0 output on compare- match a tcorb in tmr_1 h'03 (example) compare-match on the 4th (example) rise of the ihi signal after the rise of the inverse of the ivi signal rev. 2.0, 08/02, page 317 of 788 0 1 2 3 4 5 tcnt tcnt = tcorb (3) ihi signal ivi signal (pdc signal) ivo signal (without fall modification, with ihi synchronization) ivo signal (with fall modification, without ihi synchronization) ivo signal (with fall modification and ihi synchronization) figure 13.7 fall modification and ihi synchronization timing chart 13.4.6 internal synchronization signal generation (ihg/ivg/cl4 signal generation) by using the timer connection facility, frt, and tmr_y, it is possible to automatically generate internal signals (ihg and ivg signals) corresponding to the ihi and ivi signals. as the ihg signal is synchronized with the rise of the ivg signal, the ihg signal period must be made a divisor of the ivg signal period in order to keep it constant. in addition, the cl4 signal can be generated in synchronization with the ihg signal. the contents of ocra in the frt are updated by the automatic addition of the contents of ocrar or ocraf, alternately, each time a compare-match occurs. a value corresponding to the 0 interval of the ivg signal is written in ocrar, and a value corresponding to the 1 interval of the ivg signal is written in ocraf. the ivg signal is set by a compare-match after an ocrar addition, and reset by a compare-match after an ocraf addition. the ihg signal is the tmr_y timer output. tmr_y is set to count internal clock pulses, and to be cleared on a tcora compare-match, to fix the period and set the timer output. tcorb is set so as to reset the timer output. the ivg signal is connected as the tmr_y reset input (tmri), and the rise of the ivg signal can be treated in the same way as a tcora compare-match. the cl4 signal is a waveform that rises within one system clock period after the fall of the ihg signal, and has an interval of 1 for 6 system clock periods. examples of tcr, tcsr, tcora, and tcorb settings in tmr_y, and tcr, ocrar, ocraf, and tocr settings in the frt are shown in table 13.9, and the ihg signal/ivg signal timing chart is shown in figure 13.8. rev. 2.0, 08/02, page 318 of 788 table 13.9 examples of ocrar, ocraf, tcora, tcorb, tcr, and tcsr settings register bit abbreviation contents description 7 cmieb 0 6 cmiea 0 5ovie 0 interrupts due to compare-match and overflow are disabled 4 and 3 cclr1 and cclr0 01 tcnt is cleared by compare-match a tcr in tmr_y 2 to 0 cks2 to cks0 001 tcnt is incremented on internal clock: ?/4 tcsr in tmr_y 3 to 0 os3 to os0 0110 0 output on compare-match b 1 output on compare-match a tcora in tmr_y h'3f (example) ihg signal period = ? 256 tcorb in tmr_y h'03 (example) ihg signal 1 interval = ? 16 tcr in frt 1 and 0 cks1 and cks0 01 frc is incremented on internal clock: ?/8 ocrar in frt h'7fef (example) ivg signal 0 interval = ? 262016 ocraf in frt h'000f (example) ivg signal 1 interval = ? 128 ivg signal period = ? 262144 (1024 times ihg signal) tocr in frt 6 ocrams 1 ocra is set to the operating mode in which ocrar and ocraf are used rev. 2.0, 08/02, page 319 of 788 6 system clocks 6 system clocks 6 system clocks ocra (4) = ocra (3) + ocrar ocra (3) = ocra (2) + ocraf ocra (2) = ocra (1) + ocrar ocra (1) = ocra (0) + ocraf ocra frc cl4 signal ihg signal tcora tcorb tcnt ivg signal figure 13.8 ivg signal/ihg signal/cl4 signal timing chart rev. 2.0, 08/02, page 320 of 788 13.4.7 hsynco output with the hsynco output, the meaning of the signal source to be selected and use or non-use of modification varies according to the ihi signal source and the waveform required by external circuitry. the hsynco output modes are shown in table 13.10. table 13.10 hsynco output modes mode ihi signal iho signal meaning of iho signal ihi signal (without 2fh modification) hfbacki input is output directly ihi signal (with 2fh modification) meaningless unless there is a double-frequency part in the hfbacki input cl1 signal hfbacki input 1 interval is changed before output no signal hfbacki input ihg signal internal synchronization signal is output ihi signal (without 2fh modification) csynci input (composite synchronization signal) is output directly ihi signal (with 2fh modification) double-frequency part of csynci input (composite synchronization signal) is eliminated before output cl1 signal csynci input (composite synchronization signal) horizontal synchronization signal part is separated before output s-on-g mode csynci input ihg signal internal synchronization signal is output ihi signal (without 2fh modification) hsynci input (composite synchronization signal) is output directly ihi signal (with 2fh modification) double-frequency part of hsynci input (composite synchronization signal) is eliminated before output cl1 signal hsynci input (composite synchronization signal) horizontal synchronization signal part is separated before output composite mode hsynci input ihg signal internal synchronization signal is output ihi signal (without 2fh modification) hsynci input (horizontal synchronization signal) is output directly ihi signal (with 2fh modification) meaningless unless there is a double-frequency part in the hsynci input (horizontal synchronization signal) cl1 signal hsynci input (horizontal synchronization signal) 1 interval is changed before output separate mode hsynci input ihg signal internal synchronization signal is output rev. 2.0, 08/02, page 321 of 788 13.4.8 vsynco output with the vsynco output, the meaning of the signal source to be selected and use or non-use of modification varies according to the ivi signal source and the waveform required by external circuitry. the vsynco output modes are shown in table 13.11. table 13.11 vsynco output modes mode ivi signal ivo signal meaning of ivo signal ivi signal (without fall modification or ihi synchronization) vfbacki input is output directly ivi signal (without fall modification, with ihi synchronization) meaningless unless vfbacki input is synchronized with hfbacki input ivi signal (with fall modification, without ihi synchronization) vfbacki input fall is modified before output ivi signal (with fall modification and ihi synchronization) vfbacki input fall is modified and signal is synchronized with hfbacki input before output no signal vfbacki input ivg signal internal synchronization signal is output ivi signal (without fall modification or ihi synchronization) csynci/hsynci input (composite synchronization signal) vertical synchronization signal part is separated before output ivi signal (without fall modification, with ihi synchronization) csynci/hsynci input (composite synchronization signal) vertical synchronization signal part is separated, and signal is synchronized with csynci/hsynci input before output ivi signal (with fall modification, without ihi synchronization) csynci/hsynci input (composite synchronization signal) vertical synchronization signal part is separated, and fall is modified before output ivi signal (with fall modification and ihi synchronization) csynci/hsynci input (composite synchronization signal) vertical synchronization signal part is separated, fall is modified, and signal is synchronized with csynci/hsynci input before output s-on-g mode or composite mode pdc signal ivg signal internal synchronization signal is output rev. 2.0, 08/02, page 322 of 788 mode ivi signal ivo signal meaning of ivo signal ivi signal (without fall modification or ihi synchronization) vsynci input (vertical synchronization signal) is output directly ivi signal (without fall modification, with ihi synchronization) meaningless unless vsynci input (vertical synchronization signal) is synchronized with hsynci input (horizontal synchronization signal) ivi signal (with fall modification, without ihi synchronization) vsynci input (vertical synchronization signal) fall is modified before output ivi signal (with fall modification and ihi synchronization) vsynci input (vertical synchronization signal) fall is modified and signal is synchronized with hsynci input (horizontal synchronization signal) before output separate mode vsynci input ivg signal internal synchronization signal is output 13.4.9 cblank output using the signals generated/selected with timer connection, it is possible to generate a waveform based on the composite synchronization signal (blanking waveform). one kind of blanking waveform is generated by combining hfbacki and vfbacki inputs, with the phase polarity made positive by means of bits hfinv and vfinv in tconri, with the ivo signal. the logic of cblank output waveform generation is shown in figure 13.9. reset set cblank signal (positive) hfbacki input (positive) vfbacki input (positive) ivo signal (positive) q falling edge sensing rising edge sensing figure 13.9 cblank output waveform generation rev. 2.0, 08/02, page 323 of 788 13.5 usage note 13.5.1 module stop mode setting timer connection operation can be enabled or disabled using the module stop control register. the initial setting is for timer connection operation to be halted. register access is enabled by canceling the module stop mode. for details, refer to section 26, power-down modes. rev. 2.0, 08/02, page 324 of 788 rev. 2.0, 08/02, page 325 of 788 section 14 watchdog timer (wdt) this lsi incorporates two watchdog timer channels (wdt_0 and wdt_1). the watchdog timer can generate an internal reset signal or an internal nmi interrupt signal if a system crash prevents the cpu from writing to the timer counter, thus allowing it to overflow. simultaneously, it can output an overflow signal ( 5(62 ) externally. when this watchdog function is not needed, the wdt can be used as an interval timer. in interval timer operation, an interval timer interrupt is generated each time the counter overflows. a block diagram of the wdt_0 and wdt_1 is shown in figure 14.1. 14.1 features selectable from eight (wdt_0) or 16 (wdt_1) counter input clocks. switchable between watchdog timer mode and interval timer mode watchdog timer mode: if the counter overflows, an internal reset or an internal nmi interrupt is generated. when the lsi is selected to be internally reset at counter overflow, a low level signal is output from the 5(62 pin if the counter overflows. internal timer mode: if the counter overflows, an internal timer interrupt (wovi) is generated. wdt0102a_010020020700 rev. 2.0, 08/02, page 326 of 788 wovi0 (interrupt request signal) internal nmi (interrupt request signal * 2 ) signal * 1 internal reset signal * 1 tcnt_0 tcsr_0 ?/2 ?/64 ?/128 ?/512 ?/2048 ?/8192 ?/32768 ?/131072 internal clock overflow interrupt control reset control wovi1 (interrupt request signal) internal reset signal * 1 signal * 1 tcnt_1 tcsr_1 ?/2 ?/64 ?/128 ?/512 ?/2048 ?/8192 ?/32768 ?/131072 clock clock selection internal clock bus interface module bus tcsr_0 : timer control/status register_0 tcnt_0 : timer counter_0 tcsr_1 : timer control/status register_1 tcnt_1 : timer counter_1 notes: 1. the signal outputs the low level signal when the internal reset signal is generated due to a tcnt overflow of either wdt_0 or wdt_1. the internal reset signal first resets the wdt in which the overflow has occurred first. 2. the internal nmi interrupt signal can be independently output from either wdt_0 or wdt_1. the interrupt controller does not distinguish the nmi interrupt request from wdt_0 from that from wdt_1. internal bus wdt_1 legend internal nmi (interrupt request signal * 2 ) ?sub/2 ?sub/4 ?sub/8 ?sub/16 ?sub/32 ?sub/64 ?sub/128 ?sub/256 overflow interrupt control reset control clock clock selection bus interface module bus internal bus wdt_0 figure 14.1 block diagram of wdt rev. 2.0, 08/02, page 327 of 788 14.2 input/output pins the wdt has the pins listed in table 14.1. table 14.1 pin configuration name symbol i/o function reset output pin 5(62 output outputs the counter overflow signal in watchdog timer mode external sub-clock input pin excl input inputs the clock pulses to the wdt_1 prescaler counter 14.3 register descriptions the wdt has the following registers. to prevent accidental overwriting, tcsr and tcnt have to be written to in a method different from normal registers. for details, refer to section 14.6.1, notes on register access. for details on the system control register, refer to section 3.2.2, system control register (syscr). timer counter (tcnt) timer control/status register (tcsr) 14.3.1 timer counter (tcnt) tcnt is an 8-bit readable/writable up-counter. tcnt is initialized to h'00 when the tme bit in the timer control/status register (tcsr) is cleared to 0. rev. 2.0, 08/02, page 328 of 788 14.3.2 timer control/status register (tcsr) tcsr selects the clock source to be input to tcnt, and the timer mode. tcsr_0 bit bit name initial value r/w description 7ovf0 r/(w) * 1 overflow flag indicates that tcnt has overflowed (changes from hff to h00). [setting condition] when tcnt overflows (changes from hff to h00) however, when internal reset request generation is selected in watchdog timer mode, ovf is cleared automatically by the internal reset. [clearing conditions] when tcsr is read when ovf = 1 * 2 , then 0 is written to ovf when 0 is written to tme 6wt/ ,7 0 r/w timer mode select selects whether the wdt is used as a watchdog timer or interval timer. 0: interval timer mode 1: watchdog timer mode 5 tme 0 r/w timer enable when this bit is set to 1, tcnt starts counting. when this bit is cleared, tcnt stops counting and is initialized to h'00. 4 0 r/(w)reserved the initial value should not be modified. 3 rst/ 10, 0 r/w reset or nmi selects to request an internal reset or an nmi interrupt when tcnt has overflowed. 0: an nmi interrupt is requested 1: an internal reset is requested rev. 2.0, 08/02, page 329 of 788 bit bit name initial value r/w description 2 1 0 cks2 cks1 cks0 0 0 0 r/w r/w r/w clock select 2 to 0 selects the clock source to be input to. the overflow frequency for ? = 10 mhz is enclosed in parentheses. 000: ?/2 (frequency: 51.2 m s) 001: ?/64 (frequency: 1.64 ms) 010: ?/128 (frequency: 3.28 ms) 011: ?/512 (frequency: 13.1 ms) 100: ?/2048 (frequency: 52.4 ms) 101: ?/8192 (frequency: 209.7 ms) 110: ?/32768 (frequency: 0.84 s) 111: ?/131072 (frequency: 3.36 s) notes: 1. only 0 can be written, to clear the flag. 2. when ovf is polled with the interval timer interrupt disabled, ovf = 1 must be read at least twice. rev. 2.0, 08/02, page 330 of 788 tcsr_1 bit bit name initial value r/w description 7 ovf 0 r/(w) * 1 overflow flag indicates that tcnt has overflowed (changes from hff to h00). [setting condition] when tcnt overflows (changes from hff to h00) however, when internal reset request generation is selected in watchdog timer mode, ovf is cleared automatically by the internal reset. [clearing conditions] when tcsr is read when ovf = 1 * 2 , then 0 is written to ovf when 0 is written to tme 6wt/ ,7 0 r/w timer mode select selects whether the wdt is used as a watchdog timer or interval timer. 0: interval timer mode 1: watchdog timer mode 5 tme 0 r/w timer enable when this bit is set to 1, tcnt starts counting. when this bit is cleared, tcnt stops counting and is initialized to h'00. rev. 2.0, 08/02, page 331 of 788 bit bit name initial value r/w description 4 pss 0 r/w prescaler select selects the clock source to be input to tcnt. 0: counts the divided cycle of ?Cbased prescaler (psm) 1: counts the divided cycle of ?subCbased prescaler (pss) 3 rst/ 10, 0 r/w reset or nmi selects to request an internal reset or an nmi interrupt when tcnt has overflowed. 0: an nmi interrupt is requested 1: an internal reset is requested 2 1 0 cks2 cks1 cks0 0 0 0 r/w r/w r/w clock select 2 to 0 selects the clock source to be input to tcnt. the overflow cycle for ? = 10 mhz and ?sub = 32.768 khz is enclosed in parentheses. when pss = 0: 000: ?/2 (frequency: 51.2 m s) 001: ?/64 (frequency: 1.64 ms) 010: ?/128 (frequency: 3.28 ms) 011: ?/512 (frequency: 13.1 ms) 100: ?/2048 (frequency: 52.4 ms) 101: ?/8192 (frequency: 209.7 ms) 110: ?/32768 (frequency: 0.84 s) 111: ?/131072 (frequency: 3.36 s) when pss = 1: 000: ?sub/2 (cycle: 15.6 ms) 001: ?sub/4 (cycle: 31.3 ms) 010: ?sub/8 (cycle: 62.5 ms) 011: ?sub/16 (cycle: 125 ms) 100: ?sub/32 (cycle: 250 ms) 101: ?sub/64 (cycle: 500 ms) 110: ?sub/128 (cycle: 1 s) 111: ?/256 (cycle: 2 s) notes: 1. only 0 can be written, to clear the flag. 2. when ovf is polled with the interval timer interrupt disabled, ovf = 1 must be read at least twice. rev. 2.0, 08/02, page 332 of 788 14.4 operation 14.4.1 watchdog timer mode to use the wdt as a watchdog timer, set the wt/ ,7 bit and the tme bit in tcsr to 1. while the wdt is used as a watchdog timer, if tcnt overflows without being rewritten because of a system malfunction or another error, an internal reset or nmi interrupt request is generated. tcnt does not overflow while the system is operating normally. software must prevent tcnt overflows by rewriting the tcnt value (normally be writing h'00) before overflows occurs. if the rst/ 10, bit of tcsr is set to 1, when the tcnt overflows, an internal reset signal for this lsi is issued for 518 system clocks, and the low level signal is simultaneously output from the 5(62 pin for 132 states, as shown in figure 14.2. if the rst/ 10, bit is cleared to 0, when the tcnt overflows, an nmi interrupt request is generated. here, the output from the 5(62 pin remains high. an internal reset request from the watchdog timer and a reset input from the 5(6 pin are processed in the same vector. reset source can be identified by the xrst bit status in syscr. if a reset caused by a signal input to the 5(6 pin occurs at the same time as a reset caused by a wdt overflow, the 5(6 pin reset has priority and the xrst bit in syscr is set to 1. an nmi interrupt request from the watchdog timer and an interrupt request from the nmi pin are processed in the same vector. do not handle an nmi interrupt request from the watchdog timer and an interrupt request from the nmi pin at the same time. rev. 2.0, 08/02, page 333 of 788 tcnt value h'00 time h'ff wt/ = 1 tme = 1 write h'00 to tcnt wt/ = 1 tme = 1 write h'00 to tcnt 518 system clocks internal reset signal wt/ tme ovf overflow ovf = 1 * : timer mode select bit : timer enable bit : overflow flag note: * after the ovf bit becomes 1, it is cleared to 0 by an internal reset. the xrst bit is also cleared to 0. signal 132 system clocks and internal reset signals generated figure 14.2 watchdog timer mode (rst/ 10, 10, 10, 10, = 1) operation rev. 2.0, 08/02, page 334 of 788 14.4.2 interval timer mode when the wdt is used as an interval timer, an interval timer interrupt (wovi) is generated each time the tcnt overflows, as shown in figure 14.3. therefore, an interrupt can be generated at intervals. when the tcnt overflows in interval timer mode, an interval timer interrupt (wovi) is requested at the same time the ovf bit of tcsr is set to 1. the timing is shown figure 14.4. tcnt value h'00 time h'ff wt/ = 0 tme = 1 wovi overflow overflow overflow overflow wovi : internal timer interrupt request occurrence wovi wovi wovi figure 14.3 interval timer mode operation ? tcnt h'ff h'00 overflow signal (internal signal) ovf figure 14.4 ovf flag set timing rev. 2.0, 08/02, page 335 of 788 14.4.3 5(62 5(62 5(62 5(62 signal output timing when tcnt overflows in watchdog timer mode, the ovf bit in tcsr is set to 1. when the rst/ 10, bit is 1 here, the internal reset signal is generated for the entire lsi. at the same time, the low level signal is output from the 5(62 pin. the timing is shown in figure 14.5. ? tcnt h'ff h'00 132 states 518 states overflow signal (internal signal) ovf signal internal reset signal figure 14.5 output timing of 5(62 5(62 5(62 5(62 signal 14.5 interrupt sources during interval timer mode operation, an overflow generates an interval timer interrupt (wovi). the interval timer interrupt is requested whenever the ovf flag is set to 1 in tcsr. ovf must be cleared to 0 in the interrupt handling routine. when the nmi interrupt request is selected in watchdog timer mode, an nmi interrupt request is generated by an overflow. table 14.2 wdt interrupt source name interrupt source interrupt flag dtc activation wovi tcnt overflow ovf not possible rev. 2.0, 08/02, page 336 of 788 14.6 usage notes 14.6.1 notes on register access the watchdog timers registers, tcnt and tcsr differ from other registers in being more difficult to write to. the procedures for writing to and reading from these registers are given below. writing to tcnt and tcsr (example of wdt_0): these registers must be written to by a word transfer instruction. they cannot be written to by a byte transfer instruction. tcnt and tcsr both have the same write address. therefore, satisfy the relative condition shown in figure 14.6 to write to tcnt or tcsr. to write to tcnt, the upper bytes must contain the value h5a and the lower bytes must contain the write data before the transfer instruction execution. to write to tcsr, the upper bytes must contain the value ha5 and the lower bytes must contain the write data. rev. 2.0, 08/02, page 337 of 788 14.6.2 conflict between timer counter (tcnt) write and increment if a timer counter clock pulse is generated during the t2 state of a tcnt write cycle, the write takes priority and the timer counter is not incremented. figure 14.7 shows this operation. address ? internal write signal tcnt input clock tcnt nm t 1 t 2 tcnt write cycle counter write data figure 14.7 conflict between tcnt write and increment 14.6.3 changing values of cks2 to cks0 bits if bits cks2 to cks0 in tcsr are written to while the wdt is operating, errors could occur in the incrementation. software must stop the watchdog timer (by clearing the tme bit to 0) before changing the values of bits cks2 to cks0. 14.6.4 switching between watchdog timer mode and interval timer mode if the mode is switched from watchdog timer to interval timer, while the wdt is operating, errors could occur in the incrementation. software must stop the watchdog timer (by clearing the tme bit to 0) before switching the mode. rev. 2.0, 08/02, page 338 of 788 14.6.5 system reset by 5(62 5(62 5(62 5(62 signal inputting the 5(62 output signal to the 5(62 pin of this lsi prevents the lsi from being initialized correctly; the 5(62 signal must not be logically connected to the 5(6 pin of the lsi. to reset the entire system by the 5(62 signal, use the circuit as shown in figure 14.8. this lsi figure 14.8 sample circuit for resetting system by 5(62 5(62 5(62 5(62 signal 14.6.6 counter values during transitions between high-speed, sub-active, and watch modes when wdt_1 is used as a clock counter and is allowed to transit between high-speed mode and sub-active or watch mode, the counter does not display the correct value due to internal clock switching. specifically, when transiting from high-speed mode to sub-active or watch mode, that is, when the control clock for wdt_1 switches from the main clock to the sub-clock, the counter incrementing timing is delayed for approximately two to three clock cycles. similarly, when transiting from sub-active or watch mode to high-speed mode, the clock is not supplied until stabilized internal oscillation is available because the main clock oscillator is halted in sub-clock mode. the counter is therefore prevented from incrementing for the time specified by the sts2 to sts0 bits in sbycr after internal oscillation starts, thus producing counter value differences for this time. special care must be taken when using wdt_1 as a clock counter. note that no counter value difference is produced while operated in the same mode. rev. 2.0, 08/02, page 339 of 788 section 15 serial communication interface (sci and irda) this lsi has three independent serial communication interface (sci) channels. the sci can handle both asynchronous and clocked synchronous serial communication. asynchronous serial data communication can be carried out with standard asynchronous communication chips such as a universal asynchronous receiver/transmitter (uart) or asynchronous communication interface adapter (acia). a function is also provided for serial communication between processors (multiprocessor communication function) in asynchronous mode. sci_2 can handle communication using the waveform based on the infrared data association (irda) standard version 1.0. 15.1 features choice of asynchronous or clocked synchronous serial communication mode full-duplex communication capability the transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. the on-chip baud rate generator allows any bit rate to be selected an external clock can be selected as a transfer clock source. choice of lsb-first or msb-first transfer (except in the case of asynchronous mode 7-bit data) four interrupt sources four interrupt sources transmit-end, transmit-data-empty, receive-data-full, and receive error that can issue requests. the transmit-data-empty and receive-data-full interrupt sources can activate the dtc. asynchronous mode: data length: 7 or 8 bits stop bit length: 1 or 2 bits parity: even, odd, or none receive error detection: parity, overrun, and framing errors break detection: break can be detected by reading the rxd pin level directly in case of a framing error sci0022b_000020020700 rev. 2.0, 08/02, page 340 of 788 clocked synchronous mode: data length: 8 bits receive error detection: overrun errors serial data communication with other lsis that have the clock synchronized communication function a block diagram of the sci is shown in figure 15.1. rxd txd sck clock ? ?/4 ?/16 ?/64 tei txi rxi eri scmr ssr scr smr transmission/ reception control baud rate generator brr module data bus rdr tsr rsr parity generation parity check legend rsr : receive shift register rdr : receive data register tsr : transmit shift register tdr : transmit data register smr : serial mode register tdr bus interface internal data bus external clock scr : serial control register ssr : serial status register scmr : smart card mode register brr : bit rate register figure 15.1 block diagram of sci rev. 2.0, 08/02, page 341 of 788 15.2 input/output pins table 15.1 shows the input/output pins for each sci channel. table 15.1 pin configuration channel symbol * input/output function sck0 input/output channel 0 clock input/output rxd0 input channel 0 receive data input 0 txd0 output channel 0 transmit data output sck1 input/output channel 1 clock input/output rxd1 input channel 1 receive data input 1 txd1 output channel 1 transmit data output sck2 input/output channel 2 clock input/output rxd2/irrxd input channel 2 receive data input (normal/irda) 2 txd2/irtxd output channel 2 transmit data output (normal/irda) note: * pin names sck, rxd, and txd are used in the text for all channels, omitting the channel designation. 15.3 register descriptions the sci has the following registers for each channel. receive shift register (rsr) receive data register (rdr) transmit data register (tdr) transmit shift register (tsr) serial mode register (smr) serial control register (scr) serial status register (ssr) serial interface mode register (scmr) bit rate register (brr) keyboard comparator control register (kbcomp) rev. 2.0, 08/02, page 342 of 788 15.3.1 receive shift register (rsr) rsr is a shift register used to receive serial data that converts it into parallel data. when one frame of data has been received, it is transferred to rdr automatically. rsr cannot be directly accessed by the cpu. 15.3.2 receive data register (rdr) rdr is an 8-bit register that stores receive data. when the sci has received one frame of serial data, it transfers the received serial data from rsr to rdr where it is stored. after this, rsr can receive the next data. since rsr and rdr function as a double buffer in this way, continuous receive operations can be performed. after confirming that the rdrf bit in ssr is set to 1, read rdr for only once. rdr cannot be written to by the cpu. rdr is initialized to h00. 15.3.3 transmit data register (tdr) tdr is an 8-bit register that stores transmit data. when the sci detects that tsr is empty, it transfers the transmit data written in tdr to tsr and starts transmission. the double-buffered structures of tdr and tsr enables continuous serial transmission. if the next transmit data has already been written to tdr when one frame of data is transmitted, the sci transfers the written data to tsr to continue transmission. although tdr can be read from or written to by the cpu at all times, to achieve reliable serial transmission, write transmit data to tdr for only once after confirming that the tdre bit in ssr is set to 1. tdr is initialized to hff. 15.3.4 transmit shift register (tsr) tsr is a shift register that transmits serial data. to perform serial data transmission, the sci first transfers transmit data from tdr to tsr, then sends the data to the txd pin. tsr cannot be directly accessed by the cpu. rev. 2.0, 08/02, page 343 of 788 15.3.5 serial mode register (smr) smr is used to set the scis serial transfer format and select the on-chip baud rate generator clock source. bit bit name initial value r/w description 7c/ $ 0 r/w communication mode 0: asynchronous mode 1: clocked synchronous mode 6 chr 0 r/w character length (enabled only in asynchronous mode) 0: selects 8 bits as the data length. 1: selects 7 bits as the data length. lsb-first is fixed and the msb of tdr is not transmitted in transmission. in clocked synchronous mode, a fixed data length of 8 bits is used. 5 pe 0 r/w parity enable (enabled only in asynchronous mode) when this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. for a multiprocessor format, parity bit addition and checking are not performed regardless of the pe bit setting. 4o/ ( 0 r/w parity mode (enabled only when the pe bit is 1 in asynchronous mode) 0: selects even parity. 1: selects odd parity. rev. 2.0, 08/02, page 344 of 788 bit bit name initial value r/w description 3 stop 0 r/w stop bit length (enabled only in asynchronous mode) selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits in reception, only the first stop bit is checked. if the second stop bit is 0, it is treated as the start bit of the next transmit frame. 2 mp 0 r/w multiprocessor mode (enabled only in asynchronous mode) when this bit is set to 1, the multiprocessor communication function is enabled. the pe bit and o/ ( bit settings are invalid in multiprocessor mode. 1 0 cks1 cks0 0 0 r/w r/w clock select 1,0 these bits select the clock source for the on-chip baud rate generator. 00: ? clock (n = 0) 01: ?/4 clock (n = 1) 10: ?/16 clock (n = 2) 11: ?/64 clock (n = 3) for the relation between the bit rate register setting and the baud rate, see section 15.3.9, bit rate register (brr). n is the decimal display of the value of n in brr. rev. 2.0, 08/02, page 345 of 788 15.3.6 serial control register (scr) scr is a register that performs enabling or disabling of sci transfer operations and interrupt requests, and selection of the transfer clock source. for details on interrupt requests, refer to section 15.8, interrupt sources. bit bit name initial value r/w description 7 tie 0 r/w transmit interrupt enable when this bit is set to 1, a txi interrupt request is enabled. 6 rie 0 r/w receive interrupt enable when this bit is set to 1, rxi and eri interrupt requests are enabled. 5 te 0 r/w transmit enable when this bit is set to 1, transmission is enabled. 4 re 0 r/w receive enable when this bit is set to 1, reception is enabled. 3 mpie 0 r/w multiprocessor interrupt enable (enabled only when the mp bit in smr is 1 in asynchronous mode) when this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the rdrf, fer, and orer status flags in ssr is disabled. on receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. for details, refer to section 15.5, multiprocessor communication function. 2 teie 0 r/w transmit end interrupt enable when this bit is set to 1, a tei interrupt request is enabled. rev. 2.0, 08/02, page 346 of 788 bit bit name initial value r/w description 1 0 cke1 cke0 0 0 r/w r/w clock enable 1, 0 these bits select the clock source and sck pin function. asynchronous mode 00: internal clock (sck pin functions as i/o port.) 01: internal clock (outputs a clock of the same frequency as the bit rate from the sck pin.) 1x: external clock (inputs a clock with a frequency 16 times the bit rate from the sck pin.) clocked synchronous mode 0x: internal clock (sck pin functions as clock output.) 1x: external clock (sck pin functions as clock input.) legend x: dont care rev. 2.0, 08/02, page 347 of 788 15.3.7 serial status register (ssr) ssr is a register containing status flags of the sci and multiprocessor bits for transfer. tdre, rdrf, orer, per, and fer can only be cleared. bit bit name initial value r/w description 7 tdre 1 r/(w) * transmit data register empty indicates whether tdr contains transmit data. [setting conditions] when the te bit in scr is 0 when data is transferred from tdr to tsr and tdr is ready for data write [clearing conditions] when 0 is written to tdre after reading tdre = 1 when a txi interrupt request is issued allowing the dtc to write data to tdr 6 rdrf 0 r/(w) * receive data register full indicates that receive data is stored in rdr. [setting condition] when serial reception ends normally and receive data is transferred from rsr to rdr [clearing conditions] when 0 is written to rdrf after reading rdrf = 1 when an rxi interrupt request is issued allowing the dtc to read data from rdr the rdrf flag is not affected and retains its previous value when the re bit in scr is cleared to 0. 5 orer 0 r/(w) * overrun error [setting condition] when the next data is received while rdrf = 1 [clearing condition] when 0 is written to orer after reading orer = 1 rev. 2.0, 08/02, page 348 of 788 bit bit name initial value r/w description 4fer 0 r/(w) * framing error [setting condition] when the stop bit is 0 [clearing condition] when 0 is written to fer after reading fer = 1 in 2-stop-bit mode, only the first stop bit is checked. 3 per 0 r/(w) * parity error [setting condition] when a parity error is detected during reception [clearing condition] when 0 is written to per after reading per = 1 2 tend 1 r transmit end [setting conditions] when the te bit in scr is 0 when tdre = 1 at transmission of the last bit of a 1-byte serial transmit character [clearing conditions] when 0 is written to tdre after reading tdre = 1 when a txi interrupt request is issued allowing the dtc to write data to tdr 1 mpb 0 r multiprocessor bit mpb stores the multiprocessor bit in the receive frame. when the re bit in scr is cleared to 0 its previous state is retained. 0 mpbt 0 r/w multiprocessor bit transfer mpbt stores the multiprocessor bit to be added to the transmit frame. note: * only 0 can be written, to clear the flag. rev. 2.0, 08/02, page 349 of 788 15.3.8 serial interface mode register (scmr) scmr selects sci functions and its format. bit bit name initial value r/w description 7 to 4 all 1 r reserved these bits are always read as 1 and cannot be modified. 3 sdir 0 r/w data transfer direction selects the serial/parallel conversion format. 0: tdr contents are transmitted with lsb-first. receive data is stored as lsb first in rdr. 1: tdr contents are transmitted with msb-first. receive data is stored as msb first in rdr. the sdir bit is valid only when the 8-bit data format is used for transmission/reception; when the 7-bit data format is used, data is always transmitted/received with lsb-first. 2 sinv 0 r/w data invert specifies inversion of the data logic level. the sinv bit does not affect the logic level of the parity bit. when the parity bit is inverted, invert the o/ ( bit in smr. 0: tdr contents are transmitted as they are. receive data is stored as it is in rdr. 1: tdr contents are inverted before being transmitted. receive data is stored in inverted form in rdr. 1 1 r reserved this bit is always read as 1 and cannot be modified. 0 smif 0 r/w serial communication interface mode select: 0: normal asynchronous or clocked synchronous mode 1: reserved mode rev. 2.0, 08/02, page 350 of 788 15.3.9 bit rate register (brr) brr is an 8-bit register that adjusts the bit rate. as the sci performs baud rate generator control independently for each channel, different bit rates can be set for each channel. table 15.2 shows the relationships between the n setting in brr and bit rate b for normal asynchronous mode and clocked synchronous mode. the initial value of brr is h'ff, and it can be read from or written to by the cpu at all times. table 15.2 relationships between n setting in brr and bit rate b mode bit rate error asynchronous mode b = 64 2 (n+1) 2n-1 ? 10 6 error (%) = { b 64 2 (n+1) 2n-1 ? 10 6 - 1 } 100 clocked synchronous mode b = 64 2 (n+1) 2n-1 ? 10 6 legend b: bit rate (bit/s) n: brr setting for baud rate generator (0 n 255) ?: operating frequency (mhz) n: determined by the smr settings shown in the following table. smr setting cks1 cks0 n 000 011 102 113 table 15.3 shows sample n settings in brr in normal asynchronous mode. table 15.4 shows the maximum bit rate settable for each frequency. table 15.6 shows sample n settings in brr in clocked synchronous mode. tables 15.5 and 15.7 show the maximum bit rates with external clock input. rev. 2.0, 08/02, page 351 of 788 table 15.3 brr settings for various bit rates (asynchronous mode) operating frequency ? (mhz) 2 2.097152 2.4576 3 bit rate (bit/s) nn error (%) n n error (%) n n error (%) n n error (%) 110 1 141 0.03 1 148 C0.04 1 174 C0.26 1 212 0.03 150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16 300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16 600 0 103 0.16 0 108 0.21 0 127 0.00 0 155 0.16 1200 0 51 0.16 0 54 C0.70 0 63 0.00 0 77 0.16 2400 0 25 0.16 0 26 1.14 0 31 0.00 0 38 0.16 4800 0 12 0.16 0 13 C2.48 0 15 0.00 0 19 C2.34 9600 0 6 C2.48 0 7 0.00 0 9 C2.34 19200 0 3 0.00 0 4 C2.34 31250 0 1 0.00 0 2 0.00 38400 0 1 0.00 operating frequency ? (mhz) 3.6864 4 4.9152 5 bit rate (bit/s) nn error (%) n n error (%) n n error (%) n n error (%) 110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 C0.25 150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16 1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 2400 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16 4800 0 23 0.00 0 25 0.16 0 31 0.00 0 32 C1.36 9600 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73 19200 0 5 0.00 0 7 0.00 0 7 1.73 31250 0 3 0.00 0 4 C1.70 0 4 0.00 38400 0 2 0.00 0 3 0.00 0 3 1.73 legend : can be set, but there will be a degree of error. note: * make the settings so that the error does not exceed 1%. rev. 2.0, 08/02, page 352 of 788 operating frequency ? (mhz) 6 6.144 7.3728 8 bit rate (bit/s) nn error (%) n n error (%) n n error (%) n n error (%) 110 2 106 C0.44 2 108 0.08 2 130 C0.07 2 141 0.03 150 2 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16 300 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16 600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16 1200 0 155 0.16 0 159 0.00 0 191 0.00 0 207 0.16 2400 0 77 0.16 0 79 0.00 0 95 0.00 0 103 0.16 4800 0 38 0.16 0 39 0.00 0 47 0.00 0 51 0.16 9600 0 19 C2.34 0 19 0.00 0 23 0.00 0 25 0.16 19200 0 9 C2.34 0 9 0.00 0 11 0.00 0 12 0.16 31250 0 5 0.00 0 5 2.40 0 7 0.00 38400 0 4 C2.34 0 4 0.00 0 5 0.00 operating frequency ? (mhz) 9.8304 10 12 12.288 bit rate (bit/s) nn error (%) n n error (%) n n error (%) n n error (%) 110 2 174 C0.26 2 177 C0.25 2 212 0.03 2 217 0.08 150 2 127 0.00 2 129 0.16 2 155 0.16 2 159 0.00 300 1 255 0.00 2 64 0.16 2 77 0.16 2 79 0.00 600 1 127 0.00 1 129 0.16 1 155 0.16 1 159 0.00 1200 0 255 0.00 1 64 0.16 1 77 0.16 1 79 0.00 2400 0 127 0.00 0 129 0.16 0 155 0.16 0 159 0.00 4800 0 63 0.00 0 64 0.16 0 77 0.16 0 79 0.00 9600 0 31 0.00 0 32 C1.36 0 38 0.16 0 39 0.00 19200 0 15 0.00 0 15 1.73 0 19 C2.34 0 19 0.00 31250 0 9 C1.70 0 9 0.00 0 11 0.00 0 11 2.40 38400 0 7 0.00 0 7 1.73 0 9 C2.34 0 9 0.00 legend : can be set, but there will be a degree of error. note: * make the settings so that the error does not exceed 1%. rev. 2.0, 08/02, page 353 of 788 operating frequency ? (mhz) 14 14.7456 16 17.2032 bit rate (bit/s) nn error (%) n n error (%) n n error (%) n n error (%) 110 2 248 C0.17 3 64 0.70 3 70 0.03 3 75 0.48 150 2 181 0.16 2 191 0.00 2 207 0.16 2 223 0.00 300 2 90 0.16 2 95 0.00 2 103 0.16 2 111 0.00 600 1 181 0.16 1 191 0.00 1 207 0.16 1 223 0.00 1200 1 90 0.16 1 95 0.00 1 103 0.16 1 111 0.00 2400 0 181 0.16 0 191 0.00 0 207 0.16 0 223 0.00 4800 0 90 0.16 0 95 0.00 0 103 0.16 0 111 0.00 9600 0 45 C0.93 0 47 0.00 0 51 0.16 0 55 0.00 19200 0 22 C0.93 0 23 0.00 0 25 0.16 0 27 0.00 31250 0 13 0.00 0 14 C1.70 0 15 0.00 0 16 1.20 38400 0 11 0.00 0 12 0.16 0 16 0.00 operating frequency ? (mhz) 18 19.6608 20 bit rate (bit/s) nn error (%) n n error (%) n n error (%) 110 3 79 C0.12 3 86 0.31 3 88 C0.25 150 2 233 0.16 2 255 0.00 3 64 0.16 300 2 116 0.16 2 127 0.00 2 129 0.16 600 1 233 0.16 1 255 0.00 2 64 0.16 1200 1 166 0.16 1 127 0.00 1 129 0.16 2400 0 233 0.16 0 255 0.00 1 64 0.16 4800 0 166 0.16 0 127 0.00 0 129 0.16 9600 0 58 C0.69 0 63 0.00 0 64 0.16 19200 0 28 1.02 0 31 0.00 0 32 C1.36 31250 0 17 0.00 0 19 C1.70 0 19 0.00 38400 0 14 C2.34 0 15 0.00 0 15 1.73 legend : can be set, but there will be a degree of error. note: * make the settings so that the error does not exceed 1%. rev. 2.0, 08/02, page 354 of 788 table 15.4 maximum bit rate for each frequency (asynchronous mode) ? (mhz) maximum bit rate (bit/s) n n ? (mhz) maximum bit rate (bit/s) n n 2 62500 0 0 9.8304 307200 0 0 2.097152 65536 0 0 10 312500 0 0 2.4576 76800 0 0 12 375000 0 0 3 93750 0 0 12.288 384000 0 0 3.6864 115200 0 0 14 437500 0 0 4 125000 0 0 14.7456 460800 0 0 4.9152 153600 0 0 16 500000 0 0 5 156250 0 0 17.2032 537600 0 0 6 187500 0 0 18 562500 0 0 6.144 192000 0 0 19.6608 614400 0 0 7.3728 230400 0 0 20 625000 0 0 8 250000 0 0 table 15.5 maximum bit rate with external clock input (asynchronous mode) ? (mhz) external input clock (mhz) maximum bit rate (bit/s) ? (mhz) external input clock (mhz) maximum bit rate (bit/s) 2 0.5000 31250 9.8304 2.4576 153600 2.097152 0.5243 32768 10 2.5000 156250 2.4576 0.6144 38400 12 3.0000 187500 3 0.7500 46875 12.288 3.0720 192000 3.6864 0.9216 57600 14 3.5000 218750 4 1.0000 62500 14.7456 3.6864 230400 4.9152 1.2288 76800 16 4.0000 250000 5 1.2500 78125 17.2032 4.3008 268800 6 15.000 93750 18 4.5000 281250 6.144 1.5360 96000 19.6608 4.9152 307200 7.3728 1.8432 115200 20 5.0000 312500 8 2.0000 125000 rev. 2.0, 08/02, page 355 of 788 table 15.6 brr settings for various bit rates (clocked synchronous mode) operating frequency ? (mhz) 2 4 8 10 16 20 bit rate (bit/s)n nn nn nn nn nn n 110 3 70 250 2 124 2 249 3 124 3 249 500 1 249 2 124 2 249 3 124 1k 1 124 1 249 2 124 2 249 2.5k 0 199 1 99 1 199 1 249 2 99 2 124 5k 0 99 0 199 1 99 1 124 1 199 1 249 10k 0 49 0 99 0 199 0 249 1 99 1 124 25k 0 19 0 39 0 79 0 99 0 159 0 199 50k 0 9 0 19 0 39 0 49 0 79 0 99 100k 0 4 0 9 0 19 0 24 0 39 0 49 250k 0 1 0 3 0 7 0 9 0 15 0 19 500k 0 0 * 01 * 03040709 1m 0001 0304 2.5m 0 0 * 01 5m 0 0 * legend blank: cannot be set. : can be set, but there will be a degree of error. * : continuous transfer or reception is not possible. table 15.7 maximum bit rate with external clock input (clocked synchronous mode) ? (mhz) external input clock (mhz) maximum bit rate (bit/s) ? (mhz) external input clock (mhz) maximum bit rate (bit/s) 2 0.3333 333333.3 12 2.0000 2000000.0 4 0.6667 666666.7 14 2.3333 2333333.3 6 1.0000 1000000.0 16 2.6667 2666666.7 8 1.3333 1333333.3 18 3.0000 3000000.0 10 1.6667 1666666.7 20 3.3333 3333333.3 rev. 2.0, 08/02, page 356 of 788 15.3.10 keyboard comparator control register (kbcomp) kbcomp selects the functions of the sci and a/d converter. bit bit name initial value r/w description 7 ire 0 r/w irda enable specifies sci_2 i/o pins for either normal sci or irda. 0: txd2/irtxd and rxd2/irrxd pins function as txd2 and rxd2 pins, respectively 1: txd2/irtxd and rxd2/irrxd pins function as irtxd and irrxd pins, respectively 6 5 4 ircks2 ircks1 ircks0 0 0 0 r/w r/w r/w irda clock select 2 to 0 these bits specify the high-level width of the clock pulse during irtxd output pulse encoding when the irda function is enabled. 000: b 3/16 (b: bit rate) 001: ?/2 010: ? /4 011: ? /8 100: ? /16 101: ? /32 110: ? /64 111: ? /128 3 2 1 0 kbade kbch2 kbch1 kbch0 0 0 0 0 r/w r/w r/w r/w bits related to the a/d converter for details, refer to section 21.3.4, keyboard comparator control register (kbcomp). rev. 2.0, 08/02, page 357 of 788 15.4 operation in asynchronous mode figure 15.2 shows the general format for asynchronous serial communication. one frame consists of a start bit (low level), followed by transmit/receive data, a parity bit, and finally stop bits (high level). in asynchronous serial communication, the transmission line is usually held in the mark state (high level). the sci monitors the transmission line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. inside the sci, the transmitter and receiver are independent units, enabling full-duplex communication. both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer and reception. lsb start bit msb idle state (mark state) stop bit 0 transmit/receive data d0 d1 d2 d3 d4 d5 d6 d7 0/1 1 1 1 1 serial data parity bit 1 bit 1 or 2 bits 7 or 8 bits 1 bit or none one unit of transfer data (character or frame) figure 15.2 data format in asynchronous communication (example with 8-bit data, parity, two stop bits) 15.4.1 data transfer format table 15.8 shows the data transfer formats that can be used in asynchronous mode. any of 12 transfer formats can be selected according to the smr setting. for details on the multiprocessor bit, refer to section 15.5, multiprocessor communication function. rev. 2.0, 08/02, page 358 of 788 table 15.8 serial transfer formats (asynchronous mode) pe 0 0 1 1 0 0 1 1 s 8-bit data stop s 7-bit data stop s 8-bit data stop stop s 8-bit data p stop s 7-bit data stop p s 8-bit data mpb stop s 8-bit data mpb stop stop s 7-bit data stop mpb s 7-bit data stop mpb stop s 7-bit data stop stop chr 0 0 0 0 1 1 1 1 0 0 1 1 mp 0 0 0 0 0 0 0 0 1 1 1 1 stop 0 1 0 1 0 1 0 1 0 1 0 1 smr settings 123456789101112 serial transmit/receive format and frame length stop s 8-bit data p stop s 7-bit data stop p stop rev. 2.0, 08/02, page 359 of 788 15.4.2 receive data sampling timing and reception margin in asynchronous mode in asynchronous mode, the sci operates on a basic clock with a frequency of 16 times the bit rate. in reception, the sci samples the falling edge of the start bit using the basic clock, and performs internal synchronization. since receive data is latched internally at the rising edge of the 8th pulse of the basic clock, data is latched at the middle of each bit, as shown in figure 15.3. thus the reception margin in asynchronous mode is determined by formula (1) below. m = (0.5 C ) C (1 + f) C (l C 0.5) f } 100 [%] ... formula (1) 2n 1 n d C 0.5 m: reception margin (%) n : ratio of bit rate to clock (n = 16) d : clock duty (d = 0.5 to 1.0) l : frame length (l = 9 to 12) f : absolute value of clock rate deviation } assuming values of f = 0 and d = 0.5 in formula (1), the reception margin is determined by the formula below. m = {0.5 C 1/(2 16)} 100 [%] = 46.875 % however, this is only the computed value, and a margin of 20% to 30% should be allowed in system design. internal basic clock 16 clocks 8 clocks receive data (rxd) synchronization sampling timing start bit d0 d1 data sampling timing 15 0 7 15 0 07 figure 15.3 receive data sampling timing in asynchronous mode rev. 2.0, 08/02, page 360 of 788 15.4.3 clock either an internal clock generated by the on-chip baud rate generator or an external clock input at the sck pin can be selected as the scis transfer clock, according to the setting of the c/ $ bit in smr and the cke1 and cke0 bits in scr. when an external clock is input at the sck pin, the clock frequency should be 16 times the bit rate used. when the sci is operated on an internal clock, the clock can be output from the sck pin. the frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 15.4. 0 1 frame d0 d1 d2 d3 d4 d5 d6 d7 0/1 1 1 sck txd figure 15.4 relation between output clock and transmit data phase (asynchronous mode) rev. 2.0, 08/02, page 361 of 788 15.4.4 sci initialization (asynchronous mode) before transmitting and receiving data, you should first clear the te and re bits in scr to 0, then initialize the sci as shown in figure 15.5. when the operating mode, transfer format, etc., is changed, the te and re bits must be cleared to 0 before making the change using the following procedure. when the te bit is cleared to 0, the tdre flag in ssr is set to 1. note that clearing the re bit to 0 does not initialize the contents of the rdrf, per, fer, and orer flags in ssr, or the contents of rdr. when an external clock is used in asynchronous mode, the clock must be supplied even during initialization. wait rev. 2.0, 08/02, page 362 of 788 15.4.5 data transmission (asynchronous mode) figure 15.6 shows an example of the operation for transmission in asynchronous mode. in transmission, the sci operates as described below. 1. the sci monitors the tdre flag in ssr, and if it is cleared to 0, recognizes that data has been written to tdr, and transfers the data from tdr to tsr. 2. after transferring data from tdr to tsr, the sci sets the tdre flag to 1 and starts transmission. if the tie bit in scr is set to 1 at this time, a transmit data empty interrupt request (txi) is generated. because the txi interrupt routine writes the next transmit data to tdr before transmission of the current transmit data has finished, continuous transmission can be enabled. 3. data is sent from the txd pin in the following order: start bit, transmit data, parity bit or multiprocessor bit (may be omitted depending on the format), and stop bit. 4. the sci checks the tdre flag at the timing for sending the stop bit. 5. if the tdre flag is 0, the data is transferred from tdr to tsr, the stop bit is sent, and then serial transmission of the next frame is started. 6. if the tdre flag is 1, the tend flag in ssr is set to 1, the stop bit is sent, and then the mark state is entered in which 1 is output. if the teie bit in scr is set to 1 at this time, a tei interrupt request is generated. figure 15.7 shows a sample flowchart for transmission in asynchronous mode. tdre tend 0 1 frame d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 1 1 1 data start bit parity bit stop bit start bit data parity bit stop bit txi interrupt request generated data written to tdr and tdre flag cleared to 0 in txi interrupt handling routine tei interrupt request generated idle state (mark state) txi interrupt request generated figure 15.6 example of sci transmit operation in asynchronous mode (example with 8- bit data, parity, one stop bit) rev. 2.0, 08/02, page 363 of 788 no rev. 2.0, 08/02, page 364 of 788 15.4.6 serial data reception (asynchronous mode) figure 15.8 shows an example of the operation for reception in asynchronous mode. in serial reception, the sci operates as described below. 1. the sci monitors the communication line, and if a start bit is detected, performs internal synchronization, receives receive data in rsr, and checks the parity bit and stop bit. 2. if an overrun error (when reception of the next data is completed while the rdrf flag in ssr is still set to 1) occurs, the orer bit in ssr is set to 1. if the rie bit in scr is set to 1 at this time, an eri interrupt request is generated. receive data is not transferred to rdr. the rdrf flag remains to be set to 1. 3. if a parity error is detected, the per bit in ssr is set to 1 and receive data is transferred to rdr. if the rie bit in scr is set to 1 at this time, an eri interrupt request is generated. 4. if a framing error (when the stop bit is 0) is detected, the fer bit in ssr is set to 1 and receive data is transferred to rdr. if the rie bit in scr is set to 1 at this time, an eri interrupt request is generated. 5. if reception finishes successfully, the rdrf bit in ssr is set to 1, and receive data is transferred to rdr. if the rie bit in scr is set to 1 at this time, an rxi interrupt request is generated. because the rxi interrupt routine reads the receive data transferred to rdr before reception of the next receive data has finished, continuous reception can be enabled. rdrf fer 0 1 frame d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 0 1 1 data start bit parity bit stop bit start bit data parity bit stop bit eri interrupt request generated by framing error idle state (mark state) rdr data read and rdrf flag cleared to 0 in rxi interrupt handling routine rxi interrupt request generated figure 15.8 example of sci receive operation in asynchronous mode (example with 8-bit data, parity, one stop bit) rev. 2.0, 08/02, page 365 of 788 table 15.9 shows the states of the ssr status flags and receive data handling when a receive error is detected. if a receive error is detected, the rdrf flag retains its state before receiving data. reception cannot be resumed while a receive error flag is set to 1. accordingly, clear the orer, fer, per, and rdrf bits to 0 before resuming reception. figure 15.9 shows a sample flow chart for serial data reception. table 15.9 ssr status flags and receive data handling ssr status flag rdrf * orer fer per receive data receive error type 1 1 0 0 lost overrun error 0 0 1 0 transferred to rdr framing error 0 0 0 1 transferred to rdr parity error 1 1 1 0 lost overrun error + framing error 1 1 0 1 lost overrun error + parity error 0 0 1 1 transferred to rdr framing error + parity error 1 1 1 1 lost overrun error + framing error + parity error note: * the rdrf flag retains the state it had before data reception. rev. 2.0, 08/02, page 366 of 788 yes rev. 2.0, 08/02, page 367 of 788 rev. 2.0, 08/02, page 368 of 788 15.5 multiprocessor communication function use of the multiprocessor communication function enables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. when multiprocessor communication is carried out, each receiving station is addressed by a unique id code. the serial communication cycle consists of two component cycles: an id transmission cycle which specifies the receiving station, and a data transmission cycle for the specified receiving station. the multiprocessor bit is used to differentiate between the id transmission cycle and the data transmission cycle. if the multiprocessor bit is 1, the cycle is an id transmission cycle, and if the multiprocessor bit is 0, the cycle is a data transmission cycle. figure 15.10 shows an example of inter-processor communication using the multiprocessor format. the transmitting station first sends the id code of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. it then sends transmit data as data with a 0 multiprocessor bit added. the receiving station skips data until data with a 1 multiprocessor bit is sent. when data with a 1 multiprocessor bit is received, the receiving station compares that data with its own id. the station whose id matches then receives the data sent next. stations whose id does not match continue to skip data until data with a 1 multiprocessor bit is again received. the sci uses the mpie bit in scr to implement this function. when the mpie bit is set to 1, transfer of receive data from rsr to rdr, error flag detection, and setting the ssr status flags, rdrf, fer, and orer in ssr to 1 are prohibited until data with a 1 multiprocessor bit is received. on reception of a receive character with a 1 multiprocessor bit, the mpb bit in ssr is set to 1 and the mpie bit is automatically cleared, thus normal reception is resumed. if the rie bit in scr is set to 1 at this time, an rxi interrupt is generated. when the multiprocessor format is selected, the parity bit setting is invalid. all other bit settings are the same as those in normal asynchronous mode. the clock used for multiprocessor communication is the same as that in normal asynchronous mode. rev. 2.0, 08/02, page 369 of 788 transmitting station receiving station a receiving station b receiving station c receiving station d (id = 01) (id = 02) (id = 03) (id = 04) serial communication line serial data id transmission cycle = receiving station specification data transmission cycle = data transmission to receiving station specified by id (mpb = 1) (mpb = 0) h'01 h'aa legend mpb: multiprocessor bit figure 15.10 example of communication using multiprocessor format (transmission of data h'aa to receiving station a) rev. 2.0, 08/02, page 370 of 788 15.5.1 multiprocessor serial data transmission figure 15.11 shows a sample flowchart for multiprocessor serial data transmission. for an id transmission cycle, set the mpbt bit in ssr to 1 before transmission. for a data transmission cycle, clear the mpbt bit in ssr to 0 before transmission. all other sci operations are the same as those in asynchronous mode. no rev. 2.0, 08/02, page 371 of 788 15.5.2 multiprocessor serial data reception figure 15.13 shows a sample flowchart for multiprocessor serial data reception. if the mpie bit in scr is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. on receiving data with a 1 multiprocessor bit, the receive data is transferred to rdr. an rxi interrupt request is generated at this time. all other sci operations are the same as in asynchronous mode. figure 15.12 shows an example of sci operation for multiprocessor format reception. mpie rdr value 0 d0 d1 d7 1 1 0 d0 d1 d7 0 1 1 1 data (id1) start bit mpb stop bit start bit data (data 1) mpb stop bit data (id2) start bit stop bit start bit data (data 2) stop bit rxi interrupt request (multiprocessor interrupt) generated idle state (mark state) rdrf rdr data read and rdrf flag cleared to 0 in rxi interrupt handling routine if not this stations id, mpie bit is set to 1 again rxi interrupt request is not generated, and rdr retains its state id1 (a) data does not match stations id mpie rdr value 0 d0 d1 d7 1 1 0 d0 d1 d7 0 1 1 1 mpb mpb rxi interrupt request (multiprocessor interrupt) generated idle state (mark state) rdrf rdr data read and rdrf flag cleared to 0 in rxi interrupt handling routine matches this stations id, so reception continues, and data is received in rxi interrupt service routine mpie bit set to 1 again id2 (b) data matches stations id data 2 id1 mpie = 0 mpie = 0 figure 15.12 example of sci receive operation (example with 8-bit data, multiprocessor bit, one stop bit) rev. 2.0, 08/02, page 372 of 788 yes rev. 2.0, 08/02, page 373 of 788 rev. 2.0, 08/02, page 374 of 788 15.6 operation in clocked synchronous mode figure 15.14 shows the general format for clocked synchronous communication. in clocked synchronous mode, data is transmitted or received in synchronization with clock pulses. one character in transfer data consists of 8-bit data. in data transmission, the sci outputs data from one falling edge of the synchronization clock to the next. in data reception, the sci receives data in synchronization with the rising edge of the synchronization clock. after 8-bit data is output, the transmission line holds the msb state. in clocked synchronous mode, no parity or multiprocessor bit is added. inside the sci, the transmitter and receiver are independent units, enabling full- duplex communication by use of a common clock. both the transmitter and the receiver also have a double-buffered structure, so that the next transmit data can be written during transmission or the previous receive data can be read during reception, enabling continuous data transfer. dont care dont care one unit of transfer data (character or frame) bit 0 serial data synchronization clock bit 1 bit 3 bit 4 bit 5 lsb msb bit 2 bit 6 bit 7 * * note: * high except in continuous transfer/reception figure 15.14 data format in clocked synchronous communication (lsb-first) 15.6.1 clock either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the sck pin can be selected, according to the setting of the cke1 and cke0 bits in scr. when the sci is operated on an internal clock, the synchronization clock is output from the sck pin. eight synchronization clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. rev. 2.0, 08/02, page 375 of 788 15.6.2 sci initialization (clocked synchronous mode) before transmitting and receiving data, you should first clear the te and re bits in scr to 0, then initialize the sci as described in a sample flowchart in figure 15.15. when the operating mode, transfer format, etc., is changed, the te and re bits must be cleared to 0 before making the change using the following procedure. when the te bit is cleared to 0, the tdre flag in ssr is set to 1. however, clearing the re bit to 0 does not initialize the rdrf, per, fer, and orer flags in ssr, or rdr. wait rev. 2.0, 08/02, page 376 of 788 15.6.3 serial data transmission (clocked synchronous mode) figure 15.16 shows an example of sci operation for transmission in clocked synchronous mode. in serial transmission, the sci operates as described below. 1. the sci monitors the tdre flag in ssr, and if it is 0, recognizes that data has been written to tdr, and transfers the data from tdr to tsr. 2. after transferring data from tdr to tsr, the sci sets the tdre flag to 1 and starts transmission. if the tie bit in scr is set to 1 at this time, a txi interrupt request is generated. because the txi interrupt routine writes the next transmit data to tdr before transmission of the current transmit data has finished, continuous transmission can be enabled. 3. 8-bit data is sent from the txd pin synchronized with the output clock when output clock mode has been specified and synchronized with the input clock when use of an external clock has been specified. 4. the sci checks the tdre flag at the timing for sending the last bit. 5. if the tdre flag is cleared to 0, data is transferred from tdr to tsr, and serial transmission of the next frame is started. 6. if the tdre flag is set to 1, the tend flag in ssr is set to 1, and the txd pin maintains the output state of the last bit. if the teie bit in scr is set to 1 at this time, a tei interrupt request is generated. the sck pin is fixed high. figure 15.17 shows a sample flow chart for serial data transmission. even if the tdre flag is cleared to 0, transmission will not start while a receive error flag (orer, fer, or per) is set to 1. make sure to clear the receive error flags to 0 before starting transmission. note that clearing the re bit to 0 does not clear the receive error flags. transfer direction bit 0 serial data synchronization clock 1 frame tdre tend data written to tdr and tdre flag cleared to 0 in txi interrupt handling routine txi interrupt request generated bit 1 bit 7 bit 0 bit 1 bit 6 bit 7 txi interrupt request generated tei interrupt request generated figure 15.16 example of sci transmit operation in clocked synchronous mode rev. 2.0, 08/02, page 377 of 788 no rev. 2.0, 08/02, page 378 of 788 15.6.4 serial data reception (clocked synchronous mode) figure 15.18 shows an example of sci operation for reception in clocked synchronous mode. in serial reception, the sci operates as described below. 1. the sci performs internal initialization in synchronization with a synchronization clock input or output, starts receiving data, and stores the receive data in rsr. 2. if an overrun error (when reception of the next data is completed while the rdrf flag is still set to 1) occurs, the orer bit in ssr is set to 1. if the rie bit in scr is set to 1 at this time, an eri interrupt request is generated. receive data is not transferred to rdr. the rdrf flag remains to be set to 1. 3. if reception finishes successfully, the rdrf bit in ssr is set to 1, and receive data is transferred to rdr. if the rie bit in scr is set to 1 at this time, an rxi interrupt request is generated. because the rxi interrupt routine reads the receive data transferred to rdr before reception of the next receive data has finished, continuous reception can be enabled. bit 7 serial data synchronization clock 1 frame rdrf orer eri interrupt request generated by overrun error rxi interrupt request generated rdr data read and rdrf flag cleared to 0 in rxi interrupt handling routine rxi interrupt request generated bit 0 bit 7 bit 0 bit 1 bit 6 bit 7 figure 15.18 example of sci receive operation in clocked synchronous mode rev. 2.0, 08/02, page 379 of 788 reception cannot be resumed while a receive error flag is set to 1. accordingly, clear the orer, fer, per, and rdrf bits to 0 before resuming reception. figure 15.19 shows a sample flowchart for serial data reception. yes rev. 2.0, 08/02, page 380 of 788 15.6.5 simultaneous serial data transmission and reception (clocked synchronous mode) figure 15.20 shows a sample flowchart for simultaneous serial transmit and receive operations. after initializing the sci, the following procedure should be used for simultaneous serial data transmit and receive operations. to switch from transmit mode to simultaneous transmit and receive mode, check that the sci has finished transmission and the tdre and tend flags in ssr are set to 1, clear the te bit in scr to 0, and then set the te and re bits to 1 simultaneously with a single instruction. to switch from receive mode to simultaneous transmit and receive mode, check that the sci has finished reception, and clear the re bit to 0. then after checking that the rdrf bit in ssr and receive error flags (orer, fer, and per) are cleared to 0, set the te and re bits to 1 simultaneously with a single instruction. rev. 2.0, 08/02, page 381 of 788 yes rev. 2.0, 08/02, page 382 of 788 15.7 irda operation irda operation can be used with sci_2. figure 15.22 shows an irda block diagram. if the irda function is enabled using the ire bit in kbcomp, the txd2 and rxd2 pins in sci_2 are allowed to encode and decode the waveform based on the irda standard version 1.0 (function as the irtxd and irrxd pins). connecting these pins to the infrared data transceiver achieves infrared data communication based on the system defined by the irda standard version 1.0. in the system defined by the irda standard version 1.0, communication is started at a transfer rate of 9600 bps, which can be modified as required. the irda interface provided by this lsi does not incorporate the capability of automatic modification of the transfer rate; the transfer rate must be modified through programming. irda pulse encoder kbcomp txd2/irtxd rxd2/irrxd sci2 txd rxd pulse decoder figure 15.21 irda block diagram rev. 2.0, 08/02, page 383 of 788 transmission: during transmission, the output signals from the sci (uart frames) are converted to ir frames using the irda interface (see figure 15.22). for serial data of level 0, a high-level pulse having a width of 3/16 of the bit rate (1-bit interval) is output (initial setting). the high-level pulse can be selected using the ircks2 to ircks0 bits in kbcomp. the high-level pulse width is defined to be 1.41 m s at minimum and (3/16 + 2.5%) bit rate or (3/16 bit rate) + 1.08 m s at maximum. for example, when the frequency of system clock ? is 20 mhz, a high-level pulse width of at least 1.4 s to 1.6 s can be specified. for serial data of level 1, no pulses are output. ir frame data 0000 0 11 11 1 transmission reception bit cycle pulse width is 1.6 s to 3/16 bit cycle stop bit start bit uart frame data 0000 0 11 11 1 start bit stop bit figure 15.22 irda transmission and reception reception: during reception, ir frames are converted to uart frames using the irda interface before inputting to sci_2. data of level 0 is output each time a high-level pulse is detected and data of level 1 is output when no pulse is detected in a bit cycle. if a pulse has a high-level width of less than 1.41 m s, the minimum width allowed, the pulse is recognized as level 0. high-level pulse width selection: table 15.10 shows possible settings for bits ircks2 to ircks0 (minimum pulse width), and this lsi's operating frequencies and bit rates, for making the pulse width shorter than 3/16 times the bit rate in transmission. rev. 2.0, 08/02, page 384 of 788 table 15.10 ircks2 to ircks0 bit settings bit rate (bps) (upper row) / bit interval 3/16 (s) (lower row) 2400 9600 19200 38400 57600 115200 operating frequency ? (mhz) 78.13 19.53 9.77 4.88 3.26 1.63 2 010 010 010 010 010 2.097152 010 010 010 010 010 2.4576 010 010 010 010 010 3 011 011 011 011 011 3.6864 011 011 011 011 011 011 4.9152 011 011 011 011 011 011 5 011 011 011 011 011 011 6 100 100 100 100 100 100 6.144 100 100 100 100 100 100 7.3728 100 100 100 100 100 100 8 100 100 100 100 100 100 9.8304 100 100 100 100 100 100 10 100 100 100 100 100 100 12 101 101 101 101 101 101 12.288 101 101 101 101 101 101 14 101 101 101 101 101 101 14.7456 101 101 101 101 101 101 16 101 101 101 101 101 101 16.9344 101 101 101 101 101 101 17.2032 101 101 101 101 101 101 18 101 101 101 101 101 101 19.6608 101 101 101 101 101 101 20 101 101 101 101 101 101 legend : an sci bit rate setting cannot be made. rev. 2.0, 08/02, page 385 of 788 15.8 interrupt sources table 15.11 shows the interrupt sources in serial communication interface. a different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in scr. when the tdre flag in ssr is set to 1, a txi interrupt request is generated. when the tend flag in ssr is set to 1, a tei interrupt request is generated. a txi interrupt can activate the dtc to allow data transfer. the tdre flag is automatically cleared to 0 at data transfer by the dtc. when the rdrf flag in ssr is set to 1, an rxi interrupt request is generated. when the orer, per, or fer flag in ssr is set to 1, an eri interrupt request is generated. an rxi interrupt can activate the dtc to allow data transfer. the rdrf flag is automatically cleared to 0 at data transfer by the dtc. a tei interrupt is requested when the tend flag is set to 1 while the teie bit is set to 1. if a tei interrupt and a txi interrupt are requested simultaneously, the txi interrupt has priority for acceptance. however, note that if the tdre and tend flags are cleared simultaneously by the txi interrupt routine, the sci cannot branch to the tei interrupt routine later. table 15.11 sci interrupt sources channel name interrupt source interrupt flag dtc activation priority eri0 receive error orer, fer, per not possible high rxi0 receive data full rdrf possible txi0 transmit data empty tdre possible 0 tei0 transmit end tend not possible eri1 receive error orer, fer, per not possible rxi1 receive data full rdrf possible txi1 transmit data empty tdre possible 1 tei1 transmit end tend not possible eri2 receive error orer, fer, per not possible rxi2 receive data full rdrf possible txi2 transmit data empty tdre possible 2 tei2 transmit end tend not possible low rev. 2.0, 08/02, page 386 of 788 15.9 usage notes 15.9.1 module stop mode setting sci operation can be disabled or enabled using the module stop control register. the initial setting is for sci operation to be halted. register access is enabled by clearing module stop mode. for details, refer to section 26, power-down modes. 15.9.2 break detection and processing when framing error detection is performed, a break can be detected by reading the rxd pin value directly. in a break, the input from the rxd pin becomes all 0s, and so the fer flag in ssr is set, and the per flag may also be set. note that, since the sci continues the receive operation even after receiving a break, even if the fer flag is cleared to 0, it will be set to 1 again. 15.9.3 mark state and break detection when the te bit in scr is 0, the txd pin is used as an i/o port whose direction (input or output) and level are determined by dr and ddr of the port. this can be used to set the txd pin to the mark state (high level) or send a break during serial data transmission. to maintain the communication line at mark state until te is set to 1, set both ddr and dr to 1. since the te bit is cleared to 0 at this point, the txd pin becomes an i/o port, and 1 is output from the txd pin. to send a break during serial transmission, first set ddr to 1 and dr to 0, and then clear the te bit to 0. when the te bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, the txd pin becomes an i/o port, and 0 is output from the txd pin. 15.9.4 receive error flags and transmit operations (clocked synchronous mode only) transmission cannot be started when a receive error flag (orer, fer, or rer) is ssr is set to 1, even if the tdre flag in ssr is cleared to 0. be sure to clear the receive error flags to 0 before starting transmission. note also that the receive error flags cannot be cleared to 0 even if the re bit in scr is cleared to 0. 15.9.5 relation between writing to tdr and tdre flag data can be written to tdr irrespective of the tdre flag status in ssr. however, if the new data is written to tdr when the tdre flag is 0, that is, when the previous data has not been transferred to tsr yet, the previous data in tdr is lost. be sure to write transmit data to tdr after verifying that the tdre flag is set to 1. rev. 2.0, 08/02, page 387 of 788 15.9.6 restrictions on using dtc when an external clock source is used as a synchronization clock, update tdr by the dtc or rfu and wait for at least five ? clock cycles before allowing the transmit clock to be input. if the transmit clock is input within four clock cycles after tdr modification, the sci may malfunction (figure 15.23). when using the dtc to read rdr, be sure to set the receive end interrupt source (rxi) as a dtc activation source. t d0 lsb serial data sck d1 d3 d4 d5 d2 d6 d7 note: * when external clock is supplied, t must be more than four clock cycles. tdre figure 15.23 example of transmission using dtc in clocked synchronous mode 15.9.7 sci operations during mode transitions transmission: before making a transition to module stop, software standby, or sub-sleep mode, stop all transmit operations (te = tie = teie = 0). tsr, tdr, and ssr are reset. the states of the output pins during each mode depend on the port settings, and the pins output a high-level signal after mode cancellation. if a transition is made during data transmission, the data being transmitted will be undefined. to transmit data in the same transmission mode after mode cancellation, set te to 1, read ssr, write to tdr, clear tdre in this order, and then start transmission. to transmit data in a different transmission mode, initialize the sci first. figure 15.24 shows a sample flowchart for mode transition during transmission. figures 15.25 and 15.26 show the pin states during transmission. before making a transition from the transmission mode using dtc transfer to module stop, software standby, or sub-sleep mode, stop all transmit operations (te = tie = teie = 0). setting te and tie to 1 after mode cancellation generates a txi interrupt request to start transmission using the dtc. rev. 2.0, 08/02, page 388 of 788 reception: before making a transition to module stop, software standby, watch, sub-active, or sub-sleep mode, stop reception (re = 0). rsr, rdr, and ssr are reset. if a transition is made during data reception, the data being received will be invalid. to receive data in the same reception mode after mode cancellation, set re to 1, and then start reception. to receive data in a different reception mode, initialize the sci first. figure 15.27 shows a sample flowchart for mode transition during reception. start transmission transmission [1] no no no yes yes yes read tend flag in ssr make transition to software standby mode etc. cancel software standby mode etc. te = 0 initialization te = 1 [2] [3] all data transmitted? change operating mode? tend = 1 [1] data being transmitted is lost halfway. data can be normally transmitted from the cpu by setting te to 1, reading ssr, writing to tdr, and clearing tdre to 0 after mode cancellation; however, if the dtc has been initiated, the data remaining in dtc ram will be transmitted when te and tie are set to 0. [2] also clear tie and teie to 0 when they are 1. [3] module stop, watch, sub-active, and sub-sleep modes are included. figure 15.24 sample flowchart for mode transition during transmission rev. 2.0, 08/02, page 389 of 788 te bit sck output pin txd output pin port input/output port input/output port input/output start stop high output high output transmission start transmission end transition to software standby mode software standby mode cancelled sci txd output port port sci txd output figure 15.25 pin states during transmission in asynchronous mode (internal clock) te bit sck output pin txd output pin port input/output port input/output port input/output high output * marking output transmission start transmission end transition to software standby mode software standby mode cancelled sci txd output port port sci txd output last txd bit retained note: * initialized in software standby mode figure 15.26 pin states during transmission in clocked synchronous mode (internal clock) rev. 2.0, 08/02, page 390 of 788 start reception reception [1] no no yes yes read receive data in rdr read rdrf flag in ssr make transition to software standby mode etc. cancel software standby mode etc. re = 0 initialization re = 1 [2] change operating mode? rdrf = 1 [1] data being received will be invalid. [2] module stop, watch, sub-active, and sub- sleep modes are included. figure 15.27 sample flowchart for mode transition during reception rev. 2.0, 08/02, page 391 of 788 15.9.8 notes on switching from sck pins to port pins when sck pins are switched to port pins after transmission has completed, pins are enabled for port output after outputting a low pulse of half a cycle as shown in figure 15.28. sck/port cke0 cke1 c/ te data 1. transmission end 2. te = 0 3. c/ = 0 4. low pulse output bit 6 bit 7 low pulse of half a cycle figure 15.28 switching from sck pins to port pins to prevent the low pulse output that is generated when switching the sck pins to the port pins, specify the sck pins for input (pull up the sck/port pins externally), and follow the procedure below with ddr = 1, dr = 1, c/ $ = 1, cke1 = 0, cke1 = 0, and te = 1. 1. end serial data transmission 2. te bit = 0 3. cke1 bit = 1 4. c/ $ bit = 0 (switch to port output) 5. cke1 bit = 0 sck/port cke0 cke1 c/ te data 1. transmission end 2. te = 0 4. c/ = 0 3. cke1 = 1 5. cke1 = 0 bit 6 bit 7 high output figure 15.29 prevention of low pulse output at switching from sck pins to port pins rev. 2.0, 08/02, page 392 of 788 rev. 2.0, 08/02, page 393 of 788 section 16 i 2 c bus interface (iic) (optional) the i 2 c bus interface is provided as an optional function. note the following point when using this optional function. although the product type name is identical, please contact hitachi before using this optional function on an f-ztat version product. this lsi has a two-channel i 2 c bus interface. the i 2 c bus interface conforms to and provides a subset of the philips i 2 c bus (inter-ic bus) interface functions. the register configuration that controls the i 2 c bus differs partly from the philips configuration, however. 16.1 features selection of addressing format or non-addressing format ? i 2 c bus format: addressing format with an acknowledge bit, for master/slave operation ? clocked synchronous serial format: non-addressing format without an acknowledge bit, for master operation only ? formatless (for iic_0 only): non-addressing format with a clock pin dedicated for formatless; for slave operation only conforms to philips i 2 c bus interface (i 2 c bus format) two ways of setting slave address (i 2 c bus format) start and stop conditions generated automatically in master mode (i 2 c bus format) selection of the acknowledge output level in reception (i 2 c bus format) automatic loading of an acknowledge bit in transmission (i 2 c bus format) wait function in master mode (i 2 c bus format) ? a wait can be inserted by driving the scl pin low after data transfer, excluding acknowledgement. ? the wait can be cleared by clearing the interrupt flag. wait function (i 2 c bus format) ? a wait request can be generated by driving the scl pin low after data transfer. ? the wait request is cleared when the next transfer becomes possible. interrupt sources ? data transfer end (including when a transition to transmit mode with i 2 c bus format occurs, when icdr data is transferred, or during a wait state) ? address match: when any slave address matches or the general call address is received in slave receive mode with i 2 c bus format (including address reception after loss of master arbitration) ? start condition detection (in master mode) ? stop condition detection (in slave mode) ifiic60a_000020020700 rev. 2.0, 08/02, page 394 of 788 selection of 16 internal clocks (in master mode) direct bus drive (scl/sda pin) ? four pinsp52/scl0, p97/sda0, p86/scl1, and p42/sda1 (normally nmos push- pull outputs) function as nmos open-drain outputs when the bus drive function is selected. automatic switching from formatless mode to i 2 c bus format (iic_0 only) ? formatless operation (no start/stop conditions, non-addressing mode) in slave mode ? operation using a common data pin (sda) and independent clock pins (vsynci, scl) ? automatic switching from formatless mode to i 2 c bus format on the fall of the scl pin rev. 2.0, 08/02, page 395 of 788 figure 16.1 shows a block diagram of the i 2 c bus interface. figure 16.2 shows an example of i/o pin connections to external circuits. since i 2 c bus interface i/o pins are different in structure from normal port pins, they have different specifications for permissible applied voltages. for details, see section 28, electrical characteristics. ? scl ps noise canceler bus state decision circuit arbitration decision circuit output data control circuit iccr clock control icxr icmr icsr icdrs address comparator sar, sarx sda noise canceler interrupt generator interrupt request internal data bus icdrr icdrt formatless dedicated clock (iic_0 only) legend: iccr: icmr: icsr: icdr: icxr: sar: sarx: ps: i 2 c bus control register i 2 c bus mode register i 2 c bus status register i 2 c bus data register i 2 c bus extended control register slave address register slave address register x prescaler figure 16.1 block diagram of i 2 c bus interface rev. 2.0, 08/02, page 396 of 788 scl in out sda in out (slave 1) scl sda scl in out sda in out (slave 2) scl sda scl in out sda in out (master) this lsi scl sda v cc v cc scl sda v dd figure 16.2 i 2 c bus interface connections (example: this lsi as master) 16.2 input/output pins table 16.1 summarizes the input/output pins used by the i 2 c bus interface. table 16.1 pin configuration channel symbol * input/output function scl0 input/output serial clock input/output pin of iic_0 sda0 input/output serial data input/output pin of iic_0 0 vsynci input formatless serial clock input pin of iic_0 scl1 input/output serial clock input/output pin of iic_1 1 sda1 input/output serial data input/output pin of iic_1 note: * in the text, the channel subscript is omitted, and only scl and sda are used. rev. 2.0, 08/02, page 397 of 788 16.3 register descriptions the i 2 c bus interface has the following registers. registers icdr and sarx and registers icmr and sar are allocated to the same addresses. accessible registers differ depending on the ice bit in iccr. when the ice bit is cleared to 0, sar and sarx can be accessed, and when the ice bit is set to 1, icmr and icdr can be accessed. for details on the serial timer control register, refer to section 3.2.3, serial timer control register (stcr). i 2 c bus control register (iccr) i 2 c bus status register (icsr) i 2 c bus data register (icdr) i 2 c bus mode register (icmr) slave address register (sar) second slave address register (sarx) i 2 c bus extended control register (icxr) ddc switch register (ddcswr) (for iic_0 only) 16.3.1 i 2 c bus data register (icdr) icdr is an 8-bit readable/writable register that is used as a transmit data register when transmitting and a receive data register when receiving. icdr is internally divided into a shift register (icdrs), receive buffer (icdrr), and transmit buffer (icdrt). data transfers among these three registers are performed automatically in accordance with changes in the bus state, and they affect the status of internal flags such as icdre and icdrf. in master transmit mode with the i 2 c bus format, writing transmit data to icdr should be performed after start condition detection. when the start condition is detected, previous write data is ignored. in slave transmit mode, writing should be performed after the slave addresses match and the trs bit is automatically changed to 1. if the iic is in transmit mode (trs = 1) and icdrt has the next transmit data (the icdre flag is 0) after successful transmission/reception of one frame of data using icdrs, data is transferred automatically from icdrt to icdrs. if the iic is in transmit mode (trs = 1) and icdrt has the next data (the icdre flag is 0), data is transferred automatically from icdrt to icdrs, following transmission of one frame of data using icdrs. when the icdre flag is 1 and the next transmit data writing is waited, data is transferred automatically from icdrt to icdrs by writing to icdr. if i 2 c is in receive mode (trs = 0), no data is transferred from icdrt to icdrs. note that data should not be written to icdr in receive mode. reading receive data from icdr is performed after data is transferred from icdrs to icdrr. rev. 2.0, 08/02, page 398 of 788 if i 2 c is in receive mode and no previous data remains in icdrr (the icdrf flag is 0), data is transferred automatically from icdrs to icdrr, following reception of one frame of data using icdrs. if additional data is received while the icdrf flag is 1, data is transferred automatically from icdrs to icdrr by reading from icdr. in transmit mode, no data is transferred from icdrs to icdrr. always set i 2 c to receive mode before reading from icdr. if the number of bits in a frame, excluding the acknowledge bit, is less than eight, transmit data and receive data are stored differently. transmit data should be written justified toward the msb side when mls = 0 in icmr, and toward the lsb side when mls = 1. receive data bits should be read from the lsb side when mls = 0, and from the msb side when mls = 1. icdr can be written to and read from only when the ice bit is set to 1 in iccr. the initial value of icdr is undefined. 16.3.2 slave address register (sar) sar sets the slave address and selects the communication format. if the lsi is in slave mode with the i 2 c bus format selected, when the fs bit is set to 0 and the upper 7 bits of sar match the upper 7 bits of the first frame received after a start condition, the lsi operates as the slave device specified by the master device. sar can be accessed only when the ice bit in iccr is cleared to 0. bit bit name initial value r/w description 7 6 5 4 3 2 1 sva6 sva5 sva4 sva3 sva2 sva1 sva0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w slave address 6 to 0 set a slave address. 0fs 0 r/wformat select selects the communication format together with the fsx bit in sarx and the sw bit in ddcswr. refer to table 16.2. this bit should be set to 0 when general call address recognition is performed. rev. 2.0, 08/02, page 399 of 788 16.3.3 second slave address register (sarx) sarx sets the second slave address and selects the communication format. in slave mode, transmit/receive operations by the dtc are possible when the received address matches the second slave address. if the lsi is in slave mode with the i 2 c bus format selected, when the fsx bit is set to 0 and the upper 7 bits of sarx match the upper 7 bits of the first frame received after a start condition, the lsi operates as the slave device specified by the master device. sarx can be accessed only when the ice bit in iccr is cleared to 0. bit bit name initial value r/w description 7 6 5 4 3 2 1 svax6 svax5 svax4 svax3 svax2 svax1 svax0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w second slave address 6 to 0 set the second slave address. 0 fsx 1 r/w format select x selects the communication format together with the fs bit in sar and the sw bit in ddcswr. refer to table 16.2. rev. 2.0, 08/02, page 400 of 788 table 16.2 communication format ddcswr sar sarx sw fs fsx operating mode 0i 2 c bus format sar and sarx slave addresses recognized general call address recognized 0 1i 2 c bus format sar slave address recognized sarx slave address ignored general call address recognized 0i 2 c bus format sar slave address ignored sarx slave address recognized general call address ignored 0 1 1 clocked synchronous serial format sar and sarx slave addresses ignored general call address ignored 0 0 1 0 formatless mode (start/stop conditions not detected) acknowledge bit used 1 1 1 formatless mode * (start/stop conditions not detected) no acknowledge bit do not set this mode when automatic switching to the i 2 c bus format is performed by means of the ddcswr setting. i 2 c bus format: addressing format with an acknowledge bit clocked synchronous serial format: non-addressing format without an acknowledge bit, for master mode only formatless mode (for iic_0 only): non-addressing format with or without an acknowledge bit, slave mode only, start/stop conditions not detected rev. 2.0, 08/02, page 401 of 788 16.3.4 i 2 c bus mode register (icmr) icmr sets the communication format and transfer rate. it can only be accessed when the ice bit in iccr is set to 1. bit bit name initial value r/w description 7 mls 0 r/w msb-first/lsb-first select 0: msb-first 1: lsb-first set this bit to 0 when the i 2 c bus format is used. 6 wait 0 r/w wait insertion bit this bit is valid only in master mode with the i 2 c bus format. 0: data and the acknowledge bit are transferred consecutively with no wait inserted. 1: after the fall of the clock for the final data bit (8 th clock), the iric flag is set to 1 in iccr, and a wait state begins (with scl at the low level). when the iric flag is cleared to 0 in iccr, the wait ends and the acknowledge bit is transferred. for details, refer to section 16.4.7, iric setting timing and scl control. 5 4 3 cks2 cks1 cks0 0 0 0 r/w r/w r/w transfer clock select 2 to 0 these bits are used only in master mode. these bits select the required transfer rate, together with the iicx1 (iic_1) and iicx0 (iic_0) bits in stcr. refer to table 16.3. rev. 2.0, 08/02, page 402 of 788 bit bit name initial value r/w description 2 1 0 bc2 bc1 bc0 0 0 0 r/w r/w r/w bit counter 2 to 0 these bits specify the number of bits to be transferred next. bit bc2 to bc0 settings should be made during an interval between transfer frames. if bits bc2 to bc0 are set to a value other than 000, the setting should be made while the scl line is low. the bit counter is initialized to 000 when a start condition is detected. the value returns to 000 at the end of a data transfer. i 2 c bus format clocked synchronous serial mode 000: 9 bits 000: 8 bits 001: 2 bits 001: 1 bits 010: 3 bits 010: 2 bits 011: 4 bits 011: 3 bits 100: 5 bits 100: 4 bits 101: 6 bits 101: 5 bits 110: 7 bits 110: 6 bits 111: 8 bits 111: 7 bits rev. 2.0, 08/02, page 403 of 788 table 16.3 i 2 c transfer rate stcr icmr bits 5 and 6 bit 5 bit 4 bit 3 transfer rate iicx cks2 cks1 cks0 clock ? = 5 mhz ? = 8 mhz ? = 10 mhz ? = 16 mhz ? = 20 mhz 0000?/28 179 khz 286 khz 357 khz 517 khz * 714 khz * 0001?/40 125 khz 200 khz 250 khz 400 khz 500 khz * 0010?/48 104 khz 167 khz 208 khz 333 khz 417 khz * 0011?/6478.1 khz 125 khz 156 khz 250 khz 313 khz 0100?/8062.5 khz 100 khz 125 khz 200 khz 250 khz 0101?/10050.0 khz80.0 khz 100 khz 160 khz 200 khz 0110?/11244.6 khz71.4 khz89.3 khz 143 khz 179 khz 0111?/12839.1 khz62.5 khz78.1 khz 125 khz 156 khz 1000?/5689.3 khz 143 khz 179 khz 286 khz 357 khz 1001?/8062.5 khz 100 khz 125 khz 200 khz 250 khz 1010?/9652.1 khz83.3 khz 104 khz 167 khz 208 khz 1011?/12839.1 khz62.5 khz78.1 khz 125 khz 156 khz 1100?/16031.3 khz50.0 khz62.5 khz 100 khz 125 khz 1101?/20025.0 khz40.0 khz50.0 khz80.0 khz 100 khz 1110?/22422.3 khz35.7 khz44.6 khz71.4 khz89.3 khz 1111?/25619.5 khz31.3 khz39.1 khz62.5 khz78.1 khz note: * outside the i 2 c bus interface specifications (standard mode: max. 100 khz; high-speed mode: max. 400 khz) rev. 2.0, 08/02, page 404 of 788 16.3.5 i 2 c bus control register (iccr) iccr controls the i 2 c bus interface and performs interrupt flag confirmation. bit bit name initial value r/w description 7ice 0 r/wi 2 c bus interface enable 0: i 2 c bus interface modules are stopped and i 2 c bus interface module internal state is initialized. sar and sarx can be accessed. 1: i 2 c bus interface modules can perform transfer operation, and the ports function as the scl and sda input/output pins. icmr and icdr can be accessed. 6ieic 0 r/wi 2 c bus interface interrupt enable 0: disables interrupts from the i 2 c bus interface to the cpu 1: enables interrupts from the i 2 c bus interface to the cpu. 5 4 mst trs 0 0 r/w r/w master/slave select transmit/receive select 00: slave receive mode 01: slave transmit mode 10: master receive mode 11: master transmit mode both these bits will be cleared by hardware when they lose in a bus contention in master mode with the i 2 c bus format. in slave receive mode with i 2 c bus format, the r/w bit in the first frame immediately after the start condition sets these bits in receive mode or transmit mode automatically by hardware. modification of the trs bit during transfer is deferred until transfer is completed, and the changeover is made after completion of the transfer. rev. 2.0, 08/02, page 405 of 788 bit bit name initial value r/w description 5 4 mst trs 0 0 r/w [mst clearing conditions] 1. when 0 is written by software 2. when lost in bus contention in i 2 c bus format master mode [mst setting conditions] 1. when 1 is written by software (for mst clearing condition 1) 2. when 1 is written in mst after reading mst = 0 (for mst clearing condition 2) [trs clearing conditions] 1. when 0 is written by software (except for trs setting condition 3) 2. when 0 is written in trs after reading trs = 1 (for trs setting condition 3) 3 when lost in bus contention in i 2 c bus format master mode 4. when the sw bit in ddcswr is changed from 1 to 0 [trs setting conditions] 1. when 1 is written by software (except for trs clearing conditions 3 and 4) 2. when 1 is written in trs after reading trs = 0 (for trs clearing conditions 3 and 4) 3. when 1 is received as the r/ : bit after the first frame address matching in i 2 c bus format slave mode 3 acke 0 r/w acknowledge bit decision and selection 0: the value of the acknowledge bit is ignored, and continuous transfer is performed. the value of the received acknowledge bit is not indicated by the ackb bit in icsr, which is always 0. 1: if the received acknowledge bit is 1, continuous transfer is halted. depending on the receiving device, the acknowledge bit may be significant, in indicating completion of processing of the received data, for instance, or may be fixed at 1 and have no significance. rev. 2.0, 08/02, page 406 of 788 bit bit name initial value r/w description 2 0 bbsy scp 0 1 r/w w bus busy start condition/stop condition prohibit in master mode: writing 0 in bbsy and 0 in scp: a stop condition is issued writing 1 in bbsy and 0 in scp: a start condition and a restart condition are issued in slave mode: writing to the bbsy flag is disabled. [bbsy setting condition] when the sda level changes from high to low under the condition of scl = high, assuming that the start condition has been issued. [bbsy clearing condition] when the sda level changes from low to high under the condition of scl = high, assuming that the stop condition has been issued. to issue a start/stop condition, use the mov instruction. the i 2 c bus interface must be set in master transmit mode before the issue of a start condition. set mst to 1 and trs to 1 before writing 1 in bbsy and 0 in scp. the bbsy flag can be read to check whether the i 2 c bus (scl, sda) is busy or free. the scp bit is always read as 1. if 0 is written, the data is not stored. rev. 2.0, 08/02, page 407 of 788 bit bit name initial value r/w description 1 iric 0 r/w i 2 c bus interface interrupt request flag indicates that the i 2 c bus interface has issued an interrupt request to the cpu. iric is set at different times depending on the fs bit in sar, the fsx bit in sarx, and the wait bit in icmr. see section 16.4.7, iric setting timing and scl control. the conditions under which iric is set also differ depending on the setting of the acke bit in iccr. [setting conditions] i 2 c bus format master mode: when a start condition is detected in the bus line state after a start condition is issued (when the icdre flag is set to 1 because of first frame transmission) when a wait is inserted between the data and acknowledge bit when the wait bit is 1 (fall of the 8th transmit/receive clock) at the end of data transfer (rise of the 9th transmit/receive clock while no wait is inserted) when a slave address is received after bus arbitration is lost (the first frame after the start condition) if 1 is received as the acknowledge bit (when the ackb bit in icsr is set to 1) when the acke bit is 1 when the al flag is set to 1 after bus arbitration is lost while the alie bit is 1 i 2 c bus format slave mode: when the slave address (sva or svax) matches (when the aas or aasx flag in icsr is set to 1) and at the end of data transfer up to the subsequent retransmission start condition or stop condition detection (rise of the 9th transmit/receive clock) when the general call address is detected (when 0 is received as the r/ : bit and the adz flag in icsr is set to 1) and at the end of data reception up to the subsequent retransmission start condition or stop condition detection (rise of the 9th receive clock) if 1 is received as the acknowledge bit (when the ackb bit in icsr is set to 1) while the acke bit is 1 when a stop condition is detected (when the stop or estp flag in icsr is set to 1) while the stopim bit is 0 rev. 2.0, 08/02, page 408 of 788 bit bit name initial value r/w description 1 iric 0 r/w clocked synchronous serial format and formatless modes: at the end of data transfer (rise of the 8th transmit/receive clock with serial format selected and rise of the 9th transmit/receive clock with formatless selected) when a start condition is detected with serial format selected when the sw bit in ddcswr is set to 1 when the icdre or icdrf flag is set to 1 in any operating mode: when a start condition is detected in transmit mode (when a start condition is detected in transmit mode and the icdre flag is set to 1) when data is transferred among the icdr register and buffer (when data is transferred from icdrt to icdrs in transmit mode and the icdre flag is set to 1, or when data is transferred from icdrs to icdrr in receive mode and the icdrf flag is set to 1) [clearing conditions] when 0 is written in iric after reading iric = 1 when icdr is read from or written to by the dtc (this may not function as a clearing condition depending on the situation. for details, see the description of the dtc operation given below.) note: * only 0 can be written, to clear the flag. rev. 2.0, 08/02, page 409 of 788 when the dtc is used, iric is cleared automatically and transfer can be performed continuously without cpu intervention. when, with the i 2 c bus format selected, iric is set to 1 and an interrupt is generated, other flags must be checked in order to identify the source that set iric to 1. although each source has a corresponding flag, caution is needed at the end of a transfer. when the icdre or icdrf flag is set, the irtr flag may or may not be set. the irtr flag (the dtc start request flag) is not set at the end of a data transfer up to detection of a retransmission start condition or stop condition after a slave address (sva) or general call address match in i 2 c bus format slave mode. even when the iric flag and irtr flag are set, the icdre or icdrf flag may not be set. the iric and irtr flags are not cleared at the end of the specified number of transfers in continuous transfer using the dtc. the icdre or icdrf flag is cleared, however, since the specified number of icdr reads or writes have been completed. tables 16.4 and 16.5 show the relationship between the flags and the transfer states. rev. 2.0, 08/02, page 410 of 788 table 16.4 flags and transfer states (master mode) mst trs bbsy estp stop irtr aasx al aas adz ackb icdrf icdre state 1100000 00 0 0 0 idle state (flag clearing required) 111 - 001 - 000001 - start condition detected 11000000wait state 1110000001 - transmission end (acke=1 and ackb=1) 111001 - 000001 - transmission end with icdre=0 11100000000 icdr write with the above state 11100000001transmission end with icdre=1 11100000000 icdr write with the above state or after start condition detected 111001 - 000001 - automatic data transfer from icdrt to icdrs with the above state 101001 - 00001 - reception end with icdrf=0 1010000000 icdr read with the above state 1010000001reception end with icdrf=1 1010000000 icdr read with the above state 101001 - 00001 - automatic data transfer from icdrs to icdrr with the above state rev. 2.0, 08/02, page 411 of 788 mst trs bbsy estp stop irtr aasx al aas adz ackb icdrf icdre state 0 0 10001 - 0 0 arbitration lost 10 0000000 stop condition detected legend 0: 0-state retained 1: 1-state retained : previous state retained 0 : cleared to 0 1 - : set to 1 rev. 2.0, 08/02, page 412 of 788 table 16.5 flags and transfer states (slave mode) mst trs bbsy estp stop irtr aasx al aas adz ackb icdrf icdre state 000000000000idle state (flag clearing required) 001 - 0000 00001 - start condition detected 01 - /0 * 1 100001 - 001 - 1 sar match in first frame (sarx 1 sar) 00100001 - 1 - 01 - 1 general call address match in first frame (sarx 1 h00) 01 - /0 * 1 1001 - 1 - 0001 - 1 sars match in first frame (sar 1 sarx) 0110001 - transmission end (acke=1 and ackb=1) 011001 - /0 * 1 0 0 1 - transmission end with icdre=0 011000 0 000 icdr write with the above state 0110010 1transmission end with icdre=1 011000 0 00 0 icdr write with the above state 011001 - /0 * 2 0 0 0 0 1 - automatic data transfer from icdrt to icdrs with the above state 001001 - /0 * 2 1 - reception end with icdrf=0 001000 0 0 0 icdr read with the above state rev. 2.0, 08/02, page 413 of 788 mst trs bbsy estp stop irtr aasx al aas adz ackb icdrf icdre state 0 0 1 0 0 1 reception end with icdrf=1 001000 0 0 0 icdr read with the above state 001001 - /0 * 2 0 0 0 1 - automatic data transfer from icdrs to icdrr with the above state 00 1 - /0 * 3 0/1 - * 3 0 stop condition detected legend 0: 0-state retained 1: 1-state retained : previous state retained 0 : cleared to 0 1 - : set to 1 notes: 1. set to 1 when 1 is received as a r/ : bit following an address. 2. set to 1 when the aasx bit is set to 1. 3. when estp=1, stop is 0, or when stop=1, estp is 0. rev. 2.0, 08/02, page 414 of 788 16.3.6 i 2 c bus status register (icsr) icsr consists of status flags. also see tables 16.4 and 16.5. bit bit name initial value r/w description 7 estp 0 r/(w) * error stop condition detection flag this bit is valid in i 2 c bus format slave mode. [setting condition] when a stop condition is detected during frame transfer. [clearing conditions] when 0 is written in estp after reading estp = 1 when the iric flag in iccr is cleared to 0 6 stop 0 r/(w) * normal stop condition detection flag this bit is valid in i 2 c bus format slave mode. [setting condition] when a stop condition is detected after frame transfer completion. [clearing conditions] when 0 is written in stop after reading stop = 1 when the iric flag is cleared to 0 5 irtr 0 r/(w) * i 2 c bus interface continuous transfer interrupt request flag indicates that the i 2 c bus interface has issued an interrupt request to the cpu, and the source is completion of reception/transmission of one frame in continuous transmission/reception for which dtc activation is possible. when the irtr flag is set to 1, the iric flag is also set to 1 at the same time. [setting conditions] i 2 c bus format slave mode: when the icdre or icdrf flag in icdr is set to 1 when aasx = 1 master mode or clocked synchronous serial format mode with i 2 c bus format, or formatless mode: when the icdre or icdrf flag is set to 1 [clearing conditions] when 0 is written after reading irtr = 1 when the iric flag is cleared to 0 while ice is 1 rev. 2.0, 08/02, page 415 of 788 bit bit name initial value r/w description 4 aasx 0 r/(w) * second slave address recognition flag in i 2 c bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits svax6 to svax0 in sarx. [setting condition] when the second slave address is detected in slave receive mode and fsx = 0 in sarx [clearing conditions] when 0 is written in aasx after reading aasx = 1 when a start condition is detected in master mode 3 al 0 r/(w) * arbitration lost flag indicates that arbitration was lost in master mode. [setting conditions] when alsl=0 if the internal sda and sda pin disagree at the rise of scl in master transmit mode if the internal scl line is high at the fall of scl in master transmit mode when alsl=1 if the internal sda and sda pin disagree at the rise of scl in master transmit mode if the sda pin is driven low by another device before the i 2 c bus interface drives the sda pin low, after the start condition instruction was executed in master transmit mode [clearing conditions] when icdr is written to (transmit mode) or read from (receive mode) when 0 is written in al after reading al = 1 rev. 2.0, 08/02, page 416 of 788 bit bit name initial value r/w description 2 aas 0 r/(w) * slave address recognition flag in i 2 c bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits sva6 to sva0 in sar, or if the general call address (h'00) is detected. [setting condition] when the slave address or general call address (one frame including a r/ : bit is h00) is detected in slave receive mode and fs = 0 in sar [clearing conditions] when icdr is written to (transmit mode) or read from (receive mode) when 0 is written in aas after reading aas = 1 in master mode 1adz 0 r/(w) * general call address recognition flag in i 2 c bus format slave receive mode, this flag is set to 1 if the first frame following a start condition is the general call address (h'00). [setting condition] when the general call address (one frame including a r/ : bit is h00) is detected in slave receive mode and fs = 0 or fsx = 0 [clearing conditions] when icdr is written to (transmit mode) or read from (receive mode) when 0 is written in adz after reading adz = 1 in master mode if a general call address is detected while fs=1 and fsx=0, the adz flag is set to 1; however, the general call address is not recognized (aas flag is not set to 1). rev. 2.0, 08/02, page 417 of 788 bit bit name initial value r/w description 0 ackb 0 r/w acknowledge bit stores acknowledge data. transmit mode: [setting condition] when 1 is received as the acknowledge bit when acke=1 in transmit mode [clearing conditions] when 0 is received as the acknowledge bit when acke=1 in transmit mode when 0 is written to the acke bit receive mode: 0: returns 0 as acknowledge data after data reception 1: returns 1 as acknowledge data after data reception when this bit is read, the value loaded from the bus line (returned by the receiving device) is read in transmission (when trs = 1). in reception (when trs = 0), the value set by internal software is read. when this bit is written, acknowledge data that is returned after receiving is rewritten regardless of the trs value. if the icsr register bit is written using bit-manipulation instructions, the acknowledge data should be re-set since the acknowledge data setting is rewritten by the ackb bit reading value. write the acke bit to 0 to clear the ackb flag to 0, before transmission is ended and a stop condition is issued in master mode, or before transmission is ended and sda is released to issue a stop condition by a master device. note: * only 0 can be written to clear the flag. rev. 2.0, 08/02, page 418 of 788 16.3.7 ddc switch register (ddcswr) ddcswr controls the iic_0 automatic format switching function and iic internal latch clearance. bit bit name initial value r/w description 7 swe 0 r/w ddc mode switch enable 0: disables automatic switching of iic channel 0 from formatless mode to i 2 c bus format 1: enables automatic switching of iic channel 0 from formatless mode to i 2 c bus format 6 sw 0 r/w ddc mode switch 0: uses iic channel 0 with the i 2 c bus format 1: uses iic channel 0 in formatless mode [setting condition] when 1 is written in sw after reading sw = 0 [clearing conditions] when 0 is written by software when a falling edge is detected on the scl pin when swe = 1 5 ie 0 r/w ddc mode switch interrupt enable bit 0: disables interrupts when automatic format switching is executed 1: enables interrupts when automatic format switching is executed 4 if 0 r/(w) * 1 ddc mode switch interrupt flag indicates an interrupt request to the cpu is generated when automatic format switching is executed for iic_0. [setting condition] when a falling edge is detected on the scl pin when swe = 1 [clearing condition] when 0 is written in if after reading if = 1 rev. 2.0, 08/02, page 419 of 788 bit bit name initial value r/w description 3 2 1 0 clr3 clr2 clr1 clr0 1 1 1 1 w * 2 iic clear 3 to 0 controls initialization of the internal state of iic_0 and iic_1. 00--: setting prohibited 0100: setting prohibited 0101: iic_0 internal latch cleared 0110: iic_1 internal latch cleared 0111: iic_0 and iic_1 internal latches cleared 1---: invalid setting when a write operation is performed on these bits, a clear signal is generated for the internal latch circuit of the corresponding module, and the internal state of the iic module is initialized. these bits can only be written to; they are always read as 1. write data to this bit is not retained. to perform iic clearance, bits clr3 to clr0 must be written to simultaneously using an mov instruction. do not use a bit manipulation instruction such as bclr. when clearing is required again, all the bits must be written to in accordance with the setting. if the function of these bits is not used, set all of the clr3 to clr0 bits to 1 when writing to ddcswr. notes: 1. only 0 can be written, to clear the flag. 2. this bit is always read as 1. rev. 2.0, 08/02, page 420 of 788 16.3.8 i 2 c bus extended control register (icxr) icxr enables or disables the i 2 c bus interface interrupt generation and continuous receive operation, and indicates the status of receive/transmit operations. bit bit name initial value r/w description 7 stopim 0 r/w stop condition interrupt source mask enables or disables the interrupt generation when the stop condition is detected in slave mode. 0: enables iric flag setting and interrupt generation when the stop condition is detected (stop = 1 or estp = 1) in slave mode. 1: disables iric flag setting and interrupt generation when the stop condition is detected. 6 hnds 0 r/w handshake receive operation select enables or disables continuous receive operation in receive mode. 0: enables continuous receive operation 1: disables continuous receive operation when the hnds bit is cleared to 0, receive operation is performed continuously after data has been received successfully while icdrf flag is 0. when the hnds bit is set to 1, scl is fixed to the low level and the next data transfer is disabled after data has been received successfully while the icdrf flag is 0. the bus line is released and next receive operation is enabled by reading the receive data in icdr. rev. 2.0, 08/02, page 421 of 788 bit bit name initial value r/w description 5 icdrf 0 r receive data read request flag indicates the icdr (icdrr) status in receive mode. 0: indicates that the data has been already read from icdr (icdrr) or icdr is initialized. 1: indicates that data has been received successfully and transferred from icdrs to icdrr, and the data is ready to be read out. [setting conditions] when data is received successfully and transferred from icdrs to icdrr. (1) when data is received successfully while icdrf = 0 (at the rise of the 9th clock pulse). (2) when icdr is read successfully in receive mode after data was received while icdrf = 1. [clearing conditions] when icdr (icdrr) is read. when 0 is written to the ice bit. when the iic is internally initialized using the clr3 to clr0 bits in ddcswr. when icdrf is set due to the condition (2) above, icdrf is temporarily cleared to 0 when icdr (icdrr) is read; however, since data is transferred from icdrs to icdrr immediately, icdrf is set to 1 again. note that icdr cannot be read successfully in transmit mode (trs = 1) because data is not transferred from icdrs to icdrr. be sure to read data from icdr in receive mode (trs = 0). rev. 2.0, 08/02, page 422 of 788 bit bit name initial value r/w description 4 icdre 0 r transmit data write request flag indicates the icdr (icdrt) status in transmit mode. 0: indicates that the data has been already written to icdr (icdrt) or icdr is initialized. 1: indicates that data has been transferred from icdrt to icdrs and is being transmitted, or the start condition has been detected or transmission has been complete, thus allowing the next data to be written to. [setting conditions] when the start condition is detected from the bus line state with i 2 c bus format or serial format. when i 2 c bus mode is switched to formatless (when the sw bit in ddcswr is set to 1). when data is transferred from icdrt to icdrs. 1. when data transmission completed while icdre = 0 (at the rise of the 9th clock pulse). 2. when data is written to icdr in transmit mode after data transmission was completed while icdre = 1. [clearing conditions] when data is written to icdr (icdrt). when the stop condition is detected with i 2 c bus format or serial format. when 0 is written to the ice bit. when the iic is internally initialized using the clr3 to clr0 bits in ddcswr. note that if the acke bit is set to 1 with i 2 c bus format thus enabling acknowledge bit decision, icdre is not set when data transmission is completed while the acknowledge bit is 1. when icdre is set due to the condition (2) above, icdre is temporarily cleared to 0 when data is written to icdr (icdrt); however, since data is transferred from icdrt to icdrs immediately, icdre is set to 1 again. do not write data to icdr when trs = 0 because the icdre flag value is invalid during the time. rev. 2.0, 08/02, page 423 of 788 bit bit name initial value r/w description 3 alie 0 r/w arbitration lost interrupt enable enables or disables iric flag setting and interrupt generation when arbitration is lost. 0: disables interrupt request when arbitration is lost. 1: enables interrupt request when arbitration is lost. 2 alsl 0 r/w arbitration lost condition select selects the condition under which arbitration is lost. 0: when the sda pin state disagrees with the data that iic bus interface outputs at the rise of scl, or when the scl pin is driven low by another device. 1: when the sda pin state disagrees with the data that iic bus interface outputs at the rise of scl, or when the sda line is driven low by another device in idle state or after the start condition instruction was executed. 1 0 fnc1 fnc0 0 0 r/w r/w function bit cancels some restrictions on usage. for details, refer to section 16.6, usage notes. 00: restrictions on operation remaining in effect 01: setting prohibited 10: setting prohibited 11: restrictions on operation canceled rev. 2.0, 08/02, page 424 of 788 16.4 operation the i 2 c bus interface has an i 2 c bus format and a serial format. 16.4.1 i 2 c bus data format the i 2 c bus format is an addressing format with an acknowledge bit. this is shown in figure 16.3. the first frame following a start condition always consists of 9 bits. iic_0 only is capable of formatless operation, as shown in figure 16.4. the serial format is a non-addressing format with no acknowledge bit. this is shown in figure 16.5. figure 16.6 shows the i 2 c bus timing. the symbols used in figures 16.3 to 16.6 are explained in table 16.6. sa sla 7n r/ data a 1 1m 11 1 a/ 1 p 1 transfer bit count ( n = 1 to 8) transfer frame count (m = from 1) s sla 7n1 7 r/ a data 11 1m1 1 a/ 1 s 1 sla r/ 1 1m2 a 1 data n2 a/ 1 p 1 (a) fs = 0 or fsx = 0 (b) start condition retransmission fs = 0 or fsx = 0 upper row: transfer bit count (n1, n2 = 1 to 8) lower row: transfer frame count (m1, m2 = from 1) figure 16.3 i 2 c bus data format (i 2 c bus format) fs = 0 or fsx = 0 aa data 8n data 11 1m a/ 1 transfer bit count ( n = 1 to 8) transfer frame count (m = from 1) note: * this mode is applied to the pc monitor system standard ddc (display data channel). figure 16.4 i 2 c bus data format (formatless) (iic_0 only) rev. 2.0, 08/02, page 425 of 788 s data 8n data 1 1m p 1 fs=1 and fsx=1 transfer bit count ( n = 1 to 8) transfer frame count (m = from 1) figure 16.5 i 2 c bus data format (serial format) sda scl s sla r/ a 9 8 1C7 9 8 1C7 9 8 1C7 data a data a/ p figure 16.6 i 2 c bus timing table 16.6 i 2 c bus data format symbols legend s start condition. the master device drives sda from high to low while scl is high sla slave address. the master device selects the slave device. r/ : indicates the direction of data transfer: from the slave device to the master device when r/ : is 1, or from the master device to the slave device when r/ : is 0 a acknowledge. the receiving device drives sda low to acknowledge a transfer. (the slave device returns acknowledge in master transmit mode, and the master device returns acknowledge in master receive mode.) data transferred data. the bit length of transferred data is set with the bc2 to bc0 bits in icmr. the msb first or lsb first is switched with the mls bit in icmr. p stop condition. the master device drives sda from low to high while scl is high rev. 2.0, 08/02, page 426 of 788 16.4.2 initialization initialize the iic by the procedure shown in figure 16.7 before starting transmission/reception of data. start initialization set mstp4 = 0 (iic_0) mstp3 = 0 (iic_1) (mstpcrl) set ddcswr set ice = 0 in iccr set icsr set stcr cancel module stop mode set the first and second slave addresses and iic communication format (sva6 to sva0, fs, svax6 to svax0, and fsx) enable icmr and icdr to be accessed use scl/sda pin as an iic port set transfer rate (iicx) enable the cpu accessing to the iic control register and data register set communication format, wait insertion, and transfer rate (mls, wait, cks2 to cks0) enable interrupt (stopim, hnds, alie, alsl, fnc1, and fnc0) set acknowledge bit (ackb) set icmr set iccr set iice = 1 in stcr set sar and sarx set ice = 1 in iccr set icxr << start transmit/receive operation >> set interrupt enable, transfer mode, and acknowledge decision (ieic, mst, trs, and acke) enable sar and sarx to be accessed set iic communication format (swe, sw, ie, and if) figure 16.7 sample flowchart for iic initialization note: be sure to modify the icmr register after transmit/receive operation has been completed. if the icmr register is modified during transmit/receive operation, bit counter bc2 to bc0 will be modified erroneously, thus causing incorrect operation. 16.4.3 master transmit operation in i 2 c bus format master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. figure 16.8 shows the sample flowchart for the operations in master transmit mode. rev. 2.0, 08/02, page 427 of 788 start initialize iic set mst = 1 and trs = 1 in iccr set bbsy =1 and scp = 0 in iccr write transmit data in icdr clear iric flag in iccr no no yes yes yes yes no no [1] initialization [3] select master transmit mode. [4] start condition issuance [6] set transmit data for the first byte (slave address + r/ ). (after writing to icdr, clear iric flag continuously.) [9] set transmit data for the second and subsequent bytes. (after writing to icdr, clear iric flag continuously.) [2] test the status of the scl and sda lines. [7] wait for 1 byte to be transmitted. [10] wait for 1 byte to be transmitted. [11] determine end of tranfer [12] stop condition issuance [8] test the acknowledge bit transferred from the slave device. [5] wait for a start condition generation read iric flag in iccr read ackb bit in icsr iric = 1? ackb = 0? transmit mode? write transmit data in icdr clear iric flag in iccr read iric flag in iccr read ackb bit in icsr clear iric flag in iccr end of transmission? or ackb = 1? set bbsy = 0 and scp = 0 in iccr end read bbsy flag in iccr bbsy = 0? yes no read iric flag in iccr iric = 1? yes no yes no iric = 1? master receive mode figure 16.8 sample flowchart for operations in master transmit mode rev. 2.0, 08/02, page 428 of 788 the transmission procedure and operations by which data is sequentially transmitted in synchronization with icdr (icdrt) write operations, are described below. 1. initialize the iic as described in section 16.4.2, initialization. 2. read the bbsy flag in iccr to confirm that the bus is free. 3. set bits mst and trs to 1 in iccr to select master transmit mode. 4. write 1 to bbsy and 0 to scp in iccr. this changes sda from high to low when scl is high, and generates the start condition. 5. then the iric and irtr flags are set to 1. if the ieic bit in iccr has been set to 1, an interrupt request is sent to the cpu. 6. write the data (slave address + r/ : ) to icdr. with the i 2 c bus format (when the fs bit in sar or the fsx bit in sarx is 0), the first frame data following the start condition indicates the 7-bit slave address and transmit/receive direction (r/ : ). to determine the end of the transfer, the iric flag is cleared to 0. after writing to icdr, clear iric continuously so no other interrupt handling routine is executed. if the time for transmission of one frame of data has passed before the iric clearing, the end of transmission cannot be determined. the master device sequentially sends the transmission clock and the data written to icdr. the selected slave device (i.e. the slave device with the matching slave address) drives sda low at the 9th transmit clock pulse and returns an acknowledge signal. 7. when one frame of data has been transmitted, the iric flag is set to 1 at the rise of the 9th transmit clock pulse. after one frame has been transmitted, scl is automatically fixed low in synchronization with the internal clock until the next transmit data is written. 8. read the ackb bit in icsr to confirm that ackb is cleared to 0. when the slave device has not acknowledged (ackb bit is 1), operate step [12] to end transmission, and retry the transmit operation. 9. write the transmit data to icdr. as indicating the end of the transfer, the iric flag is cleared to 0. perform the icdr write and the iric flag clearing sequentially, just as in step [6]. transmission of the next frame is performed in synchronization with the internal clock. 10. when one frame of data has been transmitted, the iric flag is set to 1 at the rise of the 9th transmit clock pulse. after one frame has been transmitted, scl is automatically fixed low in synchronization with the internal clock until the next transmit data is written. 11. read the ackb bit in icsr. confirm that the slave device has been acknowledged (ackb bit is 0). when there is still data to be transmitted, go to step [9] to continue the next transmission operation. when the slave device has not acknowledged (ackb bit is set to 1), operate step [12] to end transmission. 12. clear the iric flag to 0. write 0 to acke in iccr, to clear received ackb contents to 0. rev. 2.0, 08/02, page 429 of 788 write 0 to bbsy and scp in iccr. this changes sda from low to high when scl is high, and generates the stop condition. sda (master output) sda (slave output) 2 1 r/w 4 36 58 7 12 9 a bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 icdre irtr icdrt note: * data write in icdr prohibited scl (master output) start condition generation slave address data 1 data 1 [9] icdr write [9] iric clear [6] icdr write [6] iric clear [4] bbsy set to 1 scp cleared to 0 (start condition issuance) user processing interrupt request interrupt request address + r/ iric [7] [5] icdrs data 1 address + r/ figure 16.9 example of operation timing in master transmit mode (mls = wait = 0) sda (master output) sda (slave output) 2 14 36 58 79 89 a bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 icdre irtr icdr scl (master output) start condition issuance data 2 [9] icdr write [9] iric clear [12] iric clear [11] ackb read [12] set bbsy=1and scp=0 (stop condition issuance) iric a [10] [7] data 1 data 1 data 2 user processing figure 16.10 example of stop condition issuance operation timing in master transmit mode (mls = wait = 0) rev. 2.0, 08/02, page 430 of 788 16.4.4 master receive operation in i 2 c bus format master receive mode, the master device outputs the receive clock, receives data, and returns an acknowledge signal. the slave device transmits data. the master device transmits data containing the slave address and r/ : (1: read) in the first frame following the start condition issuance in master transmit mode, selects the slave device, and then switches the mode for receive operation. receive operation using the hnds function (hnds = 1): figure 16.11 shows the sample flowchart for the operations in master receive mode (hnds = 1). end set trs = 0 in iccr set ackb = 1 in icsr read iric flag in iccr clear iric flag in iccr clear iric flag in iccr clear iric flag in iccr set hnds = 1 in icxr set bbsy = 0 and scp = 0 in iccr iric = 1? no yes yes read icdr no [4] clear iric flag. [1] select receive mode. [2] start receiving. the first read is a dummy read. [5] read the receive data (for the second and subsequent read) [3] wait for 1 byte to be received. (set iric at the rise of the 9th clock for the receive frame) [6] set acknowledge data for the last reception. [10] read the receive data. [9] clear iric flag. [7] read the receive data. dummy read to start receiving if the first frame is the last receive data. [11] set stop condition issuance. generate stop condition. master receive mode read iric flag in iccr iric = 1? no yes [8] wait for 1 byte to be received. set ackb = 0 in icsr last receive? read icdr read icdr set trs = 1 in iccr figure 16.11 sample flowchart for operations in master receive mode (hnds = 1) rev. 2.0, 08/02, page 431 of 788 the reception procedure and operations using the hnds function, by which the data reception process is provided in 1-byte units with scl fixed low at each data reception, are described below. 1. clear the trs bit in iccr to 0 to switch from transmit mode to receive mode. clear the ackb bit in icsr to 0 (acknowledge data setting). set the hnds bit in icxr to 1. clear the iric flag to 0 to determine the end of reception. go to step [6] to halt reception operation if the first frame is the last receive data. 2. when icdr is read (dummy data read), reception is started, the receive clock is output in synchronization with the internal clock, and data is received. (data from the sda pin is sequentially transferred to icdrs in synchronization with the rise of the receive clock pulses.) 3. the master device drives sda low to return the acknowledge data at the 9th receive clock pulse. the receive data is transferred from icdrs to icdrr at the rise of the 9th clock pulse, setting the icdrf, iric, and irtr flags to 1. if the ieic bit has been set to 1, an interrupt request is sent to the cpu. the master device drives scl low from the fall of the 9th receive clock pulse to the icdr data reading. 4. clear the iric flag to clear the wait state. go to step [6] to halt reception operation if the next frame is the last receive data. 5. read icdr receive data. this clears the icdrf flag to 0. the master device outputs the receive clock continuously to receive the next data. data can be received continuously by repeating steps [3] to [5]. 6. set the ackb bit to 1 so as to return the acknowledge data for the last reception. 7. read icdr receive data. this clears the icdrf flag to 0. the master device outputs the receive clock to receive data. 8. when one frame of data has been received, the icdrf, iric, and irtr flags are set to 1 at the rise of the 9th receive clock pulse. 9. clear the iric flag to 0. 10. read icdr receive data after setting the trs bit. this clears the icdrf flag to 0. 11. clear the bbsy bit and scp bit to 0 in iccr. this changes sda from low to high when scl is high, and generates the stop condition. rev. 2.0, 08/02, page 432 of 788 sda (master output) sda (slave output) 2 14 3 6 5 8 7 1 2 9 9 a a bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 irtr icdrf icdrr scl (master output) master transmit mode master receive mode data 1 data 1 data 2 [1] trs=0 clear [2] iric read (dummy read) [1] iric clear scl is fixed low until icdr is read scl is fixed low until icdr is read [4] iric clear user processing iric [3] [5] icdr read (data 1) undefined value figure 16.12 example of operation timing in master receive mode (mls = wait = 0, hnds = 1) sda (master output) sda (slave output) 2 14 3 6 5 8 7 9 9 78 a a bit 7 bit 1 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 iric icdrf icdrr scl (master output) data 3 data 2 data 1 data 2 data 3 [9] iric clear user processing irtr [8] [3] bit 0 [11] set bbsy=0 and scp=0 (stop condition instruction issuance) [4] iric clear [7] icdr read (data 2) [10] icdr read (data 3) [6] set ackb = 1 bit 0 stop condition generation scl is fixed low until icdr is read scl is fixed low until stop condition is issued figure 16.13 example of stop condition issuance operation timing in master receive mode (mls = wait = 0, hnds = 1) receive operation using the wait function: figures 16.14 and 16.15 show the sample flowcharts for the operations in master receive mode (wait = 1). rev. 2.0, 08/02, page 433 of 788 set trs = 0 in iccr set ackb = 0 in icsr set wait = 1 in icmr yes yes yes clear iric flag in iccr clear iric flag in iccr read iric flag in iccr last receive? iric = 1? irtr = 1? yes irtr=1? no no no no read iric flag in iccr iric=1? no yes read icdr [4] determine end of reception [13] determine end of reception [1] select receive mode. [2] start receiving. the first read is a dummy read. [3] wait for a receive wait (set iric at the fall of the 8th clock) or, wait for 1 byte to be received (set iric at the rise of the 9th clock) [12] wait for a receive wait (set iric at the fall of the 8th clock) or, wait for 1 byte to be received (set iric at the rise of the 9th clock) [5] read the receive data. [6] clear iric flag. (to end the wait insertion) [15] clear wait mode. clear iric flag. ( iric flag should be cleared to 0 after setting wait = 0.) [17] generate stop condition master receive mode [14] clear iric. (to end the wait insertion) [16] read the last receive data. [7] set acknowledge data for the last reception. [8] wait for trs setting [9] set trs for stop condition issuance [10] read the receive data. [11] clear iric flag. (to end the wait insertion) read icdr clear iric flag in iccr set hnds = 0 in icxr wait for one clock pulse set ackb = 1 in icsr set trs = 1 in iccr end set wait = 0 in icmr set bbsy= 0 and scp= 0 in iccr clear iric flag in iccr read icdr clear iric flag in iccr read icdr figure 16.14 sample flowchart for operations in master receive mode (receiving multiple bytes) (wait = 1) rev. 2.0, 08/02, page 434 of 788 end set hnds = 0 in icxr set wait = 0 in icmr set wait = 0 in icmr set ackb = 0 in icsr set ackb = 1 in icsr read icdr clear iric flag in iccr clear iric flag in iccr clear iric flag in iccr read iric flag in iccr read icdr read iric flag in iccr iric = 1? yes no no iric = 1? yes [1] select receive mode. [2] start receiving. the first read is a dummy read. [15] clear wait mode. clear iric flag. ( iric flag should be cleared to 0 after setting wait = 0.) [11] clear iric flag. (to end the wait insertion) [12] wait for 1 byte to be received. (set iric at the rise of the 9th clock) [9] set trs for stop condition issuance [7] set acknowledge data for the last reception. [16] read the last receive data slave receive mode set trs = 0 in iccr set trs = 1 in iccr [17] generate stop condition set bbsy = 0 and scp = 0 in iccr figure 16.15 sample flowchart for operations in master receive mode (receiving a single byte) (wait = 1) rev. 2.0, 08/02, page 435 of 788 the reception procedure and operations using the wait function (wait bit), by which data is sequentially received in synchronization with icdr (icdrr) read operations, are described below. the following describes the multiple-byte reception procedure. in single-byte reception, some steps of the following procedure are omitted. at this time, follow the procedure shown in figure 16.15. 1. clear the trs bit in iccr to 0 to switch from transmit mode to receive mode. clear the ackb bit in icsr to 0 to set the acknowledge data. clear the hnds bit in icxr to 0 to cancel the handshake function. clear the iric flag to 0, and then set the wait bit in icmr to 1. 2. when icdr is read (dummy data is read), reception is started, the receive clock is output in synchronization with the internal clock, and data is received. 3. the iric flag is set to 1 in either of the following cases. if the ieic bit in iccr has been set to 1, an interrupt request is sent to the cpu. ? at the fall of the 8th receive clock pulse for one frame scl is automatically fixed low in synchronization with the internal clock until the iric flag clearing. ? at the rise of the 9th receive clock pulse for one frame the irtr and icdrf flags are set to 1, indicating that one frame of data has been received. the master device outputs the receive clock continuously to receive the next data. 4. read the irtr flag in icsr. if the irtr flag is 0, execute step [6] to clear the iric flag to 0 to release the wait state. if the irtr flag is 1 and the next data is the last receive data, execute step [7] to halt reception. 5. if irtr flag is 1, read icdr receive data. 6. clear the iric flag. when the flag is set as the first case in step [3], the master device outputs the 9th clock and drives sda low at the 9th receive clock pulse to return an acknowledge signal. data can be received continuously by repeating steps [3] to [6]. 7. set the ackb bit in icsr to 1 so as to return the acknowledge data for the last reception. 8. after the iric flag is set to 1, wait for at least one clock pulse until the rise of the first clock pulse for the next receive data. 9. set the trs bit in iccr to 1 to switch from receive mode to transmit mode. the trs bit value becomes valid when the rising edge of the next 9th clock pulse is input. 10. read the icdr receive data. 11. clear the iric flag to 0. 12. the iric flag is set to 1 in either of the following cases. ? at the fall of the 8th receive clock pulse for one frame rev. 2.0, 08/02, page 436 of 788 scl is automatically fixed low in synchronization with the internal clock until the iric flag is cleared. ? at the rise of the 9th receive clock pulse for one frame the irtr and icdrf flags are set to 1, indicating that one frame of data has been received. the master device outputs the receive clock continuously to receive the next data. 13. read the irtr flag in icsr. if the irtr flag is 0, execute step [14] to clear the iric flag to 0 to release the wait state. if the irtr flag is 1 and data reception is complete, execute step [15] to issue the stop condition. 14. if irtr flag is 0, clear the iric flag to 0 to release the wait state. execute step [12] to read the iric flag to detect the end of reception. 15. clear the wait bit in cmr to cancel the wait mode. then, clear the iric flag. clearing of the iric flag should be done while wait = 0. (if the wait bit is cleared to 0 after clearing the iric flag and then an instruction to issue a stop condition is executed, the stop condition may not be issued correctly.) 16. read the last icdr receive data. 17. clear the bbsy bit and scp bit to 0 in iccr. this changes sda from low to high when scl is high, and generates the stop condition. sda (master output) sda (slave output) 2 1 2 1 4 36 58 79 bit 7 bit 6 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 iric irtr icdr scl (master output) data 1 [1] trs cleared to 0 iric cleard to 0 [6] iric clear [5] icdr read (data 1) [6] iric clear (to end wait insertion) user processing bit 5 bit 4 bit 3 5 4 3 9 data 1 data 2 [3] [3] a [2] icdr read (dummy read) master tansmit mode master receive mode a [4]irtr=0 [4] irtr=1 figure 16.16 example of master receive mode operation timing (mls = ackb = 0, wait = 1) rev. 2.0, 08/02, page 437 of 788 sda (master output) sda (slave output) 2 14 3 6 5 8 7 9 9 8 a a bit 7 bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 iric irtr icdr scl (master output) data 3 data 2 data 1 data 2 data 3 [6] iric clear [8] wait for one clock pulse [11] iric clear [14] iric clear [16] icdr read (data 3) user processing [12] [3] [10] icdr read (data 2) [9] set trs=1 [7] set ackb=1 [15] wait cleared to 0, iric clear [17] stop condition issuance bit 0 stop condition generation [13] irtr=1 [13] irtr=0 [12] [4] irtr=1 [4] irtr=0 [3] figure 16.17 example of stop condition issuance timing in master receive mode (mls = ackb = 0, wait = 1) 16.4.5 slave receive operation in i 2 c bus format slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. the slave device operates as the device specified by the master device when the slave address in the first frame following the start condition that is issued by the master device matches its own address. receive operation using the hnds function (hnds = 1): figure 16.18 shows the sample flowchart for the operations in slave receive mode (hnds = 1). rev. 2.0, 08/02, page 438 of 788 slave receive mode end read iric flag in iccr clear iric flag in iccr read iric flag in iccr read aasx, aas and adz in icsr read trs in iccr read iric flag in iccr clear iric in iccr clear iric flag in iccr read icdr read icdr general call address processing * description omitted set mst = 0 and trs = 0 in iccr iric = 1? no yes read iric flag in iccr set ackb = 1 in icsr iric = 1? no yes trs = 1? iric = 1? yes yes no yes no aas = 1 and adz = 1? [1] initialization. select slave receive mode. [2] read the receive data remaining unread. [3] to [7] wait for one byte to be received (slave address + r/w) [10] read the receive data. the first read is a dummy read. [9] set acknowledge data for the last reception. [8] clear iric [5] to [7] wait for the reception to end. [11] detect stop condition slave transmit mode last reception? no no yes read icdr, clear iric flag no yes initialize iic icdrf = 1? [8] clear iric flag. [12] clear iric flag. [10] read the receive data. set ackb = 0 in icsr and hnds = 1 in icxr figure 16.18 sample flowchart for operations in slave receive mode (hnds = 1) rev. 2.0, 08/02, page 439 of 788 the reception procedure and operations using the hnds bit function, by which data reception process is provided in 1-byte unit with scl being fixed low at every data reception, are described below. 1. initialize the iic as described in section 16.4.2, initialization. clear the mst and trs bits to 0 to set slave receive mode, and set the hnds bit to 1 and the ackb bit to 0. clear the iric flag in iccr to 0 to see the end of reception. 2. confirm that the icdrf flag is 0. if the icdrf flag is set to 1, read the icdr and then clear the iric flag to 0. 3. when the start condition output by the master device is detected, the bbsy flag in iccr is set to 1. the master device then outputs the 7-bit slave address and transmit/receive direction (r/w), in synchronization with the transmit clock pulses. 4. when the slave address matches in the first frame following the start condition, the device operates as the slave device specified by the master device. if the 8th data bit (r/ : ) is 0, the trs bit remains cleared to 0, and slave receive operation is performed. if the 8th data bit (r/ : ) is 1, the trs bit is set to 1, and slave transmit operation is performed. when the slave address does not match, receive operation is halted until the next start condition is detected. 5. at the 9th clock pulse of the receive frame, the slave device returns the data in the ackb bit as an acknowledge signal. 6. at the rise of the 9th clock pulse, the iric flag is set to 1. if the ieic bit has been set to 1, an interrupt request is sent to the cpu. if the aasx bit has been set to 1, irtr flag is also set to 1. 7. at the rise of the 9th clock pulse, the receive data is transferred from icdrs to icdrr, setting the icdrf flag to 1. the slave device drives scl low from the fall of the 9th receive clock pulse until data is read from icdr. 8. confirm that the stop bit is cleared to 0, and clear the iric flag to 0. 9. if the next frame is the last receive frame, set the ackb bit to 1. 10. if icdr is read, the icdrf flag is cleared to 0, releasing the scl bus line. this enables the master device to transfer the next data. receive operations can be performed continuously by repeating steps [5] to [10]. 11. when the stop condition is detected (sda is changed from low to high when scl is high), the bbsy flag is cleared to 0 and the stop bit is set to 1. if the stopim bit has been cleared to 0, the iric flag is set to 1. 12. confirm that the stop bit is set to 1, and clear the iric flag to 0. rev. 2.0, 08/02, page 440 of 788 sda (master output) sda (slave output) 2 1 2 1 4 36 58 79 bit 7 bit 6 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 icdrf iric icdrs icdrr scl (master output) scl (slave output) address +r/ address +r/ undefined value [8] iric clear [10] icdr read (dummy read) user processing 2 1 2 1 4 36 58 79 scl (pin waveform) start condition generation slave address data 1 [6] a r/ [7] scl is fixed low until icdr is read [2] icdr read interrupt request occurrence figure 16.19 example of slave receive mode operation timing (1) (mls = 0, hnds= 1) sda (master output) sda (slave output) 2 14 36 58 79 89 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 icdrf icdrs icdrr iric scl (master output) scl (slave output) [8] iric clear [12] iric clear [9] set ackb=1 [5] icdr read ( data (n- 1)) [10] icdr read ( data (n )) user processing data (n ) data (n- 1) data (n-2 ) [6] [6] [11] a a stop condition generation [7] scl is fixed low until icdr is read [7] scl is fixed low until icdr is read data (n- 1) data (n ) data (n ) [8] iric clear data (n- 1) figure 16.20 example of slave receive mode operation timing (2) (mls = 0, hnds= 1) rev. 2.0, 08/02, page 441 of 788 continuous receive operation: figure 16.21 shows the sample flowchart for the operations in slave receive mode (hnds = 0). slave receive mode end read iric in iccr clear iric in iccr clear iric in iccr read aasx, aas and adz in icsr read trs in iccr read iric in iccr clear iric in iccr clear iric in iccr read icdr wait for one frame read icdr set ackb = 0 in icsr set ackb = 1 in icsr set hnds = 0 in icxr general call address processing * description omitted set mst = 0 and trs = 0 in iccr iric = 1? no yes icdrf = 1? yes trs = 1? iric = 1? icdrf = 1? yes yes no no yes no aas = 1 and adz = 1? no no [1] select slave receive mode. [2] read the receive data remaining unread. [3] to [7] wait for one byte to be received (slave address + r/w) (set iric at the rise of the 9th clock) [9] wait for ackb setting and set acknowledge data for the last reception (after the rise of the 9th clock of (n-1)th byte data) [15] clear iric [14] read the last receive data [8] clear iric [13] clear iric [10] read the receive data. the first read is a dummy read. [11] wait for one byte to be received (set iric at the rise of the 9th clock) [12] detect stop condition slave transmit mode yes no no read icdr no yes icdrf = 1? (n-2)th-byte reception? estp = 1 or stop = 1? * n: address + total number of bytes received figure 16.21 sample flowchart for operations in slave receive mode (hnds = 0) rev. 2.0, 08/02, page 442 of 788 the reception procedure and operations in slave receive are described below. 1. initialize the iic as described in section 16.4.2, initialization. clear the mst and trs bits to 0 to set slave receive mode, and set the hnds and ackb bits to 0. clear the iric flag in iccr to 0 to see the end of reception. 2. confirm that the icdrf flag is 0. if the icdrf flag is set to 1, read the icdr and then clear the iric flag to 0. 3. when the start condition output by the master device is detected, the bbsy flag in iccr is set to 1. the master device then outputs the 7-bit slave address and transmit/receive direction (r/w) in synchronization with the transmit clock pulses. 4. when the slave address matches in the first frame following the start condition, the device operates as the slave device specified by the master device. if the 8th data bit (r/ : ) is 0, the trs bit remains cleared to 0, and slave transmit operation is performed. when the slave address does not match, receive operation is halted until the next start condition is detected. 5. at the 9th clock pulse of the receive frame, the slave device returns the data in the ackb bit as an acknowledge signal. 6. at the rise of the 9th clock pulse, the iric flag is set to 1. if the ieic bit has been set to 1, an interrupt request is sent to the cpu. if the aasx bit has been set to 1, the irtr flag is also set to 1. 7. at the rise of the 9th clock pulse, the receive data is transferred from icdrs to icdrr, setting the icdrf flag to 1. 8. confirm that the stop bit is cleared to 0 and clear the icic flag to 0. 9. if the next read data is the third last receive frame, wait for at least one frame time to set the ackb bit. set the ackb bit after the rise of the 9th clock pulse of the second last receive frame. 10. confirm that the icdrf flag is set to 1 and read icdr. this clears the icdrf flag to 0. 11. at the rise of the 9th clock pulse or when the receive data is transferred from irdrs to icdrr due to icdr read operation, the iric and icdrf flags are set to 1. 12. when the stop condition is detected (sda is changed from low to high when scl is high), the bbsy flag is cleared to 0 and the stop or estp flag is set to 1. if the stopim bit has been cleared to 0, the iric flag is set to 1. in this case, execute step [14] to read the last receive data. 13. clear the iric flag to 0. receive operations can be performed continuously by repeating steps [9] to [13]. 14. confirm that the icdrf flag is set to 1, and read icdr. 15. clear the iric flag. rev. 2.0, 08/02, page 443 of 788 sda (master output) sda (slave output) 2 14 32 14 3 6 58 79 bit 7 bit 6 bit 7 bit 6 bit 5 bit 4 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 icdrf icdrs icdrr iric scl (master output) start condition issuance address+r/ data 1 address+r/ [8] iric clear [10] icdr read user processing slave address [6] [7] a r/ data 1 figure 16.22 example of slave receive mode operation timing (1) (mls = ackb = 0) start condition detection sda (master output) sda (slave output) 2 14 36 5 2 14 36 58 79 8 79 89 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 1 bit 0 icdrf icdrs icdrr iric scl (master output) [9] set ackb = 1 [13] iric clear [10] icdr read (data n-2) [10] icdr read (data n-1) [13] iric clear [9] wait for one frame user processing bit 7 bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 data n data n-1 data n-1 data n-1 data n-2 data n-2 data n data n data n-2 [11] [11] [11] a aa [13] iric clear [14] icdr read (data n) [15] iric clear [11] figure 16.23 example of slave receive mode operation timing (2) (mls = ackb = 0) rev. 2.0, 08/02, page 444 of 788 16.4.6 slave transmit operation if the slave address matches to the address in the first frame (address reception frame) following the start condition detection when the 8th bit data (r/ : ) is 1 (read), the trs bit in iccr is automatically set to 1 and the mode changes to slave transmit mode. figure 16.24 shows the sample flowchart for the operations in slave transmit mode. end write transmit data in icdr clear iric in iccr clear iric in iccr clear acke to 0 in iccr (ackb=0 clear) clear iric in iccr read iric in iccr read ackb in icsr set trs = 0 in iccr read icdr read iric in iccr iric = 1? yes yes no no iric = 1? yes no [1], [2] if the slave address matches to the address in the first frame following the start condition detection and the r/ bit is 1 in slave recieve mode, the mode changes to slave transmit mode. [8] set slave receive mode. [6] read iric in iccr [7] clear acknowledge bit data [9] dummy read (to release the scl line). [10] wait for stop condition [3], [5] set transmit data for the second and subsequent bytes. [3], [4] wait for 1 byte to be transmitted. [4] determine end of transfer. slave transmit mode end of transmission (ackb = 1)? clear iric in iccr figure 16.24 sample flowchart for slave transmit mode rev. 2.0, 08/02, page 445 of 788 in slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. the transmission procedure and operations in slave transmit mode are described below. 1. initialize slave receive mode and wait for slave address reception. 2. when the slave address matches in the first frame following detection of the start condition, the slave device drives sda low at the 9th clock pulse and returns an acknowledge signal. if the 8th data bit (r/w) is 1, the trs bit in iccr is set to 1, and the mode changes to slave transmit mode automatically. the iric flag is set to 1 at the rise of the 9th clock. if the ieic bit in iccr has been set to 1, an interrupt request is sent to the cpu. at the same time, the icdre flag is set to 1. the slave device drives scl low from the fall of the transmit clock until icdr data is written, to disable the master device to output the next transfer clock. 3. after clearing the iric flag to 0, write data to icdr. at this time, the icdre flag is cleared to 0. the written data is transferred to icdrs, and the icdre and iric flags are set to 1 again. the slave device sequentially sends the data written into icdrs in accordance with the clock output by the master device. the iric flag is cleared to 0 to detect the end of transmission. processing from the icdr register writing to the iric flag clearing should be performed continuously. prevent any other interrupt processing from being inserted. 4. the master device drives sda low at the 9th clock pulse, and returns an acknowledge signal. as this acknowledge signal is stored in the ackb bit in icsr, this bit can be used to determine whether the transfer operation was performed successfully. when one frame of data has been transmitted, the iric flag in iccr is set to 1 at the rise of the 9th transmit clock pulse. when the icdre flag is 0, the data written into icdr is transferred to icdrs, transmission starts, and the icdre and iric flags are set to 1 again. if the icdre flag has been set to 1, this slave device drives scl low from the fall of the transmit clock until data is written to icdr. 5. to continue transmission, write the next data to be transmitted into icdr. the icdre flag is cleared to 0. the iric flag is cleared to 0 to detect the end of transmission. processing from the icdr register writing to the iric flag clearing should be performed continuously. prevent any other interrupt processing from being inserted. transmit operations can be performed continuously by repeating steps [4] and [5]. 6. clear the iric flag to 0. 7. to end transmission, clear the acke bit in iccr to 0, to clear the acknowledge bit stored in the ackb bit to 0. 8. clear the trs bit to 0 for the next address reception, to set slave receive mode. 9. dummy-read icdr to release sda on the slave side. 10. when the stop condition is detected, that is, when sda is changed from low to high when scl is high, the bbsy flag in iccr is cleared to 0 and the stop flag in icsr is set to 1. when the rev. 2.0, 08/02, page 446 of 788 stopim bit in icxr is 0, the iric flag is set to 1. if the iric flag has been set, it is cleared to 0. sda (master output) sda (slave output) 2 1 2 1 4 36 58 79 9 8 bit 7 bit 6 bit 5 bit 7 bit 6 bit 4 bit 3 bit 2 bit 1 bit 0 icdre icdr iric scl (master output) slave receive mode slave transmit mode [3] icdr write user processing data 1 data 1 data 2 data 2 a r/ a [4] [3] iric clear [3] iric clear [5] iric clear [5] icdr write [2] figure 16.25 example of slave transmit mode operation timing (mls = 0) 16.4.7 iric setting timing and scl control the interrupt request flag (iric) is set at different times depending on the wait bit in icmr, the fs bit in sar, and the fsx bit in sarx. if the icdre or icdrf flag is set to 1, scl is automatically held low after one frame has been transferred in synchronization with the internal clock. figures 16.26 to 16.28 show the iric set timing and scl control. rev. 2.0, 08/02, page 447 of 788 scl sda iric user processing clear iric 23 1 a 8 7 3 2 1 9 8 7 when wait = 0, and fs = 0 or fsx = 0 (i 2 c bus format, no wait) (a) data transfer ends with icdre=0 at transmission, or icdrf=0 at reception. (b) data transfer ends with icdre=1 at transmission, or icdrf=1 at reception. scl sda iric user processing clear iric clear iric write to icdr (transmit) or read from icdr (receive) 1 a 8 7 1 9 8 7 figure 16.26 iric setting timing and scl control (1) rev. 2.0, 08/02, page 448 of 788 scl sda iric user processing clear iric 2 13 a 8 123 9 8 clear iric when wait = 1, and fs = 0 or fsx = 0 (i 2 c bus format, wait inserted) scl sda iric user processing clear iric write to icdr (transmit) or read from icdr (receive) 1 a 8 1 9 8 clear iric (a) data transfer ends with icdre=0 at transmission, or icdrf=0 at reception. (b) data transfer ends with icdre=1 at transmission, or icdrf=1 at reception. figure 16.27 iric setting timing and scl control (2) rev. 2.0, 08/02, page 449 of 788 scl sda iric user processing clear iric 1 8 7 4 123 8 7 when fs = 1 and fsx = 1 (clocked synchronous serial format) (a) data transfer ends with icdre=0 at transmission, or icdrf=0 at reception. scl sda iric user processing clear iric clear iric write to icdr (transmit) or read from icdr (receive) 8 72 14 3 1 8 7 (b) data transfer ends with icdre=1 at transmission, or icdrf=1 at reception. figure 16.28 iric setting timing and scl control (3) 16.4.8 automatic switching from formatless mode to i 2 c bus format setting the sw bit to 1 in ddcswr enables formatless mode to be selected as the iic_0 operating mode. switching from formatless mode to the i 2 c bus format (slave mode) is performed automatically when a falling edge is detected on the scl pin. the following four preconditions are necessary for this operation: a common data pin (sda) for formatless and i 2 c bus format operation separate clock pins for formatless operation (vsynci) and i 2 c bus format operation (scl) a fixed 1 level for the scl pin during formatless operation (the scl pin does not output a low level) settings of bits other than trs in iccr that allow i 2 c bus format operation rev. 2.0, 08/02, page 450 of 788 automatic switching is performed from formatless mode to the i 2 c bus format when the sw bit in ddcswr is automatically cleared to 0 on detection of a falling edge on the scl pin. switching from the i 2 c bus format to formatless mode is achieved by setting the sw bit in ddcswr to 1 by software. in formatless mode, bits (such as msl and trs) that control the i 2 c bus interface operating mode must not be modified. when switching from the i 2 c bus format to formatless mode, set the trs bit to 1 or clear it to 0 according to the transfer direction (transmission or reception) in formatless mode, then set the sw bit to 1. after automatic switching from formatless mode to the i 2 c bus format (slave mode), the trs bit is automatically cleared to 0 in order to wait for slave address reception. if a falling edge is detected on the scl pin during formatless operation, the mode of the i 2 c bus interface is immediately switched to i 2 c bus format before a stop condition is detected. 16.4.9 operation using dtc this lsi provides the dtc to allow continuous data transfer. the dtc is initiated when the irtr flag is set to 1, which is one of the two interrupt flags (irtr and iric). when the acke bit is 0, the icdre, iric, and irtr flags are set at the end of data transmission regardless of the acknowledge bit value. if the acke bit is 1, the icdre, iric, and irtr flags are set when data transmission is completed with the acknowledge bit value of 0, and if the acke bit is 1, only the iric flag is set when data transmission is completed with the acknowledge bit value of 1. when initiated, the dtc transfers specified number of bytes, clears the icdre, iric, and irtr flags to 0. therefore, no interrupt is generated during continuous data transfer; however, if data transmission is completed with the acknowledge bit value of 1 when the acke bit is 1, the dtc is not initiated, thus allowing an interrupt to be generated if enabled. the acknowledge bit may indicate specific events such as completion of receive data processing for some receiving devices, and for other receiving devices, the acknowledge bit may be fixed at 1, indicating no specific events. the i 2 c bus format provides for selection of the slave device and transfer direction by means of the slave address and the r/ : bit, confirmation of reception with the acknowledge bit, indication of the last frame, and so on. therefore, continuous data transfer using the dtc must be carried out in conjunction with cpu processing by means of interrupts. table 16.7 shows some examples of processing using the dtc. these examples assume that the number of transfer data bytes is known in slave mode. rev. 2.0, 08/02, page 451 of 788 table 16.7 examples of operation using dtc item master transmit mode master receive mode slave transmit mode slave receive mode slave address + r/ : bit transmission/ reception transmission by dtc (icdr write) transmission by cpu (icdr write) reception by cpu (icdr read) reception by cpu (icdr read) dummy data read processing by cpu (icdr read) actual data transmission/ reception transmission by dtc (icdr write) reception by dtc (icdr read) transmission by dtc (icdr write) reception by dtc (icdr read) dummy data (h'ff) write processing by dtc (icdr write) last frame processing not necessary reception by cpu (icdr read) not necessary reception by cpu (icdr read) transfer request processing after last frame processing 1st time: clearing by cpu 2nd time: stop condition issuance by cpu not necessary automatic clearing on detection of stop condition during transmission of dummy data (h'ff) not necessary setting of number of dtc transfer data frames transmission: actual data count + 1 (+1 equivalent to slave address + r/ : bits) reception: actual data count transmission: actual data count + 1 (+1 equivalent to dummy data (h'ff)) reception: actual data count 16.4.10 noise canceler the logic levels at the scl and sda pins are routed through noise cancelers before being latched internally. figure 16.29 shows a block diagram of the noise canceler. the noise canceler consists of two cascaded latches and a match detector. the scl (or sda) pin input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. if they do not agree, the previous value is held. rev. 2.0, 08/02, page 452 of 788 system clock cycle sampling clock c dq latch c dq latch scl or sda input signal match detector internal scl or sda signal sampling clock figure 16.29 block diagram of noise canceler 16.4.11 initialization of internal state the iic has a function for forcible initialization of its internal state if a deadlock occurs during communication. initialization is executed in accordance with the setting of bits clr3 to clr0 in ddcswr or clearing ice bit. for details on the setting of bits clr3 to clr0, see section 16.3.7, ddc switch register (ddcswr). scope of initialization: the initialization executed by this function covers the following items: icdre and icdrf internal flags transmit/receive sequencer and internal operating clock counter internal latches for retaining the output state of the scl and sda pins (wait, clock, data output, etc.) the following items are not initialized: actual register values (icdr, sar, sarx, icmr, iccr, icsr, icxr (except for the icdre and icdrf flags), ddcswr) internal latches used to retain register read information for setting/clearing flags in icmr, iccr, icsr, and ddcswr the value of the icmr bit counter (bc2 to bc0) generated interrupt sources (interrupt sources transferred to the interrupt controller) rev. 2.0, 08/02, page 453 of 788 notes on initialization: interrupt flags and interrupt sources are not cleared, and so flag clearing measures must be taken as necessary. basically, other register flags are not cleared either, and so flag clearing measures must be taken as necessary. when initialization is executed by ddcswr, the write data for bits clr3 to clr0 is not retained. to perform iic clearance, bits clr3 to clr0 must be written to simultaneously using an mov instruction. do not use a bit manipulation instruction such as bclr. similarly, when clearing is required again, all the bits must be written to simultaneously in accordance with the setting. if a flag clearing setting is made during transmission/reception, the iic module will stop transmitting/receiving at that point and the scl and sda pins will be released. when transmission/reception is started again, register initialization, etc., must be carried out as necessary to enable correct communication as a system. the value of the bbsy bit cannot be modified directly by this module clear function, but since the stop condition pin waveform is generated according to the state and release timing of the scl and sda pins, the bbsy bit may be cleared as a result. similarly, state switching of other bits and flags may also have an effect. to prevent problems caused by these factors, the following procedure should be used when initializing the iic state. 1. execute initialization of the internal state according to the setting of bits clr3 to clr0 or ice bit clearing. 2. execute a stop condition issuance instruction (write 0 to bbsy and scp) to clear the bbsy bit to 0, and wait for two transfer rate clock cycles. 3. re-execute initialization of the internal state according to the setting of bits clr3 to clr0 or ice bit clearing. 4. initialize (re-set) the iic registers. rev. 2.0, 08/02, page 454 of 788 16.5 interrupt sources the iic has interrupt sources iici and ddcswi. table 16.8 shows the interrupt sources and priority. individual interrupt sources can be enabled or disabled using the enable bits in iccr and ddcswr, and are sent to the interrupt controller independently. an iici interrupt can activate the dtc to allow data transfer. table 16.8 iic interrupt sources channel name enable bit interrupt source interrupt flag dtc activation priority iici0 ieic i 2 c bus interface interrupt request iric possible high 0 ddcs wi ie format automatic switch interrupt if not possible 1 iici1 ieic i 2 c bus interface interrupt request iric possible low 16.6 usage notes 1. in master mode, if an instruction to generate a start condition is issued and then an instruction to generate a stop condition is issued before the start condition is output to the i 2 c bus, neither condition will be output correctly. to output the start condition followed by the stop condition, after issuing the instruction that generates the start condition, read dr in each i 2 c bus output pin, and check that scl and sda are both low. the pin states can be monitored by reading dr even if the ice bit is set to 1. then issue the instruction that generates the stop condition. note that scl may not yet have gone low when bbsy is cleared to 0. 2. either of the following two conditions will start the next transfer. pay attention to these conditions when accessing to icdr. ? write to icdr when ice = 1 and trs = 1 (including automatic transfer from icdrt to icdrs) ? read from icdr when ice = 1 and trs = 0 (including automatic transfer from icdrs to icdrr) 3. table 16.9 shows the timing of scl and sda outputs in synchronization with the internal clock. timings on the bus are determined by the rise and fall times of signals affected by the bus load capacitance, series resistance, and parallel resistance. rev. 2.0, 08/02, page 455 of 788 table 16.9 i 2 c bus timing (scl and sda outputs) item symbol output timing unit notes scl output cycle time t sclo 28t cyc to 256t cyc ns scl output high pulse width t sclho 0.5t sclo ns scl output low pulse width t scllo 0.5t sclo ns sda output bus free time t bufo 0.5t sclo C 1t cyc ns start condition output hold time t staho 0.5t sclo C 1t cyc ns retransmission start condition output setup time t staso 1t sclo ns stop condition output setup time t stoso 0.5t sclo + 2t cyc ns data output setup time (master) 1t scllo C 3t cyc data output setup time (slave) t sdaso 1t scll C (6t cyc or 12t cyc * ) ns data output hold time t sdaho 3t cyc ns see figure 28.29. note: * 6t cyc when iicx is 0, 12t cyc when 1. 4. scl and sda inputs are sampled in synchronization with the internal clock. the ac timing therefore depends on the system clock cycle t cyc , as shown in section 28, electrical characteristics. note that the i 2 c bus interface ac timing specifications will not be met with a system clock frequency of less than 5 mhz. 5. the i 2 c bus interface specification for the scl rise time t sr is 1000 ns or less (300 ns for high- speed mode). in master mode, the i 2 c bus interface monitors the scl line and synchronizes one bit at a time during communication. if t sr (the time for scl to go from low to v ih ) exceeds the time determined by the input clock of the i 2 c bus interface, the high period of scl is extended. the scl rise time is determined by the pull-up resistance and load capacitance of the scl line. to insure proper operation at the set transfer rate, adjust the pull-up resistance and load capacitance so that the scl rise time does not exceed the values given in table 16.10. table 16.10 permissible scl rise time (t sr ) values time indication [ns] iicx t cyc indication i 2 c bus specification (max.) ? = 5 mhz ? = 8 mhz ? = 10 mhz ? = 16 mhz ? = 20 mhz standard mode 1000 1000 937 750 468 375 0 7.5 t cyc high-speed mode 300 300 300 300 300 300 standard mode 1000 100 1000 1000 1000 875 1 17.5 t cyc high-speed mode 300 300 300 300 300 300 rev. 2.0, 08/02, page 456 of 788 6. the i 2 c bus interface specifications for the scl and sda rise and fall times are under 1000 ns and 300 ns. the i 2 c bus interface scl and sda output timing is prescribed by t cyc , as shown in table 16.9. however, because of the rise and fall times, the i 2 c bus interface specifications may not be satisfied at the maximum transfer rate. table 16.11 shows output timing calculations for different operating frequencies, including the worst-case influence of rise and fall times. t bufo fails to meet the i 2 c bus interface specifications at any frequency. the solution is either (a) to provide coding to secure the necessary interval (approximately 1 s) between issuance of a stop condition and issuance of a start condition, or (b) to select devices whose input timing permits this output timing for use as slave devices connected to the i 2 c bus. t scllo in high-speed mode and t staso in standard mode fail to satisfy the i 2 c bus interface specifications for worst-case calculations of t sr /t sf . possible solutions that should be investigated include (a) adjusting the rise and fall times by means of a pull-up resistor and capacitive load, (b) reducing the transfer rate to meet the specifications, or (c) selecting devices whose input timing permits this output timing for use as slave devices connected to the i 2 c bus. rev. 2.0, 08/02, page 457 of 788 table 16.11 i 2 c bus timing (with maximum influence of t sr /t sf ) time indication (at maximum transfer rate) [ns] item t cyc indication t sr /t sf influence (max.) i 2 c bus specifi- cation (min.) ? = 5 mhz ? = 8 mhz ? = 10 mhz ? = 16 mhz ? = 20 mhz standard mode C1000 4000 4000 4000 4000 4000 4000 t sclho 0.5 t sclo (Ct sr ) high-speed mode C300 600 950 950 950 950 950 standard mode C250 4700 4750 4750 4750 4750 4750 t scllo 0.5 t sclo (Ct sf ) high-speed mode C250 1300 1000 * 1 1000 * 1 1000 * 1 1000 * 1 1000 * 1 standard mode C1000 4700 3800 * 1 3875 * 1 3900 * 1 3938 * 1 3950 * 1 t bufo 0.5 t sclo C1 t cyc (Ct sr ) high-speed mode C300 1300 750 * 1 825 * 1 850 * 1 888 * 1 900 * 1 standard mode C250 4000 4550 4625 4650 4688 4700 t staho 0.5 t sclo C1 t cyc (Ct sf ) high-speed mode C250 600 800 875 900 938 950 standard mode C1000 4700 9000 9000 9000 9000 9000 t staso 1 t sclo (Ct sr ) high-speed mode C300 600 2200 2200 2200 2200 2200 standard mode C1000 4000 4400 4250 4200 4125 4100 t stoso 0.5 t sclo + 2 t cyc (Ct sr ) high-speed mode C300 600 1350 1200 1150 1075 1050 standard mode C1000 250 3100 3325 3400 3513 3550 t sdaso (master) 1 t scllo * 3 C3 t cyc (Ct sr ) high-speed mode C300 100 400 625 700 813 850 standard mode C1000 250 1300 2200 2500 2950 3100 t sdaso (slave) 1 t scll * 3 C12 t cyc * 2 (Ct sr ) high-speed mode C300 100 C1400 * 1 C500 * 1 C200 * 1 250 400 standard mode 0 0 600 375 300 188 150 t sdaho 3 t cyc high-speed mode 0 0 600 375 300 188 150 notes: 1. does not meet the i 2 c bus interface specification. remedial action such as the following is necessary: (a) secure a start/stop condition issuance interval; (b) adjust the rise and fall times by means of a pull-up resistor and capacitive load; (c) reduce the transfer rate; (d) select slave devices whose input timing permits this output timing. the values in the above table will vary depending on the settings of the iicx bit and bits cks0 to cks2. depending on the frequency it may not be possible to achieve the maximum transfer rate; therefore, whether or not the i 2 c bus interface specifications are met must be determined in accordance with the actual setting conditions. 2. value when the iicx bit is set to 1. when the iicx bit is cleared to 0, the value is (t scll C 6t cyc ). 3. calculated using the i 2 c bus specification values (standard mode: 4700 ns min.; high- speed mode: 1300 ns min.). 7. notes on icdr read at end of master reception rev. 2.0, 08/02, page 458 of 788 to halt reception at the end of a receive operation in master receive mode, set the trs bit to 1 and write 0 to bbsy and scp in iccr. this changes sda from low to high when scl is high, and generates the stop condition. after this, receive data can be read by means of an icdr read, but if data remains in the buffer the icdrs receive data will not be transferred to icdr (icdrr), and so it will not be possible to read the second byte of data. if it is necessary to read the second byte of data, issue the stop condition in master receive mode (i.e. with the trs bit cleared to 0). when reading the receive data, first confirm that the bbsy bit in iccr is cleared to 0, the stop condition has been generated, and the bus has been released, then read icdr with trs cleared to 0. note that if the receive data (icdr data) is read in the interval between execution of the instruction for issuance of the stop condition (writing of 0 to bbsy and scp in iccr) and the actual generation of the stop condition, the clock may not be output correctly in subsequent master transmission. clearing of the mst bit after completion of master transmission/reception, or other modifications of iic control bits to change the transmit/receive operating mode or settings, must be carried out during interval (a) in figure 16.30 (after confirming that the bbsy bit in iccr has been cleared to 0). sda scl internal clock bbsy bit master receive mode icdr read disabled period bit 0 a 8 9 stop condition (a) start condition execution of instruction for issuing stop condition (write 0 to bbsy and scp) confirmation of stop condition issuance (read bbsy = 0) start condition issuance figure 16.30 notes on reading master receive data note: this restriction on usage can be canceled by setting the fnc1 and fnc0 bits to 1 in icxr. 8. notes on start condition issuance for retransmission rev. 2.0, 08/02, page 459 of 788 figure 16.31 shows the timing of start condition issuance for retransmission, and the timing for subsequently writing data to icdr, together with the corresponding flowchart. write the transmit data to icdr after the start condition for retransmission is issued and then the start condition is actually generated. sda iric scl [3] (retransmission) start condition instruction issuance [4] iric determination [5] icdr write (transmit data) [2] determination of scl = low [1] iric determination start condition generation (retransmission) iric = 1? yes clear iric in icsr read scl pin write transmit data to icdr set bbsy = 1, scp = 0 (icsr) [1] [1] wait for end of 1-byte transfer [2] determine whether scl is low [3] issue start condition instruction for retransmission [4] determine whether start condition is generated or not [5] set transmit data (slave address + r/ ) [2] [3] [4] [5] yes yes no no iric = 1? yes scl = low? start condition issuance? no no other processing note: * program so that processing from [3] to [5] is executed continuously. bit7 ack 9 figure 16.31 flowchart for start condition issuance instruction for retransmission and timing note: this restriction on usage can be canceled by setting the fnc1 and fnc0 bits to 1 in icxr. rev. 2.0, 08/02, page 460 of 788 9. note on when i 2 c bus interface stop condition instruction is issued in cases where the rise time of the 9th clock of scl exceeds the stipulated value because of a large bus load capacity or where a slave device in which a wait can be inserted by driving the scl pin low is used, the stop condition instruction should be issued after reading scl after the rise of the 9th clock pulse and determining that it is low. stop condition generation scl iric [1] scl = low determination vih [2] stop condition instruction issuance sda 9th clock secures a high period scl is detected as low because the rise of the waveform is delayed figure 16.32 stop condition issuance timing note: this restriction on usage can be canceled by setting the fnc1 and fnc0 bits to 1 in icxr. 10. note on iric flag clear when the wait function is used if the rise time of scl exceeds the stipulated value or a slave device in which a wait can be inserted by driving the scl pin low is used when the wait function is used in i 2 c bust interface master mode, the iric flag should be cleared after determining that the scl is low, as described below. if the iric flag is cleared to 0 when wait = 1 while the scl is extending the high level time, the sda level may change before the scl goes low, which may generate a start or stop condition erroneously. scl iric [1] scl = low determination vih [2] iric clear sda secures a high period scl = low detected figure 16.33 iric flag clearing timing when wait = 1 rev. 2.0, 08/02, page 461 of 788 note: this restriction on usage can be canceled by setting the fnc1 and fnc0 bits to 1 in icxr. 11. note on icdr read and iccr access in slave transmit mode in i 2 c bus interface slave transmit mode, do not read icdr or do not read/write from/to iccr during the time shaded in figure 16.34. however, such read and write operations cause no problem in interrupt handling processing that is generated in synchronization with the rising edge of the 9th clock pulse because the shaded time has passed before making the transition to interrupt handling. to handle interrupts securely, be sure to keep either of the following conditions. ? read icdr data that has been received so far or read/write from/to iccr before starting the receive operation of the next slave address. ? monitor the bc2 to bc0 bit counter in icmr; when the count is 000 (8th or 9th clock pulse), wait for at least two transfer clock times in order to read icdr or read/write from/to iccr during the time other than the shaded time. data transmission bit 7 address reception scl trs bit waveform at problem occurrence icdr read and iccr read/write are disabled (6 system clock period) 8 r/w a 9 the rise of the 9th clock is detected sda icdr write figure 16.34 icdr read and iccr access timing in slave transmit mode note: this restriction on usage can be canceled by setting the fnc1 and fnc0 bits to 1 in icxr. rev. 2.0, 08/02, page 462 of 788 12. note on trs bit setting in slave mode in i 2 c bus interface slave mode, if the trs bit value in iccr is set after detecting the rising edge of the 9th clock pulse or the stop condition before detecting the next rising edge on the scl pin (the time indicated as (a) in figure 16.35), the bit value becomes valid immediately when it is set. however, if the trs bit is set during the other time (the time indicated as (b) in figure 16.35), the bit value is suspended and remains invalid until the rising edge of the 9th clock pulse or the stop condition is detected. therefore, when the address is received after the restart condition is input without the stop condition, the effective trs bit value remains 1 (transmit mode) internally and thus the acknowledge bit is not transmitted after the address has been received at the 9th clock pulse. to receive the address in slave mode, clear the trs bit to 0 during the time indicated as (a) in figure 16.35. to release the scl low level that is held by means of the wait function in slave mode, clear the trs bit to and then dummy-read icdr. restart condition data transmission address reception scl trs trs bit setting is suspended in this period icdr dummy read trs bit setting (a) (b) 8 a 9 123 456789 the rise of the 9th clock is detected sda the rise of the 9th clock is detected figure 16.35 trs bit set timing in slave mode note: this restriction on usage can be canceled by setting the fnc1 and fnc0 bits to 1 in icxr. 13. note on icdr read in transmit mode and icdr write in receive mode if icdr is read in transmit mode (trs = 1) or icdr is written to in receive mode (trs = 0), the scl pin may not be held low in some cases after transmit/receive operation has been completed, thus inconveniently allowing clock pulses to be output on the scl bus line before icdr is accessed correctly. to access icdr correctly, read icdr after setting receive mode or write to icdr after setting transmit mode. rev. 2.0, 08/02, page 463 of 788 14. note on acke and trs bits in slave mode in the i 2 c bus interface, if 1 is received as the acknowledge bit value (ackb = 1) in transmit mode (trs = 1) and then the address is received in slave mode without performing appropriate processing, interrupt handling may start at the rising edge of the 9th clock pulse even when the address does not match. similarly, if the start condition or address is transmitted from the master device in slave transmit mode (trs = 1), the iric flag may be set after the icdre flag is set and 1 received as the acknowledge bit value (ackb = 1), thus causing an interrupt source even when the address does not match. to use the i 2 c bus interface module in slave mode, be sure to follow the procedures below. a. when having received 1 as the acknowledge bit value for the last transmit data at the end of a series of transmit operation, clear the acke bit in iccr once to initialize the ackb bit to 0. b. set receive mode (trs = 0) before the next start condition is input in slave mode. complete transmit operation by the procedure shown in figure 16.24, in order to switch from slave transmit mode to slave receive mode. 16.6.1 module stop mode setting the iic operation can be enabled or disabled using the module stop control register. the initial setting is for the iic operation to be halted. register access is enabled by canceling module stop mode. for details, refer to section 26, power-down modes. rev. 2.0, 08/02, page 464 of 788 rev. 2.0, 08/02, page 465 of 788 section 17 keyboard buffer controller this lsi has three on-chip keyboard buffer controller channels. the keyboard buffer controller is provided with functions conforming to the ps/2 interface specifications. data transfer using the keyboard buffer controller employs a data line (kd) and a clock line (kclk), providing economical use of connectors, board surface area, etc. figure 17.1 shows a block diagram of the keyboard buffer controller. 17.1 features conforms to ps/2 interface specifications direct bus drive (via the kclk and kd pins) interrupt sources: on completion of data reception and on detection of clock edge error detection: parity error and stop bit monitoring kd (ps2ad, ps2bd, ps2cd) kdi kclki kdo kclko parity register counter value kbi interrupt kclk (ps2ac, ps2bc, ps2cc) legend kd: kbc data i/o pin kclk: kbc clock i/o pin kbbr: keyboard data buffer register kbcrh: keyboard control register h kbcrl: keyboard control register l control logic kbbr kbcrh kbcrl bus interface internal data bus module data bus figure 17.1 block diagram of keyboard buffer controller ifkey10a_000020020700 rev. 2.0, 08/02, page 466 of 788 figure 17.2 shows how the keyboard buffer controller is connected. vcc kclk in kclk out kd in kd out keyboard buffer controller (this lsi) system side kclk in kclk out kd in kd out i/f keyboard side vcc clock data figure 17.2 keyboard buffer controller connection 17.2 input/output pins table 17.1 lists the input/output pins used by the keyboard buffer controller. table 17.1 pin configuration channel name abbreviation * i/o function kbc clock i/o pin (kclk0) ps2ac i/o kbc clock input/output 0 kbc data i/o pin (kd0) ps2ad i/o kbc data input/output kbc clock i/o pin (kclk1) ps2bc i/o kbc clock input/output 1 kbc data i/o pin (kd1) ps2bd i/o kbc data input/output kbc clock i/o pin (kclk2) ps2cc i/o kbc clock input/output 2 kbc data i/o pin (kd2) ps2cd i/o kbc data input/output note: * these are the external i/o pin names. in the text, clock i/o pins are referred to as kclk and data i/o pins as kd, omitting the channel designations. rev. 2.0, 08/02, page 467 of 788 17.3 register descriptions the keyboard buffer controller has the following registers for each channel. keyboard control register h (kbcrh) keyboard control register l (kbcrl) keyboard data buffer register (kbbr) 17.3.1 keyboard control register h (kbcrh) kbcrh indicates the operating status of the keyboard buffer controller. bit bit name initial value r/w description 7 kbioe 0 r/w keyboard in/out enable selects whether or not the keyboard buffer controller is used. 0: the keyboard buffer controller is non-operational (kclk and kd signal pins have port functions) 1: the keyboard buffer controller is enabled for transmission and reception (kclk and kd signal pins are in the bus drive state) 6 kclki 1 r/w keyboard clock in monitors the kclk i/o pin. this bit cannot be modified. 0: kclk i/o pin is low 1: kclk i/o pin is high 5 kdi 1 r/w keyboard data in: monitors the kdi i/o pin. this bit cannot be modified. 0: kd i/o pin is low 1: kd i/o pin is high 4 kbfsel 1 r/w keyboard buffer register full select selects whether the kbf bit is used as the keyboard buffer register full flag or as the kclk fall interrupt flag. when kbfsel is cleared to 0, the kbe bit in kbcrl should be cleared to 0 to disable reception. 0: kbf bit is used as kclk fall interrupt flag 1: kbf bit is used as keyboard buffer register full flag rev. 2.0, 08/02, page 468 of 788 bit bit name initial value r/w description 3 kbie 0 r/w keyboard interrupt enable enables or disables interrupts from the keyboard buffer controller to the cpu. 0: interrupt requests are disabled 1: interrupt requests are enabled 2 kbf 0 r/(w) * keyboard buffer register full indicates that data reception has been completed and the received data is in kbbr. 0: [clearing condition] read kbf when kbf =1, then write 0 in kbf 1: [setting conditions] when data has been received normally and has been transferred to kbbr while kbfsel = 1 (keyboard buffer register full flag) when a kclk falling edge is detected while kbfsel = 0 (kclk interrupt flag) 1 per 0 r/(w) * parity error indicates that an odd parity error has occurred. 0: [clearing condition] read per when per =1, then write 0 in per 1: [setting condition] when an odd parity error occurs 0 kbs 0 r keyboard stop indicates the receive data stop bit. valid only when kbf = 1. 0: 0 stop bit received 1: 1 stop bit received note: * only 0 can be written for clearing the flag. rev. 2.0, 08/02, page 469 of 788 17.3.2 keyboard control register l (kbcrl) kbcrl enables the receive counter count and controls the keyboard buffer controller pin output. bit bit name initial value r/w description 7 kbe 0 r/w keyboard enable enables or disables loading of receive data into kbbr. 0: loading of receive data into kbbr is disabled 1: loading of receive data into kbbr is enabled 6 kclko 1 r/w keyboard clock out controls kbc clock i/o pin output. 0: kbc clock i/o pin is low 1: kbc clock i/o pin is high 5 kdo 1 r/w keyboard data out controls kbc data i/o pin output. 0: kbc data i/o pin is low 1: kbc data i/o pin is high 4 1 reserved this bit is always read as 1 and cannot be modified. rev. 2.0, 08/02, page 470 of 788 bit bit name initial value r/w description 3 2 1 0 rxcr3 rxcr2 rxcr1 rxcr0 0 0 0 0 r r r r receive counter these bits indicate the received data bit. their value is incremented on the fall of kclk. these bits cannot be modified. the receive counter is initialized to 0000 by a reset and when 0 is written in kbe. its value returns to 0000 after a stop bit is received. 0000: 0001: start bit 0010: kb0 0011: kb1 0100: kb2 0101: kb3 0110: kb4 0111: kb5 1000: kb6 1001: kb7 1010: parity bit 1011: 11- - : 17.3.3 keyboard data buffer register (kbbr) kbbr stores receive data. its value is valid only when kbf = 1. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 kb7 kb6 kb5 kb4 kb3 kb2 kb1 kb0 0 0 0 0 0 0 0 0 r r r r r r r r keyboard data 7 to 0 8-bit read only data. initialized to h'00 by a reset, in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode, and when kbioe is cleared to 0. rev. 2.0, 08/02, page 471 of 788 17.4 operation 17.4.1 receive operation in a receive operation, both kclk (clock) and kd (data) are outputs on the keyboard side and inputs on this lsi chip (system) side. kd receives a start bit, 8 data bits (lsb-first), an odd parity bit, and a stop bit, in that order. the kd value is valid when kclk is low. a sample receive processing flowchart is shown in figure 17.3, and the receive timing in figure 17.4. start set kbioe bit read kbcrh kclki and kdi bits both 1? set kbe bit receive enabled state kbf = 1? per = 0? kbs = 1? read kbbr receive data processing clear kbf flag (receive enabled state) keyboard side in data transmission state. execute receive abort processing. error handling [1] set the kbioe bit to 1 in kbcrl. [2] read kbcrh, and if the kclki and kdi bits are both 1, set the kbe bit (receive enabled state). [3] detect the start bit output on the keyboard side and receive data in synchronization with the fall of kclk. [4] when a stop bit is received, the keyboard buffer controller drives kclk low to disable keyboard transmission (automatic i/o inhibit). if the kbie bit is set to 1 in kbcrh, an interrupt request is sent to the cpu at the same time. [5] perform receive data processing. [6] clear the kbf flag to 0 in kbcrl. at the same time, the system automatically drives kclk high, setting the receive enabled state. the receive operation can be continued by repeating steps [3] to [6]. [1] [2] [3] [4] [5] [6] yes no yes yes yes no no no figure 17.3 sample receive processing flowchart rev. 2.0, 08/02, page 472 of 788 123 kclk (pin state) kd (pin state) kclk (input) kclk (output) kb7 to kb0 per kbs kbf start bit parity bit stop bit receive processing/ error handling automatic i/o inhibit previous data receive data flag cleared 9 10 11 7 01 kb0 kb1 [1] [2] [3] [4] [5] [6] figure 17.4 receive timing 17.4.2 transmit operation in a transmit operation, kclk (clock) is an output on the keyboard side, and kd (data) is an output on the chip (system) side. kd outputs a start bit, 8 data bits (lsb-first), an odd parity bit, and a stop bit, in that order. the kd value is valid when kclk is high. a sample transmit processing flowchart is shown in figure 17.5, and the transmit timing in figure 17.6. rev. 2.0, 08/02, page 473 of 788 start set kbioe bit kclki = 0? read kbcrh kclki and kdi bits both 1? set i/o inhibit (kclko = 0) kbe = 0 (kbbr reception prohibited) kdo remains at 1 wait set start bit (kdo = 0) set i/o inhibit (kclko = 1) kclko remains at 0 kdo remains at 0 i = 0 read kbcrh set transmit data (kdo = d(i)) read kbcrh kclki = 1? i = i + 1 i > 9? read kbcrh kclki = 1? yes no i = 0 to 7: transmit data i = 8: parity bit i = 9: stop bit no yes yes yes yes no no no 1 2 [1] set the kbe bit to 1 in kbcrh. [2] read kbcrh, and if the kclki and kdi bits are both 1, write 0 in the kclko bit (set i/o inhibit). [3] write 0 in the kbe bit (prohibit kbbr receive operation). [4] write 0 in the kdo bit (set start bit). [5] write 1 in the kclko bit (clear i/o inhibit). [6] read kbcrh, and when kclki = 0, set the transmit data in the kdo bit (lsb-first). next, set the parity bit and stop bit in the kdo bit. [7] after transmitting the stop bit, read kbcrl and confirm that kdi = 0 (receive completed notification from the keyboard). [8] read kbcrh. confirm that the kclki and kdi bits are both 1. the transmit operation can be continued by repeating steps [2] to [8]. [1] [2] [3] [4] [5] [6] (continued on next page) (continued on next page) figure 17.5 (1) sample transmit processing flowchart rev. 2.0, 08/02, page 474 of 788 read kbcrh transmit end state (kclk = high, kd = high) yes note: * to switch to reception after transmission, set kbe to 1 (kbbr receive enable) while kclki is low. 1 kclki = 0? no kdi = 0? read kbcrh kclk = 1? yes yes no no error handling to receive operation or transmit operation keyboard side in data transmission state. execute receive abort processing. 2 * [7] [8] figure 17.5 (2) sample transmit processing flowchart 1 01 01 7 7 2891011 kclk (pin state) kd (pin state) kclk (output) kd (output) kclk (input) kd (input) start bit start bit parity bit stop bit parity bit stop bit i/o inhibit receive completed notification [1] [2] [3] [4] [5] [6] [7] [8] figure 17.6 transmit timing rev. 2.0, 08/02, page 475 of 788 17.4.3 receive abort this lsi (system side) can forcibly abort transmission from the device connected to it (keyboard side) in the event of a protocol error, etc. in this case, the system holds the clock low. during reception, the keyboard also outputs a clock for synchronization, and the clock is monitored when the keyboard output clock is high. if the clock is low at this time, the keyboard judges that there is an abort request from the system, and data transmission from the keyboard is aborted. thus the system can abort reception by holding the clock low for a certain period. a sample receive abort processing flowchart is shown in figure 17.7, and the receive abort timing in figure 17.8. read kbcrl kbf = 0? rxcr3 to rxcr0 3 b'1001? disable receive abort requests yes start receive state read kbcrh processing 1 kclko = 0 (receive abort request) retransmit command transmission (data)? kbe = 0 (disable kbbr reception and clear receive counter) set start bit (kdo = 0) clear i/o inhibit (kclko = 1) transmit data to transmit operation kbe = 0 (disable kbbr reception and clear receive counter) kbe = 1 (enable kb operation) clear i/o inhibit (kclko = 1) to receive operation [1] read kbcrl, and if kbf = 1, perform processing 1. [2] read kbcrh, and if the value of bits rxcr3 to rxcr0 is less than b'1001, write 0 in kclko to abort reception. if the value of bits rxcr3 to rxcr0 is b'1001 or greater, wait until stop bit reception is completed, then perform receive data processing, and proceed to the next operation. [3] if the value of bits rxcr3 to rxcr0 is b'1001 or greater, the parity bit is being received. with the ps2 interface, a receive abort request following parity bit reception is disabled. wait until stop bit reception is completed, perform receive data processing and clear the kbf flag, then proceed to the next operation. yes no no no yes [1] [2] [3] figure 17.7 (1) sample receive abort processing flowchart rev. 2.0, 08/02, page 476 of 788 receive data processing clear kbf flag (kclk = high) processing 1 receive operation ends normally [1] on the system side, drive the kclk pin low, setting the i/o inhibit state. [1] transmit enabled state. if there is transmit data, the data is transmitted. figure 17.7 (2) sample receive abort processing flowchart keyboard side monitors clock during receive operation (transmit operation as seen from keyboard), and aborts receive operation during this period. kclk (pin state) kd (pin state) kclk (input) kclk (output) kd (input) kd (output) reception in progress receive abort request transmit operation start bit figure 17.8 receive abort and transmit start (transmission/reception switchover) timing rev. 2.0, 08/02, page 477 of 788 17.4.4 kclki and kdi read timing figure 17.9 shows the kclki and kdi read timing. t1 t2 ? * internal read signal kclk, kd (pin state) kclki, kdi (register) internal data bus (read data) note: * the ? clock shown here is scaled by 1/n in medium-speed mode when the operating mode is active mode. figure 17.9 kclki and kdi read timing 17.4.5 kclko and kdo write timing figure 17.10 shows the klcko and kdo write timing and the kclk and kd pin states. internal write signal ? * kclko, kdo (register) kclk, kd (pin state) note: * the ? clock shown here is scaled by 1/n in medium-speed mode when the operating mode is active mode. t1 t2 figure 17.10 kclko and kdo write timing rev. 2.0, 08/02, page 478 of 788 17.4.6 kbf setting timing and kclk control figure 17.11 shows the kbf setting timing and the kclk pin states. kclk (pin) ? * internal kclk falling edge signal rxcr3 to rxcr0 kclk (output) kbf 11th fall automatic i/o inhibit b'0000 b'1010 note: * the ? clock shown here is scaled by 1/n in medium-speed mode when the operating mode is active mode. figure 17.11 kbf setting and kclk automatic i/o inhibit generation timing rev. 2.0, 08/02, page 479 of 788 17.4.7 receive timing figure 17.12 shows the receive timing. n + 1 n + 2 n kclk (pin) note: * the ? clock shown here is scaled by 1/n in medium-speed mode when the operating mode is active mode. kd (pin) internal kclk (kclki) falling edge signal rxcr3 to rxcr0 internal kd (kdi) kbbr7 to kbbr0 ? * figure 17.12 receive counter and kbbr data load timing rev. 2.0, 08/02, page 480 of 788 17.4.8 kclk fall interrupt operation in this device, clearing the kbfsel bit to 0 in kbcrh enables the kbf bit in kbcrl to be used as a flag for the interrupt generated by the fall of kclk input. figure 17.13 shows the setting method and an example of operation. start set kbioe kbf = 1 (interrupt generated) kbe = 0 (kbbr reception disabled) interrupt handling clear kbf kclk pin fall detected? kbfsel = 0 kbie = 1 (kclk falling edge interrupts enabled) ye s no kclk (pin state) kbf bit interrupt generated interrupt generated cleared by software note: * the kbf setting timing is the same as the timing of kbf setting and kclk automatic i/o inhibit bit generation in figure 17.11. when the kbf bit is used as the kclk input fall interrupt flag, the automatic i/o inhibit function does not operate. figure 17.13 example of kclk input fall interrupt operation rev. 2.0, 08/02, page 481 of 788 17.5 usage notes 17.5.1 kbioe setting and kclk falling edge detection when kbioe is 0, the internal kclk and internal kd settings are fixed at 1. therefore, if the kclk pin is low when the kbioe bit is set to 1, the edge detection circuit operates and the kclk falling edge is detected. if the kbfsel bit and kbe bit are both 0 at this time, the kbf bit is set. figure 17.14 shows the timing of kbioe setting and kclk falling edge detection. t1 t2 ? kclk (pin) internal kclk (kclki) falling edge signal kbioe kbfsel kbe kbf figure 17.14 kbioe setting and kclk falling edge detection timing 17.5.2 module stop mode setting keyboard buffer controller operation can be enabled or disabled using the module stop control register. the initial setting is for keyboard buffer controller operation to be halted. register access is enabled by canceling module stop mode. for details, refer to section 26, power-down modes. rev. 2.0, 08/02, page 482 of 788 rev. 2.0, 08/02, page 483 of 788 section 18 host interface x-bus interface (xbs) this lsi has an on-chip host interface (hif) that enables connection to the isa bus (x-bus) and has an on-chip lpc interface. in the following text, these two host interfaces (hifs) are referred to as xbs and lpc, respectively. the xbs provides a four-channel parallel interface between the chips internal cpu and a host processor. communication is carried out via seven control signals from the host processor ( &6 4 , &6 5 or (&6 5 , &6 6 , &6 7 , ha0, ,25 , and ,2: ), six output signals to the host processor (ga20, hirq1, hirq11, hirq12, hirq3, and hirq4), and an 8-bit bidirectional command/data bus (hdb7 to hdb0). the &6 4 , &6 5 (or (&6 5 ), &6 6 and &6 7 signals select one of the four interface channels. 18.1 features control of the fast gate a20 function shutdown of the xbs module by the hifsd pin five host interrupt requests ifhstx0a_000020020700 rev. 2.0, 08/02, page 484 of 788 figure 18.1 shows a block diagram of the xbs. internal interrupt signals ibf2 ibf1 control logic hdb7 to hdb0 idr_3 odr_3 str_3 idr_4 odr_4 str_4 hicr2 module data bus host data bus host interrupt request fast a20 gate control port 4, port 8, port b internal data bus bus interface / ha0 hirq1 hirq11 hirq12 hirq3 hirq4 ga20 hifsd idr_1 odr_1 str_1 idr_2 odr_2 str_2 hicr ibf4 ibf3 legend idr_1: idr_2: odr_1: odr_2: str_1: str_2: hicr: input data register_1 input data register_2 output data register_1 output data register_2 status register_1 status register_2 host interface control register idr_3: idr_4: odr_3: odr_4: str_3: str_4: hicr2: input data register_3 input data register_4 output data register_3 output data register_4 status register_3 status register_4 host interface control register 2 figure 18.1 block diagram of xbs rev. 2.0, 08/02, page 485 of 788 18.2 input/output pins table 18.1 lists the input and output pins of the xbs module. table 18.1 pin configuration name abbreviation port i/o function i/o read ,25 p93 input host interface read signal i/o write ,2: p94 input host interface write signal chip select 1 &6 4 p95 input host interface chip select signal for idr_1, odr_1, str_1 &6 5 p81 chip select 2 * (&6 5 p90 input host interface chip select signal for idr_2, odr_2, str_2 chip select 3 &6 6 pb2 input host interface chip select signal for idr_3, odr_3, str_3 chip select 4 &6 7 pb3 input host interface chip select signal for idr_4, odr_4, str_4 command/data ha0 p80 input host interface address select signal in host read access, this signal selects the status registers (str_1 to str_4) or data registers (odr_1 to odr_4). in host write access to the data registers (idr_1 to idr_4), this signal indicates whether the host is writing a command or data. data bus hdb7 to hdb0 p37 to p30 i/o host interface data bus host interrupt 11 hirq11 p43 output interrupt output 11 to host host interrupt 1 hirq1 p44 output interrupt output 1 to host host interrupt 12 hirq12 p45 output interrupt output 12 to host host interrupt 3 hirq3 pb0 output interrupt output 3 to host host interrupt 4 hirq4 pb1 output interrupt output 4 to host gate a20 ga20 p81 output a20 gate control signal output hif shutdown hifsd p82 input host interface shutdown control signal note: * selection of &6 5 or (&6 5 is by means of the cs2e bit in stcr and the fga20e bit in hicr. xbs channel 2 and the &6 5 pin can be used when cs2e = 1. when cs2e = 1, &6 5 is used when fga20e =0, and (&6 5 is used when fga20e = 1. in this manual, both are referred to as &6 5 . rev. 2.0, 08/02, page 486 of 788 18.3 register descriptions xbs has the following registers. xbs registers hicr, idr_1, idr_2, odr_1, odr_2, str_1, and str_2 can only be accessed when the hie bit is set to 1 in syscr. for details on syscr, refer to section 3.2.2, system control register (syscr). system control register 2 (syscr2) host interface control register (hicr) host interface control register 2 (hicr2) input data register (idr) output data register (odr) status register (str) 18.3.1 system control register 2 (syscr2) syscr2 controls the operations of port 6 and host interface. bit bit name initial value r/w description 7 6 kwul1 kwul0 0 0 r/w r/w key wakeup level 1 and 0 sets the port 6 input level. the input level of port-6 multiplexing pins is also changed by these settings. 00: port 6 is in the standard input level 01: port 6 is in input level 1 10: port 6 is in input level 2 11: port 6 is in input level 3 5 p6pue 0 r/w port 6 input pull-up mos extra (p6pue) controls and selects the current specification for the port 6 input pull-up mos. 0: standard current specification 1: current limited specification 4 ? 0 ? reserved only 0 should be written to this bit. 3 sde 0 r/w shutdown enable 0: host interface pin shutdown function disabled 1: host interface pin shutdown function enabled when the shutdown function is enabled, host interface pin functions can be halted, and the pins placed in the high-impedance state, according to the state of the hifsd pin. rev. 2.0, 08/02, page 487 of 788 bit bit name initial value r/w description 2 cs4e 0 r/w cs4 enable 0: channel 4 functions disabled 1: channel 4 functions enabled (channel 4 pin is enabled) enabling setting is valid when the hi12e bit is 1. 1 cs3e 0 r/w cs3 enable 0: channel 3 functions disabled 1: channel 3 functions enabled (channel 3 pin is enabled) enabling setting is valid when the hi12e bit is 1. 0 hi12e 0 r/w host interface enable bit 0: host interface functions are disabled 1: host interface functions are enabled (settings of bits cs2e to cs4e, fga20e, and sde are enabled) enabling setting is valid in single-chip mode. rev. 2.0, 08/02, page 488 of 788 18.3.2 host interface control register (hicr) host interface control register 2 (hicr2) hicr controls host interface channel 1 and 2 interrupts and the fast a20 gate function. hicr2 controls host interface channel 3 and 4 interrupts. hicr r/w bit bit name initial value slave host description 7 to 3 ? all 1 ?? reserved these bits are always read as 1 and cannot be modified. 2 ibfie2 0 r/w ? input data register full interrupt enable 2 enables or disables the ibf2 interrupt to the internal cpu. 0: input data register (idr_2) reception completed interrupt request disabled 1: input data register (idr_2) reception completed interrupt request enabled 1 ibfie1 0 r/w ? input data register full interrupt enable 1 enables or disables the ibf1 interrupt to the internal cpu. 0: input data register (idr_1) reception completed interrupt request disabled 1: input data register (idr_1) reception completed interrupt request enabled rev. 2.0, 08/02, page 489 of 788 r/w bit bit name initial value slave host description 0 fga20e 0 r/w ? fast a20 gate function enable when p81ddr=0: 0: xbs fast a20 gate function disabled 1: setting prohibited when p81ddr=1: 0: xbs fast a20 gate function disabled 1: xbs fast a20 gate function enabled when the fast a20 gate is disabled, the normal a20 gate can be implemented by the firmware operation of the p81 output. when the host interface (xbs) fast a20 gate function is enabled, the ddr bit for p81 must be set to 1. therefore, the state of the p81/ga20 pin cannot be monitored by reading the dr bit for p81. a fast a20 gate function is also provided in the lpc. the state of the p81/ga20 pin can be monitored by reading the lpcs ga20 bit. rev. 2.0, 08/02, page 490 of 788 hicr2 r/w bit bit name initial value slave host description 7 to 3 ? all 1 ?? reserved these bits are always read as 1, and cannot be modified. 2 ibfie4 0 r/w ? input data register full interrupt enable 4 enables or disables the ibf4 interrupt to the internal cpu. 0: input data register (idr_4) reception completed interrupt request disabled 1: input data register (idr_4) reception completed interrupt request enabled 1 ibfie3 0 r/w ? input data register full interrupt enable 3 enables or disables the ibf3 interrupt to the internal cpu. 0: input data register (idr_3) reception completed interrupt request disabled 1: input data register (idr_3) reception completed interrupt request enabled 0 ? 0 ?? reserved the initial value should not be changed. rev. 2.0, 08/02, page 491 of 788 18.3.3 input data register (idr) idr is a register in which data to be input from the host processor to the slave processor (this lsi) is stored. r/w bit bit name initial value slave host description 7 6 5 4 3 2 1 0 idr7 idr6 idr5 idr4 idr3 idr2 idr1 idr0 ? ? ? ? ? ? ? ? r r r r r r r r w w w w w w w w when &6q (n = 1 to 4) is low, information on the host data bus is written into idr_n at the rising edge of ,2: . the ha0 state is also latched into the c/ ' bit in str_n to indicate whether the written information is a command or data. 18.3.4 output data register 1 (odr) odr is a register in which data to be output from the slave processor (this lsi) to the host processor is stored. r/w bit bit name initial value slave host description 7 6 5 4 3 2 1 0 odr7 odr6 odr5 odr4 odr3 odr2 odr1 odr0 ? ? ? ? ? ? ? ? r/w r/w r/w r/w r/w r/w r/w r/w r r r r r r r r the odr_n contents are output on the host data bus when ha0 is low, &6q (n = 1 to 4) is low, and ,25 is low. rev. 2.0, 08/02, page 492 of 788 18.3.5 status register (str) str indicates status information during host interface processing. r/w bit bit name initial value slave host description 7 to 4 dbu all 0 r/w r defined by user the user can use these bits as necessary. 3c/ ' 0 r r command/data receives the ha0 input when the host processor writes to idr, and indicates whether idr contains data or a command. 0: contents of input data register (idr) are data 1: contents of input data register (idr) are a command 2 dbu 0 r/w r defined by user the user can use these bits as necessary. 1 ibf 0 r r input buffer full this bit is an internal interrupt source to the slave processor (this lsi). the ibf flag setting and clearing conditions are different when the fast a20 gate is used. for details see table 18.5. [clearing condition] 0: when the slave processor reads idr [setting condition] 1: when the host processor writes to idr 0obf 0 r/(w) * r output buffer full [clearing condition] 0: when the host processor reads odr or the slave writes 0 in the obf bit [setting condition] 1: when the slave processor writes to odr note: * only 0 can be written, to clear the flag. rev. 2.0, 08/02, page 493 of 788 table 18.2 shows the conditions for setting and clearing the str flags. table 18.2 set/clear timing for str flags flag setting condition clearing condition c/ ' rising edge of hosts write signal ( ,2: ) when ha0 is high rising edge of hosts write signal ( ,2: ) when ha0 is low ibf * rising edge of hosts write signal ( ,2: ) when writing to idr1 falling edge of slaves internal read signal when reading idr1 obf falling edge of slaves internal write signal when writing to odr1 rising edge of hosts read signal ( ,25 ) when reading odr1 note: * the ibf flag setting and clearing conditions are different when the fast a20 gate is used. for details see table 18.5. 18.4 operation 18.4.1 host interface activation the host interface is activated by setting the hi12e bit in syscr2 to 1 in single-chip mode. when the host interface is activated, all related i/o ports (data port 3, control ports 8 and 9, and host interrupt request port 4) become dedicated host interface ports. setting the cs3e bit and cs4e bit to 1 enables the number of host interface channels to be extended to four, and makes the channel 3 and 4 related i/o port (part of port b for control and host interrupt requests) a dedicated host interface port. rev. 2.0, 08/02, page 494 of 788 table 18.3 shows hif host interface channel selection and pin operation. table 18.3 host interface channel selection and pin operation hi12e cs2e cs3e cs4e operation 0 host interface functions halted 0 host interface channel 1 only operating operation of channels 2 to 4 halted pins p43, p81, p90, and pb0 to pb3 operate as i/o ports. &6 5 or (&6 5 , &6 6 , and &6 7 inputs do not operate. 0 1 host interface channel 1 and 4 functions operating operation of channels 2 and 3 halted pins p43, p81, p90, pb0, and pb2 operate as i/o ports. &6 5 or (&6 5 and &6 6 inputs do not operate. 0 host interface channel 1 and 3 functions operating operation of channels 2 and 4 halted pins p43, p81, p90, pb1, and pb3 operate as i/o ports. &6 5 or (&6 5 and &6 7 inputs do not operate. 0 1 1 host interface channel 1, 3, and 4 functions operating operation of channel 2 halted pins p43, p81, and p90 operate as i/o ports. &6 5 or (&6 5 input does not operate. 0 host interface channel 1 and 2 functions operating operation of channels 3 and 4 halted pins pb0 to pb3 operate as i/o ports. &6 6 and &6 7 inputs do not operate. 0 1 host interface channel 1, 2, and 4 functions operating operation of channel 3 halted pins pb0 and pb2 operate as i/o ports. &6 6 input does not operate. 0 host interface channel 1 to 3 functions operating operation of channel 4 halted pins pb1 and pb3 operate as i/o ports. &6 7 input does not operate. 1 1 1 1 host interface channel 1 to 4 functions operating rev. 2.0, 08/02, page 495 of 788 18.4.2 control states table 18.4 shows host interface operations from the hif host, and slave (this lsi) operation. table 18.4 host interface operations from hif host, and slave operation other than &6q &6q &6q &6q &6q &6q &6q &6q ,25 ,25 ,25 ,25 ,2: ,2: ,2: ,2: ha0 operation 0 setting prohibited 0 1 setting prohibited 0 data read from output data register n (odr_n) 0 1 1 status read from status register n (str_n) 0 data written to input data register n (idr_n) 0 1 command written to input data register n (idr_n) 0 idle state 10 1 1 1 idle state (n = 1 to 4) 18.4.3 a20 gate the a20 gate signal can mask address a20 to emulate an addressing mode used by personal computers with an 8086*-family cpu. a regular-speed a20 gate signal can be output under firmware control. fast a20 gate output is enabled by setting the fga20e bit (bit 0) to 1 in hicr (h'fff0). note: *: intel microprocessor. regular a20 gate operation: output of the a20 gate signal can be controlled by an h'd1 command followed by data. when the slave processor (this lsi) receives data, it normally uses an interrupt routine activated by the ibf1 interrupt to read idr1. if the data follows an h'd1 command, software copies bit 1 of the data and outputs it at the gate a20 pin. fast a20 gate operation: when the fga20e bit is set to 1, p81/ga20 is used for output of a fast a20 gate signal. bit p81ddr must be set to 1 to assign this pin for output. when the ddr bit for p81 is set to 1, the state of the p81/ga20 pin cannot be monitored by reading the dr bit for p81. the state of the p81/ga20 pin can be monitored by reading the ga20 bit in the lpcs hicr2 register. the initial output from this pin will be a logic 1, which is the initial value. afterward, the host processor can manipulate the output from this pin by sending commands and data. this function is available only when register idr1 is accessed using &6 4 . the slave processor (this lsi) decodes the commands input from the host processor. when an h'd1 host command is detected, bit 1 of the data following the host command is output from the ga20 output pin. this operation does not depend on firmware or interrupts, and is faster than the regular rev. 2.0, 08/02, page 496 of 788 processing using interrupts. table 18.5 lists the conditions that set and clear ga20 (p81). figure 18.2 shows the ga20 output in flowchart form. table 18.6 indicates the ga20 output signal values. table 18.5 ga20 (p81) set/clear timing pin name setting condition clearing condition ga20 (p81) rising edge of the hosts write signal ( ,2: ) when bit 1 of the written data is 1 and the data follows an h'd1 host command rising edge of the hosts write signal ( ,2: ) when bit 1 of the written data is 0 and the data follows an h'd1 host command also, when bit fga20e in hicr is cleared to 0 start host write h'd1 command received? wait for next byte host write yes data byte? write bit 1 of data byte to dr bit of p81/ga20 yes no no figure 18.2 ga20 output rev. 2.0, 08/02, page 497 of 788 table 18.6 fast a20 gate output signal ha0 data/command internal cpu interrupt flag (ibf) ga20 (p81) remarks 1 0 1 h'd1 command 1 data * 1 h'ff command 0 0 0 q 1 q (1) turn-on sequence 1 0 1 h'd1 command 0 data * 2 h'ff command 0 0 0 q 0 q (0) turn-off sequence 1 0 1/0 h'd1 command 1 data * 1 command other than h'ff and h'd1 0 0 1 q 1 q (1) turn-on sequence (abbreviated form) 1 0 1/0 h'd1 command 0 data * 2 command other than h'ff and h'd1 0 0 1 q 0 q (0) turn-off sequence (abbreviated form) 1 1 h'd1 command command other than h'd1 0 1 q q cancelled sequence 1 1 h'd1 command h'd1 command 0 0 q q retriggered sequence 1 0 1 h'd1 command any data h'd1 command 0 0 0 q 1/0 q (1/0) consecutively executed sequences notes: 1. arbitrary data with bit 1 set to 1. 2. arbitrary data with bit 1 cleared to 0. 18.4.4 host interface pin shutdown function host interface output can be placed in the high-impedance state according to the state of the hifsd pin. setting the sde bit to 1 in the syscr2 register when the hi12e bit is set to 1 enables the hifsd pin. the hif constantly monitors the hifsd pin, and when this pin goes low, places the host interface output pins (hirq1, hirq11, hirq12, hirq3, hirq4, and ga20) in the high-impedance state. at the same time, the host interface input pins ( &6 4 , &6 5 or (&6 5 , &6 6 , &6 7 , ,2: , ,25 , and ha0) are disabled (fixed at the high input state internally) regardless of the pin states, and the signals of the multiplexed functions of these pins (input block) are similarly fixed internally. as a result, the host interface i/o pins (hdb7 to hdb0) also go to the high- impedance state. this state is maintained while the hifsd pin is low, and when the hifsd pin returns to the high- level state, the pins are restored to their normal operation as host interface pins. rev. 2.0, 08/02, page 498 of 788 table 18.7 shows the scope of hif pin shutdown. table 18.7 scope of hif pin shutdown abbreviation port scope of shutdown in slave mode i/o selection conditions ,25 p93 o input hi12e = 1 ,2: p94 o input hi12e = 1 &6 4 p95 o input hi12e = 1 &6 5 p81 d input hi12e = 1 and cs2e = 1 and fga20e = 0 (&6 5 p90 d input hi12e = 1 and cs2e = 1 and fga20e = 1 &6 6 pb2 d input hi12e = 1 and cs3e = 1 &6 7 pb3 d input hi12e = 1 and cs4e = 1 ha0 p80 o input hi12e = 1 hdb7 to hdb0 p37 to p30 o i/o hi12e = 1 hirq11 p43 d output hi12e = 1 and cs2e = 1 and p43ddr = 1 hirq1 p44 d output hi12e = 1 and p44ddr = 1 hirq12 p45 d output hi12e = 1 and p45ddr = 1 hirq3 pb0 d output hi12e = 1 and cs3e = 1 and pb0ddr = 1 hirq4 pb1 d output hi12e = 1 and cs4e = 1 and pb1ddr = 1 ga20 p81 d output hi12e = 1 and fga20e = 1 hifsd p82 input hi12e = 1 and sde = 1 legend: o: pins shut down by shutdown function the ,54 5 / $'75* input signal is also fixed in the case of p90 shutdown, the tmci1/hsynci signal in the case of p43 shutdown, and the tmri/csynci in the case of p45 shutdown. d : pins shut down only when the xbs function is selected by means of a register setting : pin not shut down rev. 2.0, 08/02, page 499 of 788 18.5 interrupt sources 18.5.1 ibf1, ibf2, ibf3, and ibf4 the host interface can issue four interrupt requests to the slave processor: ibf1, ibf2, ibf3 and ibf4. they are input buffer full interrupts for input data registers idr_1, idr_2, idr_3 and idr_4 respectively. each interrupt is enabled when the corresponding enable bit is set. table 18.8 input buffer full interrupts interrupt description ibf1 requested when ibfie1 is set to 1 and idr_1 is full ibf2 requested when ibfie2 is set to 1 and idr_2 is full ibf3 requested when ibfie3 is set to 1 and idr_3 is full ibf4 requested when ibfie4 is set to 1 and idr_4 is full 18.5.2 hirq11, hirq1, hirq12, hirq3, and hirq4 bits p45dr to p43dr in the port 4 data register (p4dr) and bits pb1odr and pb0odr in the port b data register (pbodr) can be used as host interrupt request latches. when they are used as host interrupt request output, set each bit in the data direction register (ddr) of the pin to 1. the corresponding bits in p4dr are cleared to 0 by the host processors read signal ( ,25 ). if &6 4 and ha0 are low, when ,25 goes low and the host reads odr_1, hirq1 and hirq12 are cleared to 0. if &6 5 and ha0 are low, when ,25 goes low and the host reads odr_2, hirq11 is cleared to 0. the corresponding bit in pbodr is cleared to 0 by the hosts read signal ( ,25 ). if &6 6 and ha0 are low, when ,25 goes low and the host reads odr_3, hirq3 is cleared to 0. if &6 7 and ha0 are low, when ,25 goes low and the host reads odr_4, hirq4 is cleared to 0. to generate a host interrupt request, normally on-chip firmware writes 1 in the corresponding bit. in processing the interrupt, the hosts interrupt handling routine reads the output data register (odr_1, odr_2, odr_3, or odr_4) and this clears the host interrupt latch to 0. table 18.9 indicates how these bits are set and cleared. figure 18.3 shows the processing in flowchart form. rev. 2.0, 08/02, page 500 of 788 table 18.9 hirq setting/clearing conditions host interrupt signal setting condition clearing condition hirq11 (p43) internal cpu reads 0 from bit p43dr, then writes 1 internal cpu writes 0 in bit p43dr, or host reads output data register_2 (odr_2) hirq1 (p44) internal cpu reads 0 from bit p44dr, then writes 1 internal cpu writes 0 in bit p44dr, or host reads output data register_1 (odr_1) hirq12 (p45) internal cpu reads 0 from bit p45dr, then writes 1 internal cpu writes 0 in bit p45dr, or host reads output data register_1 (odr_1) hirq3 (pb0) internal cpu reads 0 from bit pb0odr, then writes 1 internal cpu writes 0 in bit pb0odr, or host reads output data register_3 (odr_3) hirq4 (pb1) internal cpu reads 0 from bit pb1odr, then writes 1 internal cpu writes 0 in bit pb1odr, or host reads output data register_4 (odr_4) slave cpu master cpu write to odr write 1 to p4dr p4dr = 0? yes no no yes all bytes transferred? hirq output high hirq output low interrupt initiation odr read hardware operations software operations figure 18.3 hirq output flowchart (example of channels 1 and 2) hirq setting/clearing conflict: if there is conflict between a p4dr or pbodr read/write by the cpu and p4dr (hirq11, hirq1, hirq12) or pbodr (hirq3, hirq4) clearing by the rev. 2.0, 08/02, page 501 of 788 host, clearing by the host is held pending during the p4dr or pbodr read/write by the cpu. p4dr or pbodr clearing is executed after completion of the read/write. 18.6 usage notes 18.6.1 note on host interface the host interface provides buffering of asynchronous data from the host processor and slave processor (this lsi), but an interface protocol must be followed to implement necessary functions and avoid data contention. for example, if the host and slave processors try to access the same input or output data register simultaneously, the data will be corrupted. interrupts can be used to design a simple and effective protocol. also, if two or more of pins &6 4 to &6 7 are driven low simultaneously in attempting idr or odr access, signal contention will occur within the chip, and a through-current may result. this usage must therefore be avoided. 18.6.2 module stop mode setting xbs operation can be enabled or disabled using the module stop control register. the initial setting is for xbs operation to be halted. register access is enabled by canceling module stop mode. for details, refer to section 26, power-down modes. rev. 2.0, 08/02, page 502 of 788 rev. 2.0, 08/02, page 503 of 788 section 19 host interface lpc interface (lpc) this lsi has an on-chip lpc interface. the lpc performs serial transfer of cycle type, address, and data, synchronized with the 33 mhz pci clock. it uses four signal lines for address/data, and one for host interrupt requests. this lpc module supports only i/o read cycle and i/o write cycle transfers. it is also provided with power-down functions that can control the pci clock and shut down the host interface. 19.1 features supports lpc interface i/o read cycles and i/o write cycles ? uses four signal lines (lad3 to lad0) to transfer the cycle type, address, and data. ? uses three control signals: clock (lclk), reset ( /5(6(7 ), and frame ( /)5$0( ). has three register sets comprising data and status registers ? the basic register set comprises three bytes: an input register (idr), output register (odr), and status register (str). ? channels 1 and 2 have fixed i/o addresses of h'60/h'64 and h'62/h'66, respectively. a fast a20 gate function is also provided. ? the i/o address can be set for channel 3. sixteen bidirectional data register bytes can be manipulated in addition to the basic register set. supports serirq ? host interrupt requests are transferred serially on a single signal line (serirq). ? on channel 1, hirq1 and hirq12 can be generated. ? on channels 2 and 3, smi, hirq6, and hirq9 to hirq11 can be generated. ? operation can be switched between quiet mode and continuous mode. ? the &/.581 signal can be manipulated to restart the pci clock (lclk). eleven interrupt sources ? the lpc module can be shut down by inputting the /3&3' signal. ? three pins, 30( , /60, , and lsci, are provided for general input/output. ifhstl0a_000020020700 rev. 2.0, 08/02, page 504 of 788 figure 19.1 shows a block diagram of the lpc. twr1C15 idr3 idr2 idr1 h'0060/64 h'0062/66 ladr3 sirqcr0 sirqcr1 twr0mw twr1C15 odr3 odr2 odr1 str3 str2 str1 hicr0 hicr1 hicr2 hicr3 twr0sw lscie lscib lsci input pb1 i/o lsmie lsmib lsmi input pb0 i/o pmee pmeb pme input p80 i/o lad0C lad3 serirq lsci ga20 lclk ibfi1 ibfi2 ibfi3 erri module data bus cycle detection serial ? parallel conversion serial ? parallel conversion address match sync output parallel ? serial conversion control logic internal interrupt control hisel legend hicr0 to hicr3: host interface control registers 0 to 3 ladr3h, 3l: lpc channel 3 address register 3h and 3l idr1 to idr3: input data registers 1 to 3 odr1 to dor3: output data registers 1 to 3 str1 to str3: status registers 1 to 3 hisel: host interface select register twr0mw: two-way register 0mw twr0sw: two-way register 0sw twr1 to twr15: two-way data registers 1 to 15 serirq0, 1: serieq control registers 0 and 1 figure 19.1 block diagram of lpc rev. 2.0, 08/02, page 505 of 788 19.2 input/output pins table 19.1 lists the input and output pins of the lpc module. table 19.1 pin configuration name abbreviation port i/o function lpc address/ data 3 to 0 lad3 to lad0 p33 to p30 input/ output serial (4-signal-line) transfer cycle type/address/data signals, synchronized with lclk lpc frame /)5$0( p34 input * 1 transfer cycle start and forced termination signal lpc reset /5(6(7 p35 input * 1 lpc interface reset signal lpc clock lclk p36 input 33 mhz pci clock signal serialized interrupt request serirq p37 input/ output * 1 serialized host interrupt request signal, synchronized with lclk (smi, irq1, irq6, irq9 to irq12) lsci general output lsci pb1 output * 1, * 2 general output lsmi general output /60, pb0 output * 1, * 2 general output pme general output 30( p80 output * 1, * 2 general output gate a20 ga20 p81 output * 1, * 2 a20 gate control signal output lpc clock run &/.581 p82 input/ output * 1, * 2 lclk restart request signal in case of serial host interrupt request lpc power-down /3&3' p83 input * 1 lpc module shutdown signal notes: 1. pin state monitoring input is possible in addition to the lpc interface control input/output function. 2. only 0 can be output. if 1 is output, the pin goes to the high-impedance state, so an external resistor is necessary to pull the signal up to v cc . rev. 2.0, 08/02, page 506 of 788 19.3 register descriptions the lpc has the following registers. the settings of xbs related bits do not affect the operation of this lsis lpc. however, for reasons relating to the configuration of the program development tool (emulator), when the lpc is used, bit hi12e in syscr2 should not be set to 1. for details, see section 3.2.2, system control register (syscr), and section 18.3.1, system control register 2 (syscr2). host interface control register 0 (hicr0) host interface control register 1 (hicr1) host interface control register 2 (hicr2) host interface control register 3 (hicr3) lpc channel 3 address registers (ladr3h, ladr3l) input data register 1 (idr1) output data register 1 (odr1) status register 1 (str1) input data register 2 (idr2) output data register 2 (odr2) status register 2 (str2) input data register 3 (idr3) output data register 3 (odr3) status register 3 (str3) bidirectional data registers 0 to 15 (twr0 to twr15) serirq control register 0 (sirqcr0) serirq control register 1 (sirqcr1) host interface select register (hisel) rev. 2.0, 08/02, page 507 of 788 19.3.1 host interface control registers 0 and 1 (hicr0, hicr1) hicr0 and hicr1 contain control bits that enable or disable host interface functions, control bits that determine pin output and the internal state of the host interface, and status flags that monitor the internal state of the host interface. hicr0 r/w bit bit name initial value slave host description 7 6 5 lpc3e lpc2e lpc1e 0 0 0 r/w r/w r/w lpc enable 3 to 1 enable or disable the host interface function in single-chip mode. when the host interface is enabled (one of the three bits is set to 1), processing for data transfer between the slave processor (this lsi) and the host processor is performed using pins lad3 to lad0, /)5$0( , /5(6(7 , lclk, serirq, &/.581 , and /3&3' . lpc3e 0: lpc channel 3 operation is disabled no address (ladr3) matches for idr3, odr3, str3, or twr0 to twr15 1: lpc channel 3 operation is enabled lpc2e 0: lpc channel 2 operation is disabled no address (h'0062, 66) matches for idr2, odr2, or str2 1: lpc channel 2 operation is enabled lpc1e 0: lpc channel 1 operation is disabled no address (h'0060, 64) matches for idr1, odr1, or str1 1: lpc channel 1 operation is enabled rev. 2.0, 08/02, page 508 of 788 r/w bit bit name initial value slave host description 4 fga20e 0 r/w fast a20 gate function enable enables or disables the fast a20 gate function. when the fast a20 gate is disabled, the normal a20 gate can be implemented by firmware operation of the p81 output. when the fast a20 gate function is enabled, the ddr bit for p81 must not be set to 1. 0: fast a20 gate function disabled other function of pin p81 is enabled ga20 output internal state is initialized to 1 1: fast a20 gate function enabled ga20 pin output is open-drain (external vcc pull- up resistor required) 3 sdwne 0 r/w lpc software shutdown enable controls host interface shutdown. for details of the lpc shutdown function, and the scope of initialization by an lpc reset and an lpc shutdown, see section 19.4.4, host interface shutdown function (lpcpd). 0: normal state, lpc software shutdown setting enabled [clearing conditions] writing 0 lpc hardware reset or lpc software reset lpc hardware shutdown release (rising edge of /3&3' signal) 1: lpc hardware shutdown state setting enabled hardware shutdown state when /3&3' signal is low [setting condition] writing 1 after reading sdwne = 0 rev. 2.0, 08/02, page 509 of 788 r/w bit bit name initial value slave host description 2 pmee 0 r/w pme output enable controls pme output in combination with the pmeb bit in hicr1. 30( pin output is open-drain, and an external pull-up resistor is needed to pull the output up to v cc when the pme output function is used, the ddr bit for p80 must not be set to 1. pmee pmeb 0 x: pme output disabled, other function of pin is enabled 1 0: pme output enabled, 30( pin output goes to 0 level 1 1: pme output enabled, 30( pin output is high-impedance 1 lsmie 0 r/w lsmi output enable controls lsmi output in combination with the lsmib bit in hicr1. /60, pin output is open-drain, and an external pull-up resistor is needed to pull the output up to v cc when the lsmi output function is used, the ddr bit for pb0 must not be set to 1. lsmie lsmib 0 x: lsmi output disabled, other function of pin is enabled 1 0: lsmi output enabled, /60, pin output goes to 0 level 1 1: lsmi output enabled, /60, pin output is high-impedance rev. 2.0, 08/02, page 510 of 788 r/w bit bit name initial value slave host description 0 lscie 0 r/w lsci output enable controls lsci output in combination with the lscib bit in hicr1. lsci pin output is open-drain, and an external pull-up resistor is needed to pull the output up to v cc when the lsci output function is used, the ddr bit for pb1 must not be set to 1. lscie lscib 0 x: lsci output disabled, other function of pin is enabled 1 0: lsci output enabled, lsci pin output goes to 0 level 1 1: lsci output enabled, lsci pin output is high-impedance legend x: don't care rev. 2.0, 08/02, page 511 of 788 hicr1 r/w bit bit name initial value slave host description 7 lpcbsy 0 r/w lpc busy indicates that the host interface is processing a transfer cycle. 0: host interface is in transfer cycle wait state bus idle, or transfer cycle not subject to processing is in progress cycle type or address indeterminate during transfer cycle [clearing conditions] lpc hardware reset or lpc software reset lpc hardware shutdown or lpc software shutdown forced termination (abort) of transfer cycle subject to processing normal termination of transfer cycle subject to processing 1: host interface is performing transfer cycle processing [setting condition] match of cycle type and address rev. 2.0, 08/02, page 512 of 788 r/w bit bit name initial value slave host description 6 clkreq 0 r lclk request indicates that the host interfaces serirq output is requesting a restart of lclk. 0: no lclk restart request [clearing conditions] lpc hardware reset or lpc software reset lpc hardware shutdown or lpc software shutdown serirq is set to continuous mode there are no further interrupts for transfer to the host in quiet mode 1: lclk restart request issued [setting condition] in quiet mode, serirq interrupt output becomes necessary while lclk is stopped 5 irqbsy 0 r serirq busy indicates that the host interfaces serirq signal is engaged in transfer processing. 0: serirq transfer frame wait state [clearing conditions] lpc hardware reset or lpc software reset lpc hardware shutdown or lpc software shutdown end of serirq transfer frame 1: serirq transfer processing in progress [setting condition] start of serirq transfer frame rev. 2.0, 08/02, page 513 of 788 r/w bit bit name initial value slave host description 4 lrstb 0 lpc software reset bit resets the host interface. for the scope of initialization by an lpc reset, see section 19.4.4, host interface shutdown function (lpcpd). 0: normal state [clearing conditions] writing 0 lpc hardware reset 1: lpc software reset state [setting condition] writing 1 after reading lrstb = 0 3 sdwnb 0 r/w lpc software shutdown bit controls host interface shutdown. for details of the lpc shutdown function, and the scope of initialization by an lpc reset and an lpc shutdown, see section 19.4.4, host interface shutdown function (lpcpd). 0: normal state [clearing conditions] writing 0 lpc hardware reset or lpc software reset lpc hardware shutdown lpc hardware shutdown release (rising edge of /3&3' signal when sdwne = 0) 1: lpc software shutdown state [setting condition] writing 1 after reading sdwnb = 0 2 pmeb 0 r/w pme output bit controls pme output in combination with the pmee bit. for details, refer to description on the pmee bit in hicr0. 1 lsmib 0 r/w lsmi output bit controls lsmi output in combination with the lsmie bit. for details, refer to description on the lsmie bit in hicr0. rev. 2.0, 08/02, page 514 of 788 r/w bit bit name initial value slave host description 0 lscib 0 r/w lsci output bit controls lsci output in combination with the lscie bit. for details, refer to description on the lscie bit in hicr0. 19.3.2 host interface control registers 2 and 3 (hicr2, hicr3) bits 6 to 0 in hicr2 control interrupts from the host interface (lpc) module to the slave processor (this lsi). bit 7 in hicr2 and hicr3 monitor host interface pin states. the pin states can be monitored regardless of the host interface operating state or the operating state of the functions that use pin multiplexing. hicr2 r/w bit bit name initial value slave host description 7 ga20 undefined r ga20 pin monitor 6 lrst 0 r/(w) * lpc reset interrupt flag this bit is a flag that generates an erri interrupt when an lpc hardware reset occurs. 0: [clearing conditions] writing 0 after reading lrst = 1 1: [setting condition] lreset pin falling edge detection 5 sdwn 0 r/(w) * lpc shutdown interrupt flag this bit is a flag that generates an erri interrupt when an lpc hardware shutdown request is generated. 0: [clearing conditions] writing 0 after reading sdwn = 1 lpc hardware reset and lpc software reset 1: [setting condition] lpcpd pin falling edge detection rev. 2.0, 08/02, page 515 of 788 r/w bit bit name initial value slave host description 4 abrt 0 r/(w) * lpc abort interrupt flag this bit is a flag that generates an erri interrupt when a forced termination (abort) of an lpc transfer cycle occurs. 0: [clearing conditions] writing 0 after reading abrt = 1 lpc hardware reset and lpc software reset lpc hardware shutdown and lpc software shutdown 1: [setting condition] /)5$0( pin falling edge detection during lpc transfer cycle 3 ibfie3 0 r/w idr3 and twr receive completion interrupt enable enables or disables ibfi3 interrupt to the slave processor (this lsi). 0: input data register idr3 and twr receive completed interrupt requests disabled 1: [when twrie = 0 in ladr3] input data register (idr3) receive completed interrupt requests enabled [when twrie = 1 in ladr3] input data register (idr3) and twr receive completed interrupt requests enabled 2 ibfie2 0 r/w idr2 receive completion interrupt enable enables or disables ibfi2 interrupt to the slave processor (this lsi). 0: input data register (idr2) receive completed interrupt requests disabled 1: input data register (idr2) receive completed interrupt requests enabled 1 ibfie1 0 r/w idr1 receive completion interrupt enable enables or disables ibfi1 interrupt to the slave processor (this lsi). 0: input data register (idr1) receive completed interrupt requests disabled 1: input data register (idr1) receive completed interrupt requests enabled rev. 2.0, 08/02, page 516 of 788 r/w bit bit name initial value slave host description 0 errie 0 r/w error interrupt enable enables or disables erri interrupt to the slave processor (this lsi). 0: error interrupt requests disabled 1: error interrupt requests enabled note: * only 0 can be written to bits 6 to 4, to clear the flag. hicr3 r/w bit bit name initial value slave host description 7 lframe undefined r /)5$0( pin monitor 6 clkrun undefined r &/.581 pin monitor 5 serirq undefined r serirq pin monitor 4 lreset undefined r /5(6(7 pin monitor 3 lpcpd undefined r /3&3' pin monitor 2 pme undefined r 30( pin monitor 1 lsmi undefined r /60, pin monitor 0 lsci undefined r lsci pin monitor rev. 2.0, 08/02, page 517 of 788 19.3.3 lpc channel 3 address register (ladr3) ladr3 comprises two 8-bit readable/writable registers that perform lpc channel-3 host address setting and control the operation of the bidirectional data registers. the contents of the address field in ladr3 must not be changed while channel 3 is operating (while lpc3e is set to 1). ladr3h bit bit name initial value r/w description 7 6 5 4 3 2 1 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w channel 3 address bits 15 to 8: when lpc3e = 1, an i/o address received in an lpc i/o cycle is compared with the contents of ladr3. when determining an idr3, odr3, or str3 address match, bit 0 of ladr3 is regarded as 0, and the value of bit 2 is ignored. when determining a twr0 to twr15 address match, bit 4 of ladr3 is inverted, and the values of bits 3 to 0 are ignored. register selection according to the bits ignored in address match determination is as shown in table 19.2. ladr3l bit bit name initial value r/w description 7 6 5 4 3 bit 7 bit 6 bit 5 bit 4 bit 3 0 0 0 0 0 r/w r/w r/w r/w r/w channel 3 address bits 7 to 3 2 ? 0r/wreserved this bit is readable/writable, however, only 0 should be written to this bit. 1 bit 1 0 r/w channel 3 address bit 1 0 twre 0 r/w bidirectional data register enable enables or disables bidirectional data register operation. 0: twr operation is disabled twr-related i/o address match determination is halted 1: twr operation is enabled rev. 2.0, 08/02, page 518 of 788 table 19.2 register selection i/o address bit 4 bit 3 bit 2 bit 1 bit 0 transfer cycle host register selection bit 4 bit 3 0 bit 1 0 i/o write idr3 write, c/ ' 3 ? 0 bit 4 bit 3 1 bit 1 0 i/o write idr3 write, c/ ' 3 ? 1 bit 4 bit 3 0 bit 1 0 i/o read odr3 read bit 4 bit 3 1 bit 1 0 i/o read str3 read %lw #7 0 0 0 0 i/o write twr0mw write 0001 %lw #7 1111 i/o write twr1 to twr15 write %lw #7 0 0 0 0 i/o read twr0sw read 0 0 0 1 i/o read %lw #7 1111 twr1 to twr15 read 19.3.4 input data registers 1 to 3 (idr1 to idr3) the idr registers are 8-bit read-only registers for the slave processor (this lsi), and 8-bit write- only registers for the host processor. the registers selected from the host according to the i/o address are shown in the following table. for information on idr3 selection, see section 19.3.3, lpc channel 3 address register (ladr3). data transferred in an lpc i/o write cycle is written to the selected register. the state of bit 2 of the i/o address is latched into the c/ ' bit in str, to indicate whether the written information is a command or data. the initial values of idr1 to idr3 are undefined. i/o address bits 15 to 4 bit 3 bit 2 bit 1 bit 0 transfer cycle host register selection 0000 0000 0110 0 0 0 0 i/o write idr1 write, c/ ' 1 ? 0 0000 0000 0110 0 1 0 0 i/o write idr1 write, c/ ' 1 ? 1 0000 0000 0110 0 0 1 0 i/o write idr2 write, c/ ' 2 ? 0 0000 0000 0110 0 1 1 0 i/o write idr2 write, c/ ' 2 ? 1 rev. 2.0, 08/02, page 519 of 788 19.3.5 output data registers 1 to 3 (odr1 to odr3) the odr registers are 8-bit readable/writable registers for the slave processor (this lsi), and 8-bit read-only registers for the host processor. the registers selected from the host according to the i/o address are shown in the following table. for information on odr3 selection, see section 19.3.3, lpc channel 3 address register (ladr3). in an lpc i/o read cycle, the data in the selected register is transferred to the host. the initial values of odr1 to odr3 are undefined. i/o address bits 15 to 4 bit 3 bit 2 bit 1 bit 0 transfer cycle host register selection 0000 0000 0110 0 0 0 0 i/o read odr1 read 0000 0000 0110 0 0 1 0 i/o read odr2 read 19.3.6 bidirectional data registers 0 to 15 (twr0 to twr15) the twr registers are sixteen 8-bit readable/writable registers to both the slave processor (this lsi) and the host processor. in twr0, however, two registers (twr0mw and twr0sw) are allocated to the same address for both the host address and the slave address. twr0mw is a write-only register for the host processor, and a read-only register for the slave processor, while twr0sw is a write-only register for the slave processor and a read-only register for the host processor. when the host and slave processors begin a write, after the respective twr0 registers have been written to, access right arbitration for simultaneous access is performed by checking the status flags to see if those writes were valid. for the registers selected from the host according to the i/o address, see section 19.3.3, lpc channel 3 address register (ladr3). data transferred in an lpc i/o write cycle is written to the selected register; in an lpc i/o read cycle, the data in the selected register is transferred to the host. the initial values of twr0 to twr15 are undefined. rev. 2.0, 08/02, page 520 of 788 19.3.7 status registers 1 to 3 (str1 to str3) the str registers are 8-bit registers that indicate status information during host interface processing. bits 3, 1, and 0 of str1 to str3, and bits 7 to 4 of str3, are read-only bits for both the host processor and the slave processor (this lsi). however, only 0 can be written to bit 0 of str1 to str3 and bits 6 and 4 of str3, from the slave processor (this lsi), in order to clear the flags to 0. the registers selected from the host processor according to the i/o address are shown in the following table. for information on str3 selection, see section 19.3.3, lpc channel 3 address register (ladr3). in an lpc i/o read cycle, the data in the selected register is transferred to the host processor. the initial values of str1 to str3 are h00. i/o address bits 15 to 4 bit 3 bit 2 bit 1 bit 0 transfer cycle host register selection 0000 0000 0110 0 1 0 0 i/o read str1 read 0000 0000 0110 0 1 1 0 i/o read str2 read rev. 2.0, 08/02, page 521 of 788 str1 r/w bit bit name initial value slave host description 7 6 5 4 dbu17 dbu16 dbu15 dbu14 0 0 0 0 r/w r/w r/w r/w r r r r defined by user the user can use these bits as necessary. 3c/ ' 1 0 r r command/data when the host processor writes to an idr register, bit 2 of the i/o address is written into this bit to indicate whether idr contains data or a command. 0: contents of data register (idr) are data 1: contents of data register (idr) are a command 2 dbu12 0 r/w r defined by user the user can use this bit as necessary. 1 ibf1 0 r r input buffer full set to 1 when the host processor writes to idr. this bit is an internal interrupt source to the slave processor (this lsi). ibf is cleared to 0 when the slave processor reads idr. the ibf1 flag setting and clearing conditions are different when the fast a20 gate is used. for details see table 19.3. 0: [clearing condition] when the slave processor reads idr 1: [setting condition] when the host processor writes to idr using i/o write cycle 0 obf1 0 r/(w) * r output buffer full set to 1 when the slave processor (this lsi) writes to odr. cleared to 0 when the host processor reads odr. 0: [clearing condition] when the host processor reads odr using i/o read cycle, or the slave processor writes 0 to the obf bit 1: [setting condition] when the slave processor writes to odr note: * only 0 can be written to clear the flag. rev. 2.0, 08/02, page 522 of 788 str2 r/w bit bit name initial value slave host description 7 6 5 4 dbu27 dbu26 dbu25 dbu24 0 0 0 0 r/w r/w r/w r/w r r r r defined by user the user can use these bits as necessary. 3c/ ' 2 0 r r command/data when the host processor writes to an idr register, bit 2 of the i/o address is written into this bit to indicate whether idr contains data or a command. 0: contents of data register (idr) are data 1: contents of data register (idr) are a command 2 dbu22 0 r/w r defined by user the user can use this bit as necessary. 1 ibf2 0 r r input buffer full set to 1 when the host processor writes to idr. this bit is an internal interrupt source to the slave processor (this lsi). ibf is cleared to 0 when the slave processor reads idr. the ibf1 flag setting and clearing conditions are different when the fast a20 gate is used. for details see table 19.3. 0: [clearing condition] when the slave processor reads idr 1: [setting condition] when the host processor writes to idr using i/o write cycle 0 obf2 0 r/(w) * r output buffer full set to 1 when the slave processor (this lsi) writes to odr. cleared to 0 when the host processor reads odr. 0: [clearing condition] when the host processor reads odr using i/o read cycle, or the slave processor writes 0 to the obf bit 1: [setting condition] when the slave processor writes to odr note: * only 0 can be written to clear the flag. rev. 2.0, 08/02, page 523 of 788 str3 (twre = 1 or selstr3 = 0) r/w bit bit name initial value slave host description 7 ibf3b 0 r r bidirectional data register input buffer full set to 1 when the host processor writes to twr15. this is an internal interrupt source to the slave processor (this lsi). ibf3b is cleared to 0 when the slave processor reads twr15. 0: [clearing condition] when the slave processor reads twr15 1: [setting condition] when the host processor writes to twr15 using i/o write cycle 6obf3b0 r/(w) * r bidirectional data register output buffer full set to 1 when the slave processor (this lsi) writes to twr15. obf3b is cleared to 0 when the host processor reads twr15. 0: [clearing condition] when the host processor reads twr15 using i/o read cycle, or the slave processor writes 0 to the obf3b bit 1: [setting condition] when the slave processor writes to twr15 5 mwmf 0 r r master write mode flag set to 1 when the host processor writes to twr0. mwmf is cleared to 0 when the slave processor (this lsi) reads twr15. 0: [clearing condition] when the slave processor reads twr15 1: [setting condition] when the host processor writes to twr0 using i/o write cycle while swmf = 0 rev. 2.0, 08/02, page 524 of 788 r/w bit bit name initial value slave host description 4 swmf 0 r/(w) * r slave write mode flag set to 1 when the slave processor (this lsi) writes to twr0. in the event of simultaneous writes by the master and the slave, the master write has priority. swmf is cleared to 0 when the host reads twr15 0: [clearing condition] when the host processor reads twr15 using i/o read cycle, or the slave processor writes 0 to the swmf bit 1: [setting condition] when the slave processor writes to twr0 while mwmf = 0 3 c/d3 0 r r command/data when the host processor writes to an idr register, bit 2 of the i/o address is written into this bit to indicate whether idr contains data or a command. 0: contents of data register (idr) are data 1: contents of data register (idr) are a command 2 dbu32 0 r/w r defined by user the user can use this bit as necessary. 1 ibf3a 0 r r input buffer full set to 1 when the host processor writes to idr. this bit is an internal interrupt source to the slave processor (this lsi). ibf is cleared to 0 when the slave processor reads idr. the ibf1 flag setting and clearing conditions are different when the fast a20 gate is used. for details see table 19.3. 0: [clearing condition] when the slave processor reads idr 1: [setting condition] when the host processor writes to idr using i/o write cycle rev. 2.0, 08/02, page 525 of 788 r/w bit bit name initial value slave host description 0obf3a0 r/(w) * r output buffer full set to 1 when the slave processor (this lsi) writes to odr. obf3a is cleared to 0 when the host processor reads odr. 0: [clearing condition] when the host processor reads odr using i/o read cycle, or the slave processor writes 0 to the obf bit 1: [setting condition] when the slave processor writes to odr note: * only 0 can be written to clear the flag. str3 (twre = 0 and selstr3 = 1) r/w bit bit name initial value slave host description 7 6 5 4 dbu37 dbu36 dbu35 dbu34 0 0 0 0 r/w r/w r/w r/w r r r r defined by user the user can use these bits as necessary. 3c/ ' 3 0 r r command/data when the host processor writes to an idr register, bit 2 of the i/o address is written into this bit to indicate whether idr contains data or a command. 0: contents of data register (idr) are data 1: contents of data register (idr) are a command 2 dbu32 0 r/w r defined by user the user can use this bit as necessary. rev. 2.0, 08/02, page 526 of 788 r/w bit bit name initial value slave host description 1 ibf3a 0 r r input buffer full set to 1 when the host processor writes to idr. this bit is an internal interrupt source to the slave processor (this lsi). ibf is cleared to 0 when the slave processor reads idr. the ibf1 flag setting and clearing conditions are different when the fast a20 gate is used. for details see table 19.3. 0: [clearing condition] when the slave processor reads idr 1: [setting condition] when the host processor writes to idr using i/o write cycle 0obf3a0 r/(w) * r output buffer full set to 1 when the slave processor (this lsi) writes to odr. obf3a is cleared to 0 when the host processor reads odr. 0: [clearing condition] when the host processor reads odr using i/o read cycle, or the slave processor writes 0 to the obf bit 1: [setting condition] when the slave processor writes to odr note: * only 0 can be written to clear the flag. rev. 2.0, 08/02, page 527 of 788 19.3.8 serirq control registers 0 and 1 (sirqcr0, sirqcr1) the sirqcr registers contain status bits that indicate the serirq operating mode and bits that specify serirq interrupt sources. sirqcr0 r/w bit bit name initial value slave host description 7q/ & 0 r quiet/continuous mode flag indicates the mode specified by the host at the end of an serirq transfer cycle (stop frame). 0: continuous mode [clearing conditions] lpc hardware reset, lpc software reset specification by serirq transfer cycle stop frame 1: quiet mode [setting condition] specification by serirq transfer cycle stop frame. 6 selreq 0 r/w start frame initiation request select selects whether start frame initiation is requested when one or more interrupt requests are cleared, or when all interrupt requests are cleared, in quiet mode. 0: start frame initiation is requested when all interrupt requests are cleared in quiet mode. 1: start frame initiation is requested when one or more interrupt requests are cleared in quiet mode. 5 iedir 0 r/w interrupt enable direct mode specifies whether lpc channel 2 and channel 3 serirq interrupt source (smi, irq6, irq9 to irq11) generation is conditional upon obf, or is controlled only by the host interrupt enable bit. 0: host interrupt is requested when host interrupt enable bit and corresponding obf are both set to 1 1: host interrupt is requested when host interrupt enable bit is set to 1 rev. 2.0, 08/02, page 528 of 788 r/w bit bit name initial value slave host description 4 smie3b 0 r/w host smi interrupt enable 3b enables or disables a host smi interrupt request when obf3b is set by a twr15 write. 0: host smi interrupt request by obf3b and smie3b is disabled [clearing conditions] writing 0 to smie3b lpc hardware reset, lpc software reset clearing obf3b to 0 (when iedir = 0) 1: [when iedir = 0] host smi interrupt request by setting obf3b to 1 is enabled [when iedir = 1] host smi interrupt is requested [setting condition] writing 1 after reading smie3b = 0 3 smie3a 0 r/w host smi interrupt enable 3a enables or disables a host smi interrupt request when obf3a is set by an odr3 write. 0: host smi interrupt request by obf3a and smie3a is disabled [clearing conditions] writing 0 to smie3a lpc hardware reset, lpc software reset clearing obf3a to 0 (when iedir = 0) 1: [when iedir = 0] host smi interrupt request by setting obf3a to 1 is enabled [when iedir = 1] host smi interrupt is requested [setting condition] writing 1 after reading smie3a = 0 rev. 2.0, 08/02, page 529 of 788 r/w bit bit name initial value slave host description 2 smie2 0 r/w host smi interrupt enable 2 enables or disables a host smi interrupt request when obf2 is set by an odr2 write. 0: host smi interrupt request by obf2 and smie2 is disabled [clearing conditions] writing 0 to smie2 lpc hardware reset, lpc software reset clearing obf2 to 0 (when iedir = 0) 1: [when iedir = 0] host smi interrupt request by setting obf2 to 1 is enabled [when iedir = 1] host smi interrupt is requested [setting condition] writing 1 after reading smie2 = 0 1 irq12e1 0 r/w host irq12 interrupt enable 1 enables or disables a host irq12 interrupt request when obf1 is set by an odr1 write. 0: host irq12 interrupt request by obf1 and irq12e1 is disabled [clearing conditions] writing 0 to irq12e1 lpc hardware reset, lpc software reset clearing obf1 to 0 1: host irq12 interrupt request by setting obf1 to 1 is enabled [setting condition] writing 1 after reading irq12e1 = 0 rev. 2.0, 08/02, page 530 of 788 r/w bit bit name initial value slave host description 0 irq1e1 0 r/w host irq1 interrupt enable 1 enables or disables a host irq1 interrupt request when obf1 is set by an odr1 write. 0: host irq1 interrupt request by obf1 and irq1e1 is disabled [clearing conditions] writing 0 to irq1e1 lpc hardware reset, lpc software reset clearing obf1 to 0 1: host irq1 interrupt request by setting obf1 to 1 is enabled [setting condition] writing 1 after reading irq1e1 = 0 sirqcr1 r/w bit bit name initial value slave host description 7 irq11e3 0 r/w host irq11 interrupt enable 3 enables or disables a host irq11 interrupt request when obf3a is set by an odr3 write. 0: host irq11 interrupt request by obf3a and irq11e3 is disabled [clearing conditions] writing 0 to irq11e3 lpc hardware reset, lpc software reset clearing obf3a to 0 (when iedir = 0) 1: [when iedir = 0] host irq11 interrupt request by setting obf3a to 1 is enabled [when iedir = 1] host irq11 interrupt is requested. [setting condition] writing 1 after reading irq11e3 = 0 rev. 2.0, 08/02, page 531 of 788 r/w bit bit name initial value slave host description 6 irq10e3 0 r/w host irq10 interrupt enable 3 enables or disables a host irq10 interrupt request when obf3a is set by an odr3 write. 0: host irq10 interrupt request by obf3a and irq10e3 is disabled [clearing conditions] writing 0 to irq10e3 lpc hardware reset, lpc software reset clearing ob3fa to 0 (when iedir = 0) 1: [when iedir = 0] host irq10 interrupt request by setting obf3a to 1 is enabled [when iedir = 1] host irq10 interrupt is requested. [setting condition] writing 1 after reading irq10e3 = 0 5 irq9e3 0 r/w host irq9 interrupt enable 3 enables or disables a host irq9 interrupt request when obf3a is set by an odr3 write. 0: host irq9 interrupt request by obf3a and irq9e3 is disabled [clearing conditions] writing 0 to irq9e3 lpc hardware reset, lpc software reset clearing obf3a to 0 (when iedir = 0) 1: [when iedir = 0] host irq9 interrupt request by setting obf3a to 1 is enabled [when iedir = 1] host irq9 interrupt is requested. [setting condition] writing 1 after reading irq9e3 = 0 rev. 2.0, 08/02, page 532 of 788 r/w bit bit name initial value slave host description 4 irq6e3 0 r/w host irq6 interrupt enable 3 enables or disables a host irq6 interrupt request when obf3a is set by an odr3 write. 0: host irq6 interrupt request by obf3a and irq6e3 is disabled [clearing conditions] writing 0 to irq6e3 lpc hardware reset, lpc software reset clearing obf3a to 0 (when iedir = 0) 1: [when iedir = 0] host irq6 interrupt request by setting obf3a to 1 is enabled [when iedir = 1] host irq6 interrupt is requested. [setting condition] writing 1 after reading irq6e3 = 0 3 irq11e2 0 r/w host irq11 interrupt enable 2 enables or disables a host irq11 interrupt request when obf2 is set by an odr2 write. 0: host irq11 interrupt request by obf2 and irq11e2 is disabled [clearing conditions] writing 0 to irq11e2 lpc hardware reset, lpc software reset clearing obf2 to 0 (when iedir = 0) 1: [when iedir = 0] host irq11 interrupt request by setting obf2 to 1 is enabled [when iedir = 1] host irq11 interrupt is requested. [setting condition] writing 1 after reading irq11e2 = 0 rev. 2.0, 08/02, page 533 of 788 r/w bit bit name initial value slave host description 2 irq10e2 0 r/w host irq10 interrupt enable 2 enables or disables a host irq10 interrupt request when obf2 is set by an odr2 write. 0: host irq10 interrupt request by obf2 and irq10e2 is disabled [clearing conditions] writing 0 to irq10e2 lpc hardware reset, lpc software reset clearing obf2 to 0 (when iedir = 0) 1: [when iedir = 0] host irq10 interrupt request by setting obf2 to 1 is enabled [when iedir = 1] host irq10 interrupt is requested. [setting condition] writing 1 after reading irq10e2 = 0 1 irq9e2 0 r/w host irq9 interrupt enable 2 enables or disables a host irq9 interrupt request when obf2 is set by an odr2 write. 0: host irq9 interrupt request by obf2 and irq9e2 is disabled [clearing conditions] writing 0 to irq9e2 lpc hardware reset, lpc software reset clearing obf2 to 0 (when iedir = 0) 1: [when iedir = 0] host irq9 interrupt request by setting obf2 to 1 is enabled [when iedir = 1] host irq9 interrupt is requested. [setting condition] writing 1 after reading irq9e2 = 0 rev. 2.0, 08/02, page 534 of 788 r/w bit bit name initial value slave host description 0 irq6e2 0 r/w host irq6 interrupt enable 2 enables or disables a host irq6 interrupt request when obf2 is set by an odr2 write. 0: host irq6 interrupt request by obf2 and irq6e2 is disabled [clearing conditions] writing 0 to irq6e2 lpc hardware reset, lpc software reset clearing obf2 to 0 (when iedir = 0) 1: [when iedir = 0] host irq6 interrupt request by setting obf2 to 1 is enabled [when iedir = 1] host irq6 interrupt is requested. [setting condition] writing 1 after reading irq6e2 = 0 rev. 2.0, 08/02, page 535 of 788 19.3.9 host interface select register (hisel) hisel selects the function of bits 7 to 4 in str3 and specifies the output of the host interrupt request signal of each frame. r/w bit bit name initial value slave host description 7 selstr3 0 w str3 register function select 3 selects the function of bits 7 to 4 in str3 in combination with the twre bit in ladr3l. see description on str3 in section 19.3.7, status registers 1 to 3 (str1 to str3), for details. 0: bits 7 to 4 in str3 are status bits of the host interface. 1: [when twre = 1] bits 7 to 4 in str3 are status bits of the host interface. [when twre = 0] bits 7 to 4 in str3 are user bits. 6 5 4 3 2 1 0 selirq11 selirq10 selirq9 selirq6 selsmi selirq12 selirq1 0 0 0 0 0 1 1 w w w w w w w serirq output select selects the pin output status of host interrupt requests (hirq11, hirq10, hirq9, hirq6, smi, hirq12, and hirq1) of the lpc. 0: [when host interrupt request is cleared] serirq pin output is in the high-impedance state. [when host interrupt request is set] serirq pin output is 0. 1: [when host interrupt request is cleared] serirq pin output is 0. [when host interrupt request is set] serirq pin output is in the high-impedance state. rev. 2.0, 08/02, page 536 of 788 19.4 operation 19.4.1 host interface activation the host interface is activated by setting one of bits lpc3e to lpc1e in hicr0 to 1 in single- chip mode. when the host interface is activated, the related i/o ports (ports 37 to 30, ports 83 and 82) function as dedicated host interface input/output pins. in addition, setting the fga20e, pmee, lsmie, and lscie bits to 1 adds the related i/o ports (ports 81 and 80, ports b0 and b1) to the host interfaces input/output pins. use the following procedure to activate the host interface after a reset release. 1. read the signal line status and confirm that the lpc module can be connected. also check that the lpc module is initialized internally. 2. when using channel 3, set ladr3 to determine the channel 3 i/o address and whether bidirectional data registers are to be used. 3. set the enable bit (lpc3e to lpc1e) for the channel to be used. 4. set the enable bits (ga20e, pmee, lsmie, and lscie) for the additional functions to be used. 5. set the selection bits for other functions (sdwne, iedir). 6. as a precaution, clear the interrupt flags (lrst, sdwn, abrt, obf). read idr or twr15 to clear ibf. 7. set interrupt enable bits (ibfie3 to ibfie1, errie) as necessary. rev. 2.0, 08/02, page 537 of 788 19.4.2 lpc i/o cycles there are ten kinds of lpc transfer cycle: memory read, memory write, i/o read, i/o write, dma read, dma write, bus master memory read, bus master memory write, bus master i/o read, and bus master i/o write. of these, the chip's lpc supports only i/o read and i/o write cycles. an lpc transfer cycle is started when the /)5$0( signal goes low in the bus idle state. if the /)5$0( signal goes low when the bus is not idle, this means that a forced termination (abort) of the lpc transfer cycle has been requested. in an i/o read cycle or i/o write cycle, transfer is carried out using lad3 to lad0 in the following order, in synchronization with lclk. the host can be made to wait by sending back a value other than b 0000 in the slaves synchronization return cycle, but with the chips lpc a value of b 0000 is always returned. if the received address matches the host address in an lpc register (idr, odr, str, twr), the host interface enters the busy state; it returns to the idle state by output of a state count 12 turnaround. register and flag changes are made at this timing, so in the event of a transfer cycle forced termination (abort) before state #12, registers and flags are not changed. i/o read cycle i/o write cycle state count contents drive source value (3 to 0) contents drive source value (3 to 0) 1 start host 0000 start host 0000 2 cycle type/direction host 0000 cycle type/direction host 0010 3 address 1 host bits 15 to 12 address 1 host bits 15 to 12 4 address 2 host bits 11 to 8 address 2 host bits 11 to 8 5 address 3 host bits 7 to 4 address 3 host bits 7 to 4 6 address 4 host bits 3 to 0 address 4 host bits 3 to 0 7 turnaround (recovery) host 1111 data 1 host bits 3 to 0 8 turnaround none zzzz data 2 host bits 7 to 4 9 synchronization slave 0000 turnaround (recovery) host 1111 10 data 1 slave bits 3 to 0 turnaround none zzzz 11 data 2 slave bits 7 to 4 synchronization slave 0000 12 turnaround (recovery) slave 1111 turnaround (recovery) slave 1111 13 turnaround none zzzz turnaround none zzzz rev. 2.0, 08/02, page 538 of 788 the timing of the /)5$0( , lclk, and lad signals is shown in figures 19.2 and 19.3. addr start lad3Clad0 number of clocks lclk tar sync data tar start cycle type, direction, and size 114 1 2221 figure 19.2 typical /)5$0( /)5$0( /)5$0( /)5$0( timing addr start lad3Clad0 lclk tar sync cycle type, direction, and size slave must stop driving too many syncs cause timeout master will drive high figure 19.3 abort mechanism rev. 2.0, 08/02, page 539 of 788 19.4.3 a20 gate the a20 gate signal can mask address a20 to emulate an addressing mode used by personal computers with an 8086*-family cpu. a regular-speed a20 gate signal can be output under firmware control. the fast a20 gate function that is speeded up by hardware is enabled by setting the fga20e bit to 1 in hicr0. note: an intel microprocessor regular a20 gate operation: output of the a20 gate signal can be controlled by an h'd1 command followed by data. when the slave processor (this lsi) receives data, it normally uses an interrupt routine activated by the ibf1 interrupt to read idr1. at this time, firmware copies bit 1 of data following an h'd1 command and outputs it at the gate a20 pin. fast a20 gate operation: the internal state of ga20 output is initialized to 1 when fga20e = 0. when the fga20e bit is set to 1, p81/ga20 is used for output of a fast a20 gate signal. the state of the p81/ga20 pin can be monitored by reading the ga20 bit in hicr2. the initial output from this pin will be a logic 1, which is the initial value. afterward, the host processor can manipulate the output from this pin by sending commands and data. this function is only available via the idr1 register. the host interface decodes commands input from the host. when an h'd1 host command is detected, bit 1 of the data following the host command is output from the ga20 output pin. this operation does not depend on firmware or interrupts, and is faster than the regular processing using interrupts. table 19.3 shows the conditions that set and clear ga20 (p81). figure 19.4 shows the ga20 output in flowchart form. table 19.4 indicates the ga20 output signal values. table 19.3 ga20 (p81) set/clear timing pin name setting condition clearing condition ga20 (p81) when bit 1 of the data that follows an h'd1 host command is 1 when bit 1 of the data that follows an h'd1 host command is 0 rev. 2.0, 08/02, page 540 of 788 start wait for next byte h'd1 command received? host write host write yes no data byte? no write bit 1 of data byte to dr bit of p81/ga20 yes figure 19.4 ga20 output rev. 2.0, 08/02, page 541 of 788 table 19.4 fast a20 gate output signals ha0 data/command internal cpu interrupt flag (ibf) ga20 (p81) remarks 1 h'd1 command 0 q 0 1 data * 1 01 1 h'ff command 0 q (1) turn-on sequence 1 h'd1 command 0 q 0 0 data * 2 00 1 h'ff command 0 q (0) turn-off sequence 1 h'd1 command 0 q 0 1 data * 1 01 1/0 command other than h'ff and h'd1 1 q (1) turn-on sequence (abbreviated form) 1 h'd1 command 0 q 0 0 data * 2 00 1/0 command other than h'ff and h'd1 1 q (0) turn-off sequence (abbreviated form) 1 h'd1 command 0 q 1 command other than h'd1 1 q cancelled sequence 1 h'd1 command 0 q 1 h'd1 command 0 q retriggered sequence 1 h'd1 command 0 q 0 any data 0 1/0 1 h'd1 command 0 q (1/0) consecutively executed sequences notes: 1. arbitrary data with bit 1 set to 1. 2. arbitrary data with bit 1 cleared to 0. rev. 2.0, 08/02, page 542 of 788 19.4.4 host interface shutdown function (lpcpd) the host interface can be placed in the shutdown state according to the state of the /3&3' pin. there are two kinds of host interface shutdown state: lpc hardware shutdown and lpc software shutdown. the lpc hardware shutdown state is controlled by the /3&3' pin, while the software shutdown state is controlled by the sdwnb bit. in both states, the host interface enters the reset state by itself, and is no longer affected by external signals other than the /5(6(7 and /3&3' signals. placing the slave processor in sleep mode or software standby mode is effective in reducing current dissipation in the shutdown state. if software standby mode is set, some means must be provided for exiting software standby mode before clearing the shutdown state with the /3&3' signal. if the sdwne bit has been set to 1 beforehand, the lpc hardware shutdown state is entered at the same time as the /3&3' signal falls, and prior preparation is not possible. if the lpc software shutdown state is set by means of the sdwnb bit, on the other hand, the lpc software shutdown state cannot be cleared at the same time as the rise of the /3&3' signal. taking these points into consideration, the following operating procedure uses a combination of lpc software shutdown and lpc hardware shutdown. 1. clear the sdwne bit to 0. 2. set the errie bit to 1 and wait for an interrupt by the sdwn flag. 3. when an erri interrupt is generated by the sdwn flag, check the host interface internal status flags and perform any necessary processing. 4. set the sdwnb bit to 1 to set lpc software standby mode. 5. set the sdwne bit to 1 and make a transition to lpc hardware standby mode. the sdwnb bit is cleared automatically. 6. check the state of the /3&3' signal to make sure that the /3&3' signal has not risen during steps 3 to 5. if the signal has risen, clear sdwne to 0 to return to the state in step 1. 7. place the slave processor in sleep mode or software standby mode as necessary. 8. if software standby mode has been set, exit software standby mode by some means independent of the lpc. 9. when a rising edge is detected in the /3&3' signal, the sdwne bit is automatically cleared to 0. if the slave processor has been placed in sleep mode, the mode is exited by means of /5(6(7 signal input, on completion of the lpc transfer cycle, or by some other means. rev. 2.0, 08/02, page 543 of 788 table 19.5 shows the scope of the host interface pin shutdown. table 19.5 scope of host interface pin shutdown abbreviation port scope of shutdown i/o notes lad3 to lad0 p33Cp30 o i/o hi-z /)5$0( p34 o input hi-z /5(6(7 p35 input lpc hardware reset function is active lclk p36 o input hi-z serirq p37 o i/o hi-z lsci pb1 d i/o hi-z, only when lscie = 1 /60, pb0 d i/o hi-z, only when lsmie = 1 30( p80 d i/o hi-z, only when pmee = 1 ga20 p81 d i/o hi-z, only when fga20e = 1 &/.581 p82 o i/o hi-z /3&3' p83 input needed to clear shutdown state legend o: pin that is shutdown by the shutdown function d : pin that is shutdown only when the lpc function is selected by register setting : pin that is not shutdown in the lpc shutdown state, the lpcs internal state and some register bits are initialized. the order of priority of lpc shutdown and reset states is as follows. 1. system reset (reset by 67%< or 5(6 pin input, or wdt0 overflow) ? all register bits, including bits lpc3e to lpc1e, are initialized. 2. lpc hardware reset (reset by /5(6(7 pin input) ? lrstb, sdwne, and sdwnb bits are cleared to 0. 3. lpc software reset (reset by lrstb) ? sdwne and sdwnb bits are cleared to 0. 4. lpc hardware shutdown ? sdwnb bit is cleared to 0. 5. lpc software shutdown rev. 2.0, 08/02, page 544 of 788 the scope of the initialization in each mode is shown in table 19.6. table 19.6 scope of initialization in each host interface mode items initialized system reset lpc reset lpc shutdown lpc transfer cycle sequencer (internal state), lpcbsy and abrt flags initialized initialized initialized serirq transfer cycle sequencer (internal state), clkreq and irqbsy flags initialized initialized initialized host interface flags (ibf1, ibf2, ibf3a, ibf3b, mwmf, c/ ' 1, c/ ' 2, c/ ' 3, obf1, obf2, obf3a, obf3b, swmf, dbu), ga20 (internal state) initialized initialized retained host interrupt enable bits (irq1e1, irq12e1, smie2, irq6e2, irq9e2 to irq11e2, smie3b, smie3a, irq6e3, irq9e3 to irq11e3), q/ & flag, selreq bit initialized initialized retained lrst flag initialized (0) can be set/cleared can be set/cleared sdwn flag initialized (0) initialized (0) can be set/cleared lrstb bit initialized (0) hr: 0 sr: 1 0 (can be set) sdwnb bit initialized (0) initialized (0) hs: 0 ss: 1 sdwne bit initialized (0) initialized (0) hs: 1 ss: 0 or 1 host interface operation control bits (lpc3e to lpc1e, fga20e, ladr3, ibfie1 to ibfie3, pmee, pmeb, lsmie, lsmib, lscie, lscib, twre, selstr3, selirq1, selsmi, selirq6, selirq9, selirq10, selirq11, selirq12) initialized retained retained /5(6(7 signal input (port function input input /3&3' signal input input lad3 to lad0, /)5$0( , lclk, serirq, &/.581 signals input hi-z 30( , /60, , lsci, ga20 signals (when function is selected) output hi-z 30( , /60, , lsci, ga20 signals (when function is not selected) port function port function note: system reset: reset by stby input, res input, or wdt overflow lpc reset: reset by lpc hardware reset (hr) or lpc software reset (sr) rev. 2.0, 08/02, page 545 of 788 lpc shutdown: reset by lpc hardware shutdown (hs) or lpc software shutdown (ss) figure 19.5 shows the timing of the /3&3' and /5(6(7 signals. lad3Clad0 lclk at least 30 m s at least 100 m s at least 60 m s figure 19.5 power-down state termination timing rev. 2.0, 08/02, page 546 of 788 19.4.5 host interface serialized interrupt operation (serirq) a host interrupt request can be issued from the host interface by means of the serirq pin. in a host interrupt request via the serirq pin, lclk cycles are counted from the start frame of the serialized interrupt transfer cycle generated by the host or a peripheral function, and a request signal is generated by the frame corresponding to that interrupt. the timing is shown in figure 19.6. irq1 irq1 host controller none none serirq drive source lclk start start frame irq0 frame irq1 frame irq2 frame sl or h hrtr st r st r st irq15 host controller none none serirq driver lclk start stop frame stop frame next cycle irq14 frame irq15 frame r st r st r st rt h i h = host control, sl = slave control, r = recovery, t = turnaround, s = sample h = host control, r = recovery, t = turnaround, s = sample, i = idle figure 19.6 serirq timing the serialized interrupt transfer cycle frame configuration is as follows. two of the states comprising each frame are the recover state in which the serirq signal is returned to the 1-level at the end of the frame, and the turnaround state in which the serirq signal is not driven. the recover state must be driven by the host or slave processor that was driving the preceding state. rev. 2.0, 08/02, page 547 of 788 serial interrupt transfer cycle frame count contents drive source number of states notes 0 start slave host 6 in quiet mode only, slave drive possible in first state, then next 3 states 0-driven by host 1irq0 slave3 2 irq1 slave 3 drive possible in lpc channel 1 3 smi slave 3 drive possible in lpc channels 2 and 3 4irq3 slave3 5irq4 slave3 6irq5 slave3 7 irq6 slave 3 drive possible in lpc channels 2 and 3 8irq7 slave3 9irq8 slave3 10 irq9 slave 3 drive possible in lpc channels 2 and 3 11 irq10 slave 3 drive possible in lpc channels 2 and 3 12 irq11 slave 3 drive possible in lpc channels 2 and 3 13 irq12 slave 3 drive possible in lpc channel 1 14 irq13 slave 3 15 irq14 slave 3 16 irq15 slave 3 17 iochck slave 3 18 stop host undefined first, 1 or more idle states, then 2 or 3 states 0-driven by host 2 states: quiet mode next 3 states: continuous mode next there are two modescontinuous mode and quiet modefor serialized interrupts. the mode initiated in the next transfer cycle is selected by the stop frame of the serialized interrupt transfer cycle that ended before that cycle. in continuous mode, the host initiates host interrupt transfer cycles at regular intervals. in quiet mode, the slave processor with interrupt sources requiring a request can also initiate an interrupt transfer cycle, in addition to the host. in quiet mode, since the host does not necessarily initiate interrupt transfer cycles, it is possible to suspend the clock (lclk) supply and enter the power- down state. in order for a slave to transfer an interrupt request in this case, a request to restart the clock must first be issued to the host. for details see section 19.4.6, host interface clock start request (clkrun). rev. 2.0, 08/02, page 548 of 788 19.4.6 host interface clock start request (clkrun) a request to restart the clock (lclk) can be sent to the host processor by means of the &/.581 pin. with lpc data transfer and serirq in continuous mode, a clock restart is never requested since the transfer cycles are initiated by the host. with serirq in quiet mode, when a host interrupt request is generated the &/.581 signal is driven and a clock (lclk) restart request is sent to the host. the timing for this operation is shown in figure 19.7. clk pull-up enable drive by the host processor drive by the slave processor 1 2 3 4 5 6 figure 19.7 clock start request timing cases other than serirq in quiet mode when clock restart is required must be handled with a different protocol, using the 30( signal, etc. 19.5 interrupt sources 19.5.1 ibfi1, ibfi2, ibfi3, and erri the host interface has four interrupt requests for the slave processor (this lsi): ibf1, ibf2, ibf3, and erri. ibfi1, ibfi2, and ibfi3 are idr receive complete interrupts for idr1, idr2, and idr3 and twr, respectively. the erri interrupt indicates the occurrence of a special state such as an lpc reset, lpc shutdown, or transfer cycle abort. an interrupt request is enabled by setting the corresponding enable bit. table 19.7 receive complete interrupts and error interrupt interrupt description ibfi1 when ibfie1 is set to 1 and idr1 reception is completed ibfi2 when ibfie2 is set to 1 and idr2 reception is completed ibfi3 when ibfie3 is set to 1 and idr3 reception is completed, or when twre and ibfie3 are set to 1 and reception is completed up to twr15 erri when errie is set to 1 and one of lrst, sdwn and abrt is set to 1 rev. 2.0, 08/02, page 549 of 788 19.5.2 smi, hirq1, hirq6, hirq9, hirq10, hirq11, and hirq12 the host interface can request seven kinds of host interrupt by means of serirq. hirq1 and hirq12 are used on lpc channel 1 only, while smi, hirq6, hirq9, hirq10, and hirq11 can be requested from lpc channel 2 or 3. there are two ways of clearing a host interrupt request. when the iedir bit is cleared to 0 in sirqcr0, host interrupt sources and lpc channels are all linked to the host interrupt request enable bits. when the obf flag is cleared to 0 by a read of odr or twr15 by the host in the corresponding lpc channel, the corresponding host interrupt enable bit is automatically cleared to 0, and the host interrupt request is cleared. when the iedir bit is set to 1 in sirqcr0, lpc channel 2 and 3 interrupt requests are dependent only upon the host interrupt enable bits. the host interrupt enable bit is not cleared when obf for channel 2 or 3 is cleared. therefore, smie2, smie3a and smie3b, irq6e2 and irq6e3, irq9e2 and irq9e3, irq10e2 and irq10e3, and irq11e2 and irq11e3 lose their respective functional differences. in order to clear a host interrupt request, it is necessary to clear the host interrupt enable bit. rev. 2.0, 08/02, page 550 of 788 table 19.8 summarizes the methods of setting and clearing these bits, and figure 19.8 shows the processing flowchart. table 19.8 hirq setting and clearing conditions host interrupt setting condition clearing condition hirq1 (independent from iedir) internal cpu writes to odr1, then reads 0 from bit irq1e1 and writes 1 internal cpu writes 0 to bit irq1e1, or host reads odr1 hirq12 (independent from iedir) internal cpu writes to odr1, then reads 0 from bit irq12e1 and writes 1 internal cpu writes 0 to bit irq12e1, or host reads odr1 smi (iedir = 0) internal cpu writes to odr2, then reads 0 from bit smie2 and writes 1 writes to odr3, then reads 0 from bit smie3a and writes 1 writes to twr15, then reads 0 from bit smie3b and writes 1 internal cpu writes 0 to bit smie2, or host reads odr2 writes 0 to bit smie3a, or host reads odr3 writes 0 to bit smie3b, or host reads twr15 smi (iedir = 1) internal cpu reads 0 from bit smie2, then writes 1 reads 0 from bit smie3a, then writes 1 reads 0 from bit smie3b, then writes 1 internal cpu writes 0 to bit smie2 writes 0 to bit smie3a writes 0 to bit smie3b hirqi (i = 6, 9, 10, 11) (iedir = 0) internal cpu writes to odr2, then reads 0 from bit irqie2 and writes 1 writes to odr3, then reads 0 from bit irqie3 and writes 1 internal cpu writes 0 to bit irqie2, or host reads odr2 cpu writes 0 to bit irqie3, or host reads odr3 hirqi (i = 6, 9, 10, 11) (iedir = 1) internal cpu reads 0 from bit irqie2, then writes 1 reads 0 from bit irqie3, then writes 1 internal cpu writes 0 to bit irqie2 writes 0 to bit irqie3 rev. 2.0, 08/02, page 551 of 788 slave cpu master cpu odr1 write write 1 to irq1e1 obf1 = 0? yes no no yes all bytes transferred? serirq irq1 output serirq irq1 source clearance interrupt initiation odr1 read hardware operation software operation figure 19.8 hirq flowchart (example of channel 1) 19.6 usage notes 19.6.1 module stop mode setting lpc operation can be enabled or disabled using the module stop control register. the initial setting is for lpc operation to be halted. register access is enabled by canceling module stop mode. for details, refer to section 26, power-down modes. 19.6.2 notes on using host interface the host interface provides buffering of asynchronous data from the host processor and slave processor (this lsi), but an interface protocol that uses the flags in str must be followed to avoid data contention. for example, if the host and slave processor both try to access idr or odr at the same time, the data will be corrupted. to prevent simultaneous accesses, ibf and obf must be used to allow access only to data for which writing has finished. unlike the idr and odr registers, the transfer direction is not fixed for the bidirectional data registers (twr). mwmf and swmf are provided in str to handle this situation. after writing rev. 2.0, 08/02, page 552 of 788 to twr0, mwmf and swmf must be used to confirm that the write authority for twr1 to twr15 has been obtained. table 19.9 shows host address examples for ladr3 and registers, idr3, odr3, str3, twr0mw, twr0sw, and twr1 to twr15 when ladr3 = h'a24f and ladr3 = h'3fd0. table 19.9 host address example register host address when ladr3 = h'a24f host address when ladr3 = h'3fd0 idr3 h'a24a and h'a24e h'3fd0 and h'3fd4 odr3 h'a24a h'3fd0 str3 h'a24e h'3fd4 twr0mw h'a250 h'3fc0 twr0sw h'a250 h'3fc0 twr1 h'a251 h'3fc1 twr2 h'a252 h'3fc2 twr3 h'a253 h'3fc3 twr4 h'a254 h'3fc4 twr5 h'a255 h'3fc5 twr6 h'a256 h'3fc6 twr7 h'a257 h'3fc7 twr8 h'a258 h'3fc8 twr9 h'a259 h'3fc9 twr10 h'a25a h'3fca twr11 h'a25b h'3fcb twr12 h'a25c h'3fcc twr13 h'a25d h'3fcd twr14 h'a25e h'3fce twr15 h'a25f h'3fcf rev. 2.0, 08/02, page 553 of 788 section 20 d/a converter 20.1 features 8-bit resolution two output channels conversion time: max. 10 s (when load capacitance is 20 pf) output voltage: 0 v to avref d/a output retaining function in software standby mode module data bus internal data bus avref avcc da1 da0 avss 8-bit d/a control circuit d a d r 0 d a d r 1 d a c r legend dacr : d/a control register dadr0 : d/a data register 0 dadr1 : d/a data register 1 bus interface figure 20.1 block diagram of d/a converter dac0002a_010020020700 rev. 2.0, 08/02, page 554 of 788 20.2 input/output pins table 20.1 summarizes the input/output pins used by the d/a converter. table 20.1 pin configuration pin name symbol i/o function analog power supply pin avcc input analog block power supply analog ground pin avss input analog block ground and reference voltage analog output pin 0 da0 output channel 0 analog output analog output pin 1 da1 output channel 1 analog output reference power supply pin avref input analog block reference voltage 20.3 register descriptions the d/a converter has the following registers. d/a data register 0 (dadr0) d/a data register 1 (dadr1) d/a control register (dacr) 20.3.1 d/a data registers 0 and 1 (dadr0, dadr1) dadr0 and dadr1 are 8-bit readable/writable registers that store data for d/a conversion. when analog output is permitted, d/a data register contents are converted and output to analog output pins. dadr0 and dadr1 are initialized to h 00. rev. 2.0, 08/02, page 555 of 788 20.3.2 d/a control register (dacr) dacr controls d/a converter operation. bit bit name initial value r/w description 7 daoe1 0 r/w d/a output enable 1 controls d/a conversion and analog output. 0: analog output da1 is disabled 1: d/a conversion for channel 1 and analog output da1 are enabled 6 daoe0 0 r/w d/a output enable 0 controls d/a conversion and analog output. 0: analog output da0 is disabled 1: d/a conversion for channel 0 and analog output da0 are enabled 5 dae 0 r/w d/a enable controls d/a conversion in conjunction with the daoe0 and daoe1 bits. when the dae bit is cleared to 0, d/a conversion for channels 0 and 1 is controlled individually. when the dae bit is set to 1, d/a conversion for channels 0 and 1 are controlled as one. conversion result output is controlled by the daoe0 and daoe1 bits. for details, see table 20.2 below. 4 to 0 all 1 r reserved these bits are always read as 1 and cannot be modified. table 20.2 d/a channel enable bit 7 bit 6 bit 5 daoe1 daoe0 dae description 0 disables d/a conversion enables d/a conversion for channel 0 0 disables d/a conversion for channel 1 0 1 1 enables d/a conversion for channels 0 and 1 disables d/a conversion for channel 0 0 enables d/a conversion for channel 1 0 1 enables d/a conversion for channels 0 and 1 1 1 enables d/a conversion for channels 0 and 1 rev. 2.0, 08/02, page 556 of 788 20.4 operation the d/a converter incorporates two channels of the d/a circuits and can be converted individually. when the daoe bit in dacr is set to 1, d/a conversion is enabled and conversion results are output. an example of d/a conversion of channel 0 is shown below. the operation timing is shown in figure 20.2. 1. write conversion data to dadr0. 2. when the daoe0 bit in dacr is set to 1, d/a conversion starts. after the interval of t dconv , conversion results are output from the analog output pin da0. the conversion results are output continuously until dadr0 is modified or the daoe0 bit is cleared to 0. the output value is calculated by the following formula: dadr contents/256 avref 3. conversion starts immediately after dadr0 is modified. after the interval of t dconv , conversion results are output. 4. when the daoe0 bit is cleared to 0, analog output is disabled. dadr0 write cycle dacr write cycle dadr0 write cycle dacr write cycle address ? dadr0 daoe0 da 0 conversion data ( 1) conversion data ( 2) high impedance state conversion result ( 1) conversion result ( 2) t dconv t dconv legend tdconv: d/a conversion time figure 20.2 d/a converter operation example rev. 2.0, 08/02, page 557 of 788 20.5 usage note when this lsi enters software standby mode with d/a conversion enabled, the d/a output is retained, and the analog power supply current is equal to as during d/a conversion. if the analog power supply current needs to be reduced in software standby mode, clear the daoe1, daoe0, and dae bits all to 0 to disable d/a output. 20.5.1 module stop mode setting d/a converter operation can be enabled or disabled using the module stop control register. the initial setting is for d/a converter operation to be halted. register access is enabled by canceling module stop mode. for details, refer to section 26, power-down modes. rev. 2.0, 08/02, page 558 of 788 rev. 2.0, 08/02, page 559 of 788 section 21 a/d converter this lsi includes a successive-approximation-type 10-bit a/d converter that allows up to eight analog input channels and up to 16 digital input to be selected. a/d conversion for digital input is effective as a comparator in multiple input testing. 21.1 features 10-bit resolution i nput channels: eight analog input channels and 16 digital input channels analog conversion voltage range can be specified using the reference power supply voltage pin (avref) as an analog reference voltage. conversion time: 13.4 s per channel (at 10-mhz operation) two kinds of operating modes ? single mode: single-channel a/d conversion ? scan mode: continuous a/d conversion on 1 to 4 channels four data registers ? conversion results are held in a 16-bit data register for each channel sample and hold function three kinds of conversion start ? software, 8-bit timer (tmr) conversion start trigger, or external trigger signal. interrupt request ? a/d conversion end interrupt (adi) request can be generated adcms33a_010020020700 rev. 2.0, 08/02, page 560 of 788 a block diagram of the a/d converter is shown in figure 21.1. module data bus control circuit internal data bus 10-bit d/a comparator + sample-and-hold circuit ?/16 adi interrupt signal a d c s r a d c r a d d r d a d d r c a d d r b a d d r a successive approximations register legend adcr : a/d control register adcsr : a/d control/status register addra : a/d data register a addrb : a/d data register b addrc : a/d data register c addrd : a/d data register d conversion start trigger from 8-bit timer ?/8 av cc av ss av ref multiplexer bus interface an0 an1 an2 an3 an4 an5 an6 /cin0 to cin7 an7/cin8 to cin15 figure 21.1 block diagram of a/d converter rev. 2.0, 08/02, page 561 of 788 21.2 input/output pins table 21.1 summarizes the pins used by the a/d converter. the 8 analog input pins are divided into two groups consisting of four channels. analog input pins 0 to 3 (an0 to an3) comprising group 0 and analog input pins 4 to 7 (an4 to an7) comprising group 1. expanded a/d conversion input pins (cin0 to cin15) can be selected with the an6 and an7 pins. the avcc and avss pins are the power supply pins for the analog block in the a/d converter. table 21.1 pin configuration pin name symbol i/o function analog power supply pin av cc input analog block power supply and reference voltage analog ground pin av ss input analog block ground and reference voltage reference power supply pin avref input reference voltage for a/d conversion analog input pin 0 an0 input analog input pin 1 an1 input analog input pin 2 an2 input analog input pin 3 an3 input group 0 analog input pins analog input pin 4 an4 input analog input pin 5 an5 input analog input pin 6 an6 input analog input pin 7 an7 input group 1 analog input pins a/d external trigger input pin $'75* input external trigger input pin for starting a/d conversion expanded a/d conversion input pins 0 to 15 cin0 to cin15 input expanded a/d conversion input (digital input) channels 0 to 15 can be used as digital input pins rev. 2.0, 08/02, page 562 of 788 21.3 register descriptions the a/d converter has the following registers. a/d data register a (addra) a/d data register b (addrb) a/d data register c (addrc) a/d data register d (addrd) a/d control/status register (adcsr) a/d control register (adcr) keyboard comparator control register (kbcomp) 21.3.1 a/d data registers a to d (addra to addrd) there are four 16-bit read-only addr registers, addra to addrd, used to store the results of a/d conversion. the addr registers, which store a conversion result for each channel, are shown in table 21.2. the converted 10-bit data is stored to bits 15 to 6. the lower 6-bit data is always read as 0. the data bus between the cpu and the a/d converter is 8-bit width. the upper byte can be read directly from the cpu, but the lower byte should be read via a temporary register. the temporary register contents are transferred from the addr when the upper byte data is read. when reading the addr, read the upper byte before lower byte or in word units. table 21.2 analog input channels and corresponding addr registers analog input channel group 0 group 1 a/d data register to store a/d conversion results an0 an4 addra an1 an5 addrb an2 an6, or cin0 to cin7 addrc an3 an7, or cin8 to cin15 addrd rev. 2.0, 08/02, page 563 of 788 21.3.2 a/d control/status register (adcsr) adcsr controls a/d conversion operations. bit bit name initial value r/w description 7adf 0 r/(w) * a/d end flag a status flag that indicates the end of a/d conversion. [setting conditions] when a/d conversion ends in single mode when a/d conversion ends on all channels specified in scan mode [clearing conditions] when 0 is written after reading adf = 1 when dtc starts by an adi interrupt and addr is read 6 adie 0 r/w a/d interrupt enable enables adi interrupt by adf when this bit is set to 1 5 adst 0 r/w a/d start setting this bit to 1 starts a/d conversion. clearing this bit to 0 stops a/d conversion. in single mode, this bit is cleared to 0 automatically when conversion on the specified channel ends. in scan mode, conversion continues sequentially on the specified channels until this bit is cleared to 0 by software, a reset, or a transition to standby mode or module stop mode. 4 scan 0 r/w scan mode selects the a/d conversion operating mode. the setting of this bit must be made when conversion is halted (adst = 0). 0: single mode 1: scan mode 3 cks 0 r/w clock select sets a/d conversion time. the input channel setting must be made when conversion is halted (adst = 0). 0: conversion time is 266 states (max) 1: conversion time is 134 states (max) switch conversion time while adst is 0. rev. 2.0, 08/02, page 564 of 788 bit bit name initial value r/w description channel select 2 to 0 select analog input channels. the input channel setting must be made when conversion is halted (adst = 0). 2 1 0 ch2 ch1 ch0 0 0 0 r/w r/w r/w when scan = 0: 000: an0 001: an1 010: an2 011: an3 100: an4 101: an5 110: an6, or cin0 to cin7 111: an7, or cin8 to cin15 when scan = 1: 000: an0 001: an0 and an1 010: an0 to an2 011: an0 to an3 100: an4 101: an4 and an5 110: an4 to an6 or cin0 to cin7 111: an4 to an6 or cin0 to cin7, or an7 or cin8 to cin15 note: * only 0 can be written for clearing the flag. 21.3.3 a/d control register (adcr) adcr enables a/d conversion started by an external trigger signal. bit bit name initial value r/w description 7 6 trgs1 trgs0 0 0 r/w r/w timer trigger select 1 and 0 enable the start of a/d conversion by a trigger signal. only set bits trgs1 and trgs0 when conversion is halted (adst = 0). 00: a/d conversion start by external trigger is disabled 01: a/d conversion start by external trigger is disabled 10: a/d conversion start by conversion trigger from tmr is enabled 11: a/d conversion start by $'75* pin is enabled 5 to 0 all 1 r reserved these bits are always read as 1 and cannot be modified. rev. 2.0, 08/02, page 565 of 788 21.3.4 keyboard comparator control register (kbcomp) kbcomp selects the cin input channel for which a/d conversion is performed and enables or disables the comparator scan function of cin7 to cin0. bit bit name initial value r/w description 7ire 0 r/w 6 ircks2 0 r/w 5 ircks1 0 r/w 4 ircks0 0 r/w these bits are related to the sci. for details, refer to section 15.3.10, keyboard comparator control register (kbcomp). 3 kbade 0 r/w keyboard a/d enable (an6, an7) selects whether channels 6 and 7 of the a/d converter are used as analog pins or digital pins, in combination with the kbch2 to kbch0 bits. for details, refer to description for bits 2 to 0. analog pins of the a/d converter are set to digital pins (cin0 to cin7 and cin8 to cin15). 2 1 0 kbch2 kbch1 kbch0 0 0 0 r/w r/w r/w keyboard a/d channel select 2 to 0 these bits select a channel of digital input pins for a/d conversion, in combination with the kbade bit. the input channel setting must be made while conversion is halted. channel 6 channel 7 0xxx: selects an6 an7 1000: selects cin0 cin8 1001: selects cin1 cin9 1010: selects cin2 cin10 1011: selects cin3 cin11 1100: selects cin4 cin12 1101: selects cin5 cin13 1110: selects cin6 cin14 1111: selects cin7 cin15 legend x: dont care rev. 2.0, 08/02, page 566 of 788 21.4 operation the a/d converter operates by successive approximation with 10-bit resolution. it has two operating modes: single mode and scan mode. when changing the operating mode or analog input channel, to prevent incorrect operation, first clear the adst bit to 0 in adcsr to halt a/d conversion. the adst bit can be set at the same time as the operating mode or analog input channel is changed. 21.4.1 single mode in single mode, a/d conversion is to be performed only once on the specified single channel. operations are as follows. 1. a/d conversion on the specified channel is started when the adst bit in adcsr is set to 1, by software or an external trigger input. 2. when a/d conversion is completed, the result is transferred to the a/d data register corresponding to the channel. 3. on completion of a/d conversion, the adf bit in adcsr is set to 1. if the adie bit is set to 1 at this time, an adi interrupt request is generated. 4. the adst bit remains set to 1 during a/d conversion. when conversion ends, the adst bit is automatically cleared to 0, and the a/d converter enters wait state. 21.4.2 scan mode scan mode is useful for monitoring analog inputs in a group of one or more channels. when the adst bit is set to 1 by software, or by timer or external trigger input, a/d conversion starts on the first channel in the group (an0 when ch2 = 0; an4 when ch2 = 1). when two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (an1 or an5) starts immediately. a/d conversion continues cyclically on the selected channels until the adst bit is cleared to 0. the conversion results are transferred for storage into the addr registers corresponding to the channels. typical operations when three channels (an0 to an2) are selected in scan mode are described below. rev. 2.0, 08/02, page 567 of 788 figure 21.2 shows the operation timing. 1. scan mode is selected (scan = 1), scan group 0 is selected (ch2 = 0), analog input channels an0 to an2 are selected (ch1 = 1, ch0 = 0), and a/d conversion is started (adst = 1). 2. when a/d conversion of the first channel (an0) is completed, the result is transferred to addra. next, conversion of the second channel (an1) starts automatically. 3. conversion proceeds in the same way through the third channel (an2). 4. when conversion of all the selected channels (an0 to an2) is completed, the adf flag is set to 1 and conversion of the first channel (an0) starts again. if the adie bit is set to 1 at this time, an adi interrupt is requested after a/d conversion ends. 5. steps 2 to 4 are repeated as long as the adst bit remains set to 1. when the adst bit is cleared to 0, a/d conversion stops. after that, if the adst bit is set to 1, a/d conversion starts again from the first channel (an0). adst adf addra addrb addrc addrd state of channel 0 (an0) state of channel 1 (an1) state of channel 2 (an2) state of channel 3 (an3) set * 1 clear * 1 idle notes: 1. vertical arrows ( ) indicate instructions executed by software. 2. data currently being converted is ignored. clear * 1 idle idle a/d conversion time idle continuous a/d conversion execution a/d conversion 1 idle idle idle idle idle transfer * 2 a/d conversion 3 a/d conversion 2 a/d conversion 5 a/d conversion 4 a/d conversion result 1 a/d conversion result 2 a/d conversion result 3 a/d conversion result 4 figure 21.2 example of a/d converter operation (scan mode, channels an0 to an2 selected) rev. 2.0, 08/02, page 568 of 788 21.4.3 input sampling and a/d conversion time the a/d converter has a built-in sample-and-hold circuit. the a/d converter samples the analog input when the a/d conversion start delay time (t d ) passes after the adst bit in adcsr is set to 1, then starts a/d conversion. figure 21.3 shows the a/d conversion timing. table 21.3 indicates the a/d conversion time. as indicated in figure 21.3, the a/d conversion time (t conv ) includes t d and the input sampling time (t spl ). the length of t d varies depending on the timing of the write access to adcsr. the total conversion time therefore varies within the ranges indicated in table 21.3. in scan mode, the values given in table 21.3 apply to the first conversion time. in the second and subsequent conversions, the conversion time is 256 state (fixed) when cks = 0 and 128 states (fixed) when cks = 1. ? address write signal input sampling timing adf legend (1) : adcsr write cycle (2) : adcsr address t d : a/d conversion start delay t spl : input sampling time t conv : a/d conversion time (1) (2) t d t spl t conv figure 21.3 a/d conversion timing rev. 2.0, 08/02, page 569 of 788 table 21.3 a/d conversion time (single mode) cks = 0 cks = 1 item symbol min typ max min typ max a/d conversion start delay time t d 10176 9 input sampling time t spl 6331 a/d conversion time t conv 259 266 131 134 note: * values in the table indicate the number of states. 21.4.4 external trigger input timing a/d conversion can be externally triggered. when the trgs1 and trgs0 bits are set to b11 in adcr, external trigger input is enabled at the $'75* pin. a falling edge at the $'75* pin sets the adst bit to 1 in adcsr, starting a/d conversion. other operations, in both single and scan modes, are the same as when the adst bit has been set to 1 by software. figure 21.4 shows the timing. ? internal trigger signal adst a/d conversion figure 21.4 external trigger input timing 21.5 interrupt sources the a/d converter generates an a/d conversion end interrupt (adi) at the end of a/d conversion. setting the adie bit to 1 enables adi interrupt requests while the adf bit in adcsr is set to 1 after a/d conversion is completed. rev. 2.0, 08/02, page 570 of 788 21.6 a/d conversion accuracy definitions this lsis a/d conversion accuracy definitions are given below. resolution the number of a/d converter digital output codes quantization error the deviation inherent in the a/d converter, given by 1/2 lsb (see figure 21.5). offset error the deviation of the analog input voltage value from the ideal a/d conversion characteristic when the digital output changes from the minimum voltage value b'0000000000 (h'000) to b'0000000001 (h'001) (see figure 21.6). full-scale error the deviation of the analog input voltage value from the ideal a/d conversion characteristic when the digital output changes from b'1111111110 (h'3fe) to b'1111111111 (h'3ff) (see figure 21.6). nonlinearity error the error with respect to the ideal a/d conversion characteristics between the zero voltage and the full-scale voltage. does not include the offset error, full-scale error, or quantization error (see figure 21.6). absolute accuracy the deviation between the digital value and the analog input value. includes the offset error, full-scale error, quantization error, and nonlinearity error. rev. 2.0, 08/02, page 571 of 788 h'001 h'000 1 1024 2 1024 1022 1024 1023 1024 fs quantization error digital output ideal a/d conversion characteristic analog input voltage h'002 h'003 h'004 h'3fd h'3fe h'3ff figure 21.5 a/d conversion accuracy definitions fs offset error nonlinearity error actual a/d conversion characteristic analog input voltage digital output ideal a/d conversion characteristic full-scale error figure 21.6 a/d conversion accuracy definitions rev. 2.0, 08/02, page 572 of 788 21.7 usage notes 21.7.1 permissible signal source impedance this lsis analog input (3-v version) is designed so that the conversion accuracy is guaranteed for an input signal for which the signal source impedance is 5 k w or less. this specification is provided to enable the a/d converters sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 5 k w , charging may be insufficient and it may not be possible to guarantee the a/d conversion accuracy. however, if a large capacitance is provided externally in single mode, the input load will essentially comprise only the internal input resistance of 10 k w , and the signal source impedance is ignored. however, since a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., voltage fluctuation ratio of 5 mv/s or greater) (see figure 21.7). when converting a high-speed analog signal or converting in scan mode, a low- impedance buffer should be inserted. for details on the 5-v version, refer to section 28, electrical characteristics. 21.7.2 influences on absolute accuracy adding capacitance results in coupling with ground, and therefore noise in ground may adversely affect the absolute accuracy. be sure to make the connection to an electrically stable ground such as avss. care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, so acting as antennas. a/d converter equivalent circuit this lsi 20 pf c in = 15 pf 10 k w to 5 k w low-pass filter c to 0.1 f sensor output impedance sensor input figure 21.7 example of analog input circuit rev. 2.0, 08/02, page 573 of 788 21.7.3 setting range of analog power supply and other pins if conditions shown below are not met, the reliability of this lsi may be adversely affected. analog input voltage range the voltage applied to analog input pin ann during a/d conversion should be in the range avss ann avref (n = 0 to 7). digital input voltage range the voltage applied to digital input pin cinn should be in the range avss cinn avref and vss cinn vcc (n = 0 to 15). relation between avcc, avss and vcc, vss for the relationship between avcc, avss and vcc, vss, set avss = vss. if the a/d converter is not used, the avcc and avss pins must on no account be left open. avref pin reference voltage specification range the reference voltage of the avref pin should be in the range avref avcc. 21.7.4 notes on board design in board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting a/d conversion values. also, digital circuitry must be isolated from the analog input signals (an0 to an7), analog reference voltage (av ref ), and analog power supply (av cc ) by the analog ground (av ss ). also, the analog ground (av ss ) should be connected at one point to a stable digital ground (v ss ) on the board. 21.7.5 notes on noise countermeasures a protection circuit connected to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (an0 to an7) and analog reference voltage (av ref ) should be connected between avcc and avss as shown in figure 21.8. also, the bypass capacitors connected to avcc and av ref , and the filter capacitor connected to an2 to an7, must be connected to av ss . if a filter capacitor is connected, the input currents at the analog input pins (an0 to an7) are averaged, and so an error may arise. also, when a/d conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the a/d converter exceeds the current input via the input impedance (r in ), an error will arise in the analog input pin voltage. careful consideration is therefore required when deciding the circuit constants. rev. 2.0, 08/02, page 574 of 788 av cc * 1 an0 to an7 av ss notes: values are reference values. * 1 * 2 r in : input impedance * 1 r in * 2 100 0.1 f 0.01 f 10 f avref figure 21.8 example of analog input protection circuit 20 pf to a/d converter an0 to an7 10 k note: * values are reference values. figure 21.9 equivalent circuit of analog input pin 21.7.6 module stop mode setting a/d converter operation can be enabled or disabled using the module stop control register. the initial setting is for a/d converter operation to be halted. register access is enabled by canceling module stop mode. for details, refer to section 26, power-down modes. rev. 2.0, 08/02, page 575 of 788 section 22 ram this lsi has an on-chip high-speed static ram. the ram is connected to the cpu by a 16-bit data bus, enabling one-state access by the cpu to both byte data and word data. the on-chip ram can be enabled or disabled by means of the rame bit in the system control register (syscr). for details on syscr, refer to section 3.2.2, system control register (syscr). product classification ram capacitance ram address h8s/2161b 4 kbytes h e080Ch efff, h ff00Ch ff7f h8s/2160b 4 kbytes h e080Ch efff, h ff00Ch ff7f h8s/2141b 4 kbytes h e080Ch efff, h ff00Ch ff7f h8s/2140b 4 kbytes h e080Ch efff, h ff00Ch ff7f h8s/2145b 8 kbytes h d080Ch efff, h ff00Ch ff7f flash memory version h8s/2148b 4 kbytes h e080Ch efff, h ff00Ch ff7f h8s/2161b 4 kbytes h e080Ch efff, h ff00Ch ff7f masked rom version h8s/2160b 4 kbytes h e080Ch efff, h ff00Ch ff7f rev. 2.0, 08/02, page 576 of 788 rev. 2.0, 08/02, page 577 of 788 section 23 rom this lsi has an on-chip rom (flash memory or masked rom). the features of the flash memory are summarized below. a block diagram of the flash memory is shown in figure 23.1. 23.1 features size product classification ram capacitance ram address h8s/2161b 128 kbytes h000000Ch01ffff (mode 2) h0000Chdfff (mode 3) h8s/2160b 64 kbytes h000000Ch00ffff (mode 2) h0000Chdfff (mode 3) h8s/2141b 128 kbytes h000000Ch01ffff (mode 2) h0000Chdfff (mode 3) h8s/2140b 64 kbytes h000000Ch00ffff (mode 2) h0000Chdfff (mode 3) h8s/2145b 256 kbytes h000000Ch03ffff (mode 2) h0000Chdfff (mode 3) h8s/2148b 128 kbytes h000000Ch01ffff (mode 2) h0000Chdfff (mode 3) programming/erase methods the flash memory is programmed 128 bytes at a time. erase is performed in single-block units. the flash memory is configured as follows: ? 64-kbyte version: 8 kbytes 2 blocks, 16 kbytes 1 block, 28 kbytes 1 block, and 1 kbyte 4 blocks ? 128-kbyte version: 32 kbytes 2 blocks, 8 kbytes 2 blocks, 16 kbytes 1 block, 28 kbytes 1 block, and 1 kbyte 4 blocks ? 256-kbyte version: 64 kbytes 3 blocks, 32 kbytes 1 block, and 4 kbytes 8 blocks. to erase the entire flash memory, each block must be erased in turn. programming/erase time it takes 10 ms (typ.) to program the flash memory 128 bytes at a time; 80 s (typ.) per 1 byte. erasing one block takes 100 ms (typ.). reprogramming capability the flash memory can be reprogrammed up to 100 times. two flash memory on-board programming modes romf254a_010020020700 rev. 2.0, 08/02, page 578 of 788 ? boot mode ? user program mode on-board programming/erasing can be done in boot mode in which the boot program built into the chip is started for erase or programming of the entire flash memory. in user program mode, individual blocks can be erased or programmed. automatic bit rate adjustment with data transfer in boot mode, this lsi's bit rate can be automatically adjusted to match the transfer bit rate of the host. programming/erasing protection sets protection against flash memory programming/erasing via hardware, software, or error protection. programmer mode in addition to on-board programming mode, programmer mode is supported to program or erase the flash memory using a prom programmer. bus interface/controller flash memory (64/128/256 kbytes) operating mode internal address bus internal data bus (16 bits) mode pin flmcr2 ebr1 ebr2 flmcr1 legend flmcr1 : flash memory control register 1 flmcr2 : flash memory control register 2 ebr1 : erase block register 1 ebr2 : erase block register 2 module bus figure 23.1 block diagram of flash memory rev. 2.0, 08/02, page 579 of 788 23.2 mode transitions when the mode pins are set in the reset state and a reset-start is executed, this lsi enters an operating mode as shown in figure 23.2. in user mode, flash memory can be read but not programmed or erased. the boot, user program, and programmer modes are provided as modes to write and erase the flash memory. the differences between boot mode and user program mode are shown in table 23.1. figure 23.3 shows the boot mode and figure 23.4 shows the user program mode. = 0 = 0 flshe = 1 swe = 1 flshe = 0 swe = 0 * 1 * 2 = 0 md1 = 1 = 0 boot mode on-board programming mode user program mode user mode (on-chip rom enabled) reset state programmer mode notes: only make a transition between user mode and user program mode when the cpu is not accessing the flash memory. 1. md1 = md0 = 0, p92 = p91 = p90 = 1 2. md1 = md0 = 0, p92 = 0, p91 = p90 = 1 figure 23.2 flash memory state transitions table 23.1 differences between boot mode and user program mode boot mode user program mode total erase yes yes block erase no yes programming control program * program/program-verify program/program-verify erase/erase-verify note: * should be provided by the user, in accordance with the recommended algorithm. rev. 2.0, 08/02, page 580 of 788 ! " rev. 2.0, 08/02, page 581 of 788 rev. 2.0, 08/02, page 582 of 788 23.3 block configuration 23.3.1 block configuration of 64-kbyte flash memory figure 23.5 shows the block configuration of 64-kbyte flash memory. the thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. the flash memory is divided into 8 kbytes (2 blocks), 16 kbytes (1 block), 28 kbytes (1 block), and 1 kbyte (4 blocks). erasing is performed in these divided units. programming is performed in 128-byte units starting from an address whose lower bits are h'00 or h'80. eb0 erase unit: 1 kbyte eb1 erase unit: 1 kbyte eb2 erase unit: 1 kbyte eb3 erase unit: 1 kbyte eb4 erase unit: 28 kbytes eb5 erase unit: 16 kbytes eb6 erase unit: 8 kbytes eb7 erase unit: 8 kbytes h'000000 h'000001 h'000002 h'00007f h'0003ff h'00047f h'00087f h'000c7f h'00107f h'007fff h'00807f h'00bfff h'0007ff h'000bff h'000fff h'00c07f h'00dfff h'00e07f h'00ffff programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes h'000400 h'000401 h'000402 h'000800 h'000801 h'000802 h'000c00 h'000c01 h'000c02 h'001000 h'001001 h'001002 h'008000 h'008001 h'008002 h'00c000 h'00c001 h'00c002 h'00e000 h'00e001 h'00e002 h'000380 h'000381 h'000382 h'000780 h'000781 h'000782 h'000b80 h'000b81 h'000b82 h'000f80 h'000f81 h'000f82 h'007f80 h'007f81 h'007f82 h'00bf80 h'00bf81 h'00bf82 h'00df80 h'00df81 h'00df82 h'00ff80 h'00ff81 h'00ff82 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C figure 23.5 64-kbyte flash memory block configuration rev. 2.0, 08/02, page 583 of 788 23.3.2 block configuration of 128-kbyte flash memory figure 23.6 shows the block configuration of 128-kbyte flash memory. the thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. the flash memory is divided into 32 kbytes (2 blocks), 8 kbytes (2 blocks), 16 kbytes (1 block), 28 kbytes (1 block), and 1 kbyte (4 blocks). erasing is performed in these divided units. programming is performed in 128-byte units starting from an address whose lower bits are h'00 or h'80. eb0 erase unit: 1 kbyte eb1 erase unit: 1 kbyte eb2 erase unit: 1 kbyte eb3 erase unit: 1 kbyte eb4 erase unit: 28 kbytes eb5 erase unit: 16 kbytes eb6 erase unit: 8 kbytes eb7 erase unit: 8 kbytes h'000000 h'000001 h'000002 h'00007f h'0003ff h'00407f h'00087f h'000c7f h'00107f h'007fff h'00807f h'00bfff h'0007ff h'000bff h'000fff h'00c07f h'00dfff h'00e07f h'00ffff programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes h'000400 h'000401 h'000402 h'000800 h'000801 h'000802 h'000c00 h'000c01 h'000c02 h'001000 h'001001 h'001002 h'008000 h'008001 h'008002 h'00c000 h'00c001 h'00c002 h'00e000 h'00e001 h'00e002 h'000380 h'000381 h'000382 h'000780 h'000781 h'000782 h'000b80 h'000b81 h'000b82 h'000f80 h'000f81 h'000f82 h'007f80 h'007f81 h'007f82 h'00bf80 h'00bf81 h'00bf82 h'00df80 h'00df81 h'00df82 h'00ff80 h'00ff81 h'00ff82 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C eb8 erase unit: 32 kbytes eb9 erase unit: 32 kbytes h'01007f h'017fff h'01807f h'01ffff programming unit: 128 bytes programming unit: 128 bytes h'010000 h'010001 h'010002 h'018000 h'018001 h'018002 h'017f80 h'017f81 h'017f82 h'01ff80 h'01ff81 h'01ff82 C C C C C C C C C C C C C C C C C C C C C C C C C C C C figure 23.6 128-kbyte flash memory block configuration rev. 2.0, 08/02, page 584 of 788 23.3.3 block configuration of 256-kbyte flash memory figure 23.7 shows the block configuration of 256-kbyte flash memory. the thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. the flash memory is divided into 64 kbytes (3 blocks), 32 kbytes (1 block), and 4 kbytes (8 blocks). erasing is performed in these divided units. programming is performed in 128-byte units starting from an address whose lower bits are h'00 or h'80. rev. 2.0, 08/02, page 585 of 788 eb0 erase unit: 4 kbytes eb1 erase unit: 4 kbytes eb2 erase unit: 4 kbytes eb3 erase unit: 4 kbytes eb4 erase unit: 32 kbytes eb5 erase unit: 4 kbytes eb6 erase unit: 4 kbytes eb7 erase unit: 4 kbytes h'000000 h'000001 h'000002 h'00007f h'000fff h'00107f h'00207f h'00307f h'00407f h'00bfff h'00c07f h'00cfff h'001fff h'002fff h'003fff h'00d07f h'00dfff h'00e07f h'00efff programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes h'001000 h'001001 h'001002 h'002000 h'002001 h'002002 h'003000 h'003001 h'003002 h'004000 h'004001 h'004002 h'00c000 h'00c001 h'00c002 h'00d000 h'00d001 h'00d002 h'00e000 h'00e001 h'00e002 h'000f80 h'000f81 h'000f82 h'001f80 h'001f81 h'001f82 h'002f80 h'002f81 h'002f82 h'003f80 h'003f81 h'003f82 h'00bf80 h'00bf81 h'00bf82 h'00cf80 h'00cf81 h'00cf82 h'00df80 h'00df81 h'00df82 h'00ef80 h'00ef81 h'00ef82 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C eb8 erase unit: 4 kbytes eb9 erase unit: 64 kbytes h'00f07f h'00ffff h'01007f h'01ffff programming unit: 128 bytes programming unit: 128 bytes h'00f000 h'00f001 h'00f002 h'010000 h'010001 h'010002 h'00ff80 h'00ff81 h'00ff82 h'01ff80 h'01ff81 h'01ff82 C C C C C C C C C C C C C C C C C C C C C C C C C C C C eb10 erase unit: 64 kbytes eb11 erase unit: 64 kbytes h'02007f h'02ffff h'03007f h'03ffff programming unit: 128 bytes programming unit: 128 bytes h'020000 h'020001 h'020002 h'030000 h'030001 h'030002 h'02ff80 h'02ff81 h'02ff82 h'03ff80 h'03ff81 h'03ff82 C C C C C C C C C C C C C C C C C C C C C C C C C C C C figure 23.7 256-kbyte flash memory block configuration 23.4 input/output pins the flash memory is controlled by means of the pins shown in table 23.2. rev. 2.0, 08/02, page 586 of 788 table 23.2 pin configuration pin name i/o function 5(6 input reset md1 input sets this lsis operating mode md0 input sets this lsis operating mode p92 input sets this lsis operating mode p91 input sets this lsis operating mode p90 input sets this lsis operating mode txd1 output serial transmit data output rxd1 input serial receive data input 23.5 register descriptions the flash memory has the following registers. to access flmcr1, flmcr2, ebr1, or ebr2, the flshe bit in the serial/timer control register (stcr) should be set to 1. for details on the serial/timer control register, refer to section 3.2.3, serial/timer control register (stcr). flash memory control register 1 (flmcr1) flash memory control register 2 (flmcr2) erase block register 1 (ebr1) erase block register 2 (ebr2) rev. 2.0, 08/02, page 587 of 788 23.5.1 flash memory control register 1 (flmcr1) flmcr1, used together with flmcr2, makes the flash memory transit to program mode, program-verify mode, erase mode, or erase-verify mode. for details on register setting, refer to section 23.8, flash memory programming/erasing. flmcr1 is initialized to h'80 by a reset, or in hardware standby mode, software standby mode, sub-active mode, sub-sleep mode, or watch mode. bit bit name initial value r/w description 7 fwe 1 r flash write enable controls programming/erasing of on-chip flash memory. this bit is always read as 0, and cannot be modified. 6 swe 0 r/w software write enable when this bit is set to 1, flash memory programming/erasing is enabled. when this bit is cleared to 0, the ev, pv, e, and p bits in this register, the esu and psu bits in flmcr2, and all ebr1 and ebr2 bits cannot be set to 1. do not clear these bits and swe to 0 simultaneously. 5 4 0 0 r r reserved these bits are always read as 0 and cannot be modified. 3 ev 0 r/w erase-verify when this bit is set to 1 while swe = 1, the flash memory transits to erase-verify mode. when it is cleared to 0, erase-verify mode is cancelled. 2 pv 0 r/w program-verify when this bit is set to 1 while swe = 1, the flash memory transits to program-verify mode. when it is cleared to 0, program-verify mode is cancelled. 1 e 0 r/w erase when this bit is set to 1 while swe = 1 and esu = 1, the flash memory transits to erase mode. when it is cleared to 0, erase mode is cancelled. 0 p 0 r/w program when this bit is set to 1 while swe = 1 and psu = 1, the flash memory transits to program mode. when it is cleared to 0, program mode is cancelled. rev. 2.0, 08/02, page 588 of 788 23.5.2 flash memory control register 2 (flmcr2) flmcr2 monitors the state of flash memory programming/erasing protection (error protection) and sets up the flash memory to transit to programming/erasing mode. flmcr2 is initialized to h00 by a reset or in hardware standby mode. the esu and psu bits are cleared to 0 in software standby mode, sub-active mode, sub-sleep mode, or watch mode, or when the swe bit in flmcr1 is cleared to 0. bit bit name initial value r/w description 7 fler 0 r flash memory error indicates that an error has occurred during flash memory programming/erasing. when this bit is set to 1, flash memory goes to the error-protection state. for details, see section 23.9.3, error protection. 6 to 2 all 0 r/(w) reserved the initial values should not be modified. 1 esu 0 r/w erase setup when this bit is set to 1 while swe = 1, the flash memory transits to the erase setup state. when it is cleared to 0, the erase setup state is cancelled. set this bit to 1 before setting the e bit in flmcr1 to 1. 0 psu 0 r/w program setup when this bit is set to 1 while swe = 1, the flash memory transits to the program setup state. when it is cleared to 0, the program setup state is cancelled. set this bit to 1 before setting the p bit in flmcr1 to 1. 23.5.3 erase block registers 1 and 2 (ebr1, ebr2) ebr1 and ebr2 are used to specify the flash memory erase block. ebr1 and ebr2 are initialized to h00 by a reset, or in hardware standby mode, software standby mode, sub-active mode, sub-sleep mode, or watch mode, or when the swe bit in flmcr1 is cleared to 0. set only one bit to 1 at a time, otherwise all bits in ebr1 and ebr2 are automatically cleared to 0. ebr1 (64-kbyte version) bit bit name initial value r/w description 7 to 0 all 0 r/(w) reserved the initial values should not be modified. rev. 2.0, 08/02, page 589 of 788 ebr2 (64-kbyte version) bit bit name initial value r/w description 7 eb7 0 r/w * when this bit is set to 1, 8 kbytes of eb7 (h'00e000 to h00ffff) are to be erased. 6 eb6 0 r/w when this bit is set to 1, 8 kbytes of eb6 (h'00c000 to h00dfff) are to be erased. 5 eb5 0 r/w when this bit is set to 1, 16 kbytes of eb5 (h'008000 to h'00bfff) are to be erased. 4 eb4 0 r/w when this bit is set to 1, 28 kbytes of eb4 (h'001000 to h'007fff) are to be erased. 3 eb3 0 r/w when this bit is set to 1, 1 kbyte of eb3 (h'000c00 to h'000fff) is to be erased. 2 eb2 0 r/w when this bit is set to 1, 1 kbyte of eb2 (h'000800 to h'000bff) is to be erased. 1 eb1 0 r/w when this bit is set to 1, 1 kbyte of eb1 (h'000400 to h'0007ff) is to be erased. 0 eb0 0 r/w when this bit is set to 1, 1 kbyte of eb0 (h'000000 to h'0003ff) is to be erased. note: * in normal mode, this bit is always read as 0 and cannot be modified. ebr1 (128-kbyte version) bit bit name initial value r/w description 7 to 2 all 0 r/(w) reserved the initial values should not be modified. 1 eb9 0 r/w * when this bit is set to 1, 32 kbytes of eb9 (h'018000 to h'01ffff) are to be erased. 0 eb8 0 r/w * when this bit is set to 1, 32 kbytes of eb8 (h'010000 to h'017fff) are to be erased. rev. 2.0, 08/02, page 590 of 788 ebr2 (128-kbyte version) bit bit name initial value r/w description 7 eb7 0 r/w * when this bit is set to 1, 8 kbytes of eb7 (h'00e000 to h00ffff) are to be erased. 6 eb6 0 r/w when this bit is set to 1, 8 kbytes of eb6 (h'00c000 to h00dfff) are to be erased. 5 eb5 0 r/w when this bit is set to 1, 16 kbytes of eb5 (h'008000 to h'00bfff) are to be erased. 4 eb4 0 r/w when this bit is set to 1, 28 kbytes of eb4 (h'001000 to h'007fff) are to be erased. 3 eb3 0 r/w when this bit is set to 1, 1 kbyte of eb3 (h'000c00 to h'000fff) is to be erased. 2 eb2 0 r/w when this bit is set to 1, 1 kbyte of eb2 (h'000800 to h'000bff) is to be erased. 1 eb1 0 r/w when this bit is set to 1, 1 kbyte of eb1 (h'000400 to h'0007ff) is to be erased. 0 eb0 0 r/w when this bit is set to 1, 1 kbyte of eb0 (h'000000 to h'0003ff) is to be erased. note: * in normal mode, this bit is always read as 0 and cannot be modified. ebr1 (256-kbyte version) bit bit name initial value r/w description 7 to 4 all 0 r/(w) reserved the initial values should not be modified. 3 eb11 0 r/w * when this bit is set to 1, 64 kbytes of eb11 (h'030000 to h'03ffff) are to be erased. 2 eb10 0 r/w * when this bit is set to 1, 64 kbytes of eb10 (h'020000 to h'02ffff) are to be erased. 1 eb9 0 r/w * when this bit is set to 1, 64 kbytes of eb9 (h'010000 to h'01ffff) are to be erased. 0 eb8 0 r/w * when this bit is set to 1, 4 kbytes of eb8 (h'00f000 to h'00ffff) are to be erased. rev. 2.0, 08/02, page 591 of 788 ebr2 (256-kbyte version) bit bit name initial value r/w description 7 eb7 0 r/w * when this bit is set to 1, 4 kbytes of eb7 (h'00e000 to h00efff) are to be erased. 6 eb6 0 r/w when this bit is set to 1, 4 kbytes of eb6 (h'00d000 to h00dfff) are to be erased. 5 eb5 0 r/w when this bit is set to 1, 4 kbytes of eb5 (h'00c000 to h'00cfff) are to be erased. 4 eb4 0 r/w when this bit is set to 1, 32 kbytes of eb4 (h'004000 to h'00bfff) are to be erased. 3 eb3 0 r/w when this bit is set to 1, 4 kbytes of eb3 (h'003000 to h'003fff) is to be erased. 2 eb2 0 r/w when this bit is set to 1, 4 kbytes of eb2 (h'002000 to h'002fff) is to be erased. 1 eb1 0 r/w when this bit is set to 1, 4 kbytes of eb1 (h'001000 to h'001fff) is to be erased. 0 eb0 0 r/w when this bit is set to 1, 4 kbytes of eb0 (h'000000 to h'000fff) is to be erased. note: * in normal mode, this bit is always read as 0 and cannot be modified. rev. 2.0, 08/02, page 592 of 788 23.6 operating modes the flash memory is connected to the cpu via a 16-bit data bus, enabling byte data and word data to be accessed in a single state. even addresses are connected to the upper 8 bits and odd addresses are connected to the lower 8 bits. note that word data must start from an even address. on-chip rom is enabled or disabled by the mode select pins (md1 and md0) and the expe bit in mdcr, as summarized in table 23.3. in normal mode (mode 3), up to 56 kbytes of rom can be used. table 23.3 operating modes and rom operating modes mode pins mdcr mcu operating mode cpu operating mode mode md1 md0 expe on-chip rom mode 1 normal expanded mode with on-chip rom disabled 0 1 1 disabled advanced single-chip mode 1 0 0 mode 2 advanced expanded mode with on-chip rom enabled 101 enabled (64/128/256 kbytes) normal single-chip mode 1 1 0 mode 3 normal expanded mode with on-chip rom enabled 111 enabled (56 kbytes) 23.7 on-board programming modes an on-board programming mode is used to perform on-chip flash memory programming, erasing, and verification. this lsi has two on-board programming modes: boot mode and user program mode. table 23.4 shows pin settings for boot mode. in user program mode, operation by software is enabled by setting control bits. for details on flash memory mode transitions, see figure 23.2. table 23.4 on-board programming mode settings mode setting md1 md0 p92 p91 p90 boot mode 0 0 1 * 1 * 1 * mode 2 (advanced mode) 1 0 ??? user program mode mode 3 (normal mode) 1 1 ??? note: * can be used as an i/o port after the boot mode activation. rev. 2.0, 08/02, page 593 of 788 23.7.1 boot mode table 23.5 shows the boot mode operations between reset end and branching to the programming control program. 1. when boot mode is used, the flash memory programming control program must be prepared in the host beforehand. prepare a programming control program in accordance with the description in section 23.8, flash memory programming/erasing. in boot mode, if any data exists in the flash memory (except in the case that all data are 1), all blocks in the flash memory are erased. use boot mode at initial writing in the on-board state, or forced recovery when user program mode cannot be executed because the program to be initiated in user program mode was mistakenly erased. 2. the sci_1 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop bit, and no parity. 3. when the boot program is initiated, this lsi measures the low-level period of asynchronous sci communication data (h'00) transmitted continuously from the host. this lsi then calculates the bit rate of transmission from the host, and adjusts the sci_1 bit rate to match that of the host. the reset should end with the rxd1 pin high. the rxd1 and txd1 pins should be pulled up on the board if necessary. after the reset ends, it takes approximately 100 states before this lsi is ready to measure the low-level period. 4. after matching the bit rates, this lsi transmits one h'00 byte to the host to indicate the end of bit rate adjustment. the host should confirm that this adjustment end indication (h'00) has been received normally, and transmit one h'55 byte to this lsi. if reception could not be performed normally, initiate boot mode again by a reset. depending on the hosts transfer bit rate and system clock frequency of this lsi, there will be a discrepancy between the bit rates of the host and this lsi. to operate the sci properly, set the hosts transfer bit rate and system clock frequency of this lsi within the ranges listed in table 23.6. 5. in boot mode, a part of the on-chip ram area is used by the boot program. addresses h'ffe080 to h'ffe87f* 1 is the area to which the programming control program is transferred from the host. note, however, that id codes are assigned to addresses h'ffe080 to h'ffe087* 2 . the boot program area cannot be used until the execution state in boot mode switches to the programming control program. figure 23.8 shows the on-chip ram area in boot mode. 6. before branching to the programming control program (h'ffe088* 3 in the ram area), this lsi terminates transfer operations by the sci_1 (by clearing the re and te bits in scr to 0), but the adjusted bit rate value remains set in brr. therefore, the programming control program can still use it for transfer of write data or verify data with the host. the txd1 pin is in high-level output state. the contents of the cpu general registers are undefined immediately after branching to the programming control program. these registers must be initialized at the beginning of the programming control program, since the stack pointer (sp), in particular, is used implicitly in subroutine calls, etc. rev. 2.0, 08/02, page 594 of 788 7. boot mode can be cleared by a reset. cancel the reset* 4 after driving the reset pin low, waiting at least 20 states, and then setting the mode pins. boot mode is also cleared when a wdt overflow occurs. 8. do not change the mode pin input levels in boot mode. if mode pin input levels are changed from low to high during reset, operating modes are switched and the state of ports that are also used for address output and bus control output signals ( $6 , 5' , and +:5 ) are changed* 5 . therefore, set these pins carefully not to be output signals during reset or not to conflict with lsi external signals. 9. all interrupts are disabled during programming or erasing of the flash memory. notes: 1. address area for the h8s/2140b, h8s/2141b, h8s/2148b, h8s/2160b, and h8s/2161b. on the h8s/2145b, the address area is from hffd080 to hffd87f. 2. address area for the h8s/2140b, h8s/2141b, h8s/2148b, h8s/2160b, and h8s/2161b. on the h8s/2145b, the address area is from hffd080 to hffd087. 3. ram address for the h8s/2140b, h8s/2141b, h8s/2148b, h8s/2160b, and h8s/2161b. on the h8s/2145b, the address is hffd088. 4. after reset is cancelled, mode pin input settings must satisfy the mode programming setup time (t mds = 4 states). 5. the ports that also have address output functions output low as address output when the mode pins are set to mode 1 during a reset. in modes other than mode 1, it enters the high impedance state. bus control output signals output high when the mode pins are set to mode 1 during a reset. in modes other than mode 1, it enters the high impedance state. rev. 2.0, 08/02, page 595 of 788 table 23.5 boot mode operation communications contents processing contents host operation lsi operation processing contents continuously transmits data h'00 at specified bit rate. branches to boot program at reset-start. boot program start branches to programming control program transferred to on-chip ram and starts execution. h'00, h'00 . . . h'00 h'00 h'55 transmits data h'55 when data h'00 is received error-free. boot program erase error h'ff h'aa receives data h'aa. receives data h'aa. h'aa echobacks the 2-byte data received to host. echobacks received data to host and also transfers it to ram (repeated for n times). high-order byte and low-order byte echoback echoback h'xx transmits number of bytes (n) of programming control program to be transferred as 2-byte data (low-order byte following high-order byte). transmits 1-byte of programming control program (repeated for n times). item boot mode start ? measures low-level period of receive data h'00. ? calculates bit rate and sets it in brr of sci_1. ? transmits data h'00 to host as adjustment end indication. bit rate adjustment checks flash memory data, erases all flash memory blocks in case of written data existing, and transmits data h'aa to host. (if erase could not be done, transmits data h'ff to host and aborts operation.) flash memory erase transfer of programming control program after receiving data h'55, transmits data h'aa to host. rev. 2.0, 08/02, page 596 of 788 table 23.6 system clock frequencies for which automatic adjustment of lsi bit rate is possible host bit rate system clock frequency range of lsi (3-v version) system clock frequency range of lsi (5-v version) 19200 bps 8 to 10 mhz 8 to 20 mhz 9600 bps 4 to 10 mhz 4 to 20 mhz 4800 bps 2 to 10 mhz 2 to 18 mhz boot program area * (128 bytes) h'ffff7f h'ffff00 h'ffefff h'ffe880 h'ffe088 h'ffe080 id code area programming control program area (2040 bytes) boot program area * (1920 bytes) h8s/2140b, h8s/2141b, h8s/2148b, h8s/2160b, and h8s/2161b h8s/2145b boot program area * (128 bytes) h'ffff7f h'ffff00 h'ffefff h'ffe880 h'ffd088 h'ffd080 id code area programming control program area (6136 bytes) boot program area * (1920 bytes) note: the boot program area and area which is not used cannot be used until a transition is made to the execution state for the programming control program transferred to ram. note that the contents of the boot program area in ram are remained after a branch is made to the programming control program. figure 23.8 on-chip ram area in boot mode in boot mode, this lsi checks the contents of the 8-byte id code area as shown below to confirm that the programming control program corresponds with this lsi. to originally write a programming control program to be used in boot mode, the above 8-byte id code must be added at the beginning of the program. h'ffe080 h'ffe088 39 40 fe 64 66 32 31 34 ? instruction codes of the programming control program (product id) h8s/2140b, h8s/2141b, h8s/2148b, h8s/2160b, or h8s/2161b h'ffd080 h'ffd088 35 40 fe 64 66 32 31 34 ? instruction codes of the programming control program (product id) h8s/2145b figure 23.9 id code area rev. 2.0, 08/02, page 597 of 788 23.7.2 user program mode on-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. the user must set branching conditions and provide on-board means of supplying programming data. the flash memory must contain the user program/erase control program or a program which provides the user program/erase control program from external memory. because the flash memory itself cannot be read during programming/erasing, transfer the user program/erase control program to on-chip ram, as like in boot mode. figure 23.10 shows a sample procedure for programming/erasing in user program mode. prepare a user program/erase control program in accordance with the description in section 23.8, flash memory programming/erasing. ye s no program/erase? reset-start branch to flash memory application program transfer user program/ erase control program to ram branch to flash memory application program branch to user program/ erase control program in ram execute user program/erase control program (flash memory rewrite) figure 23.10 programming/erasing flowchart example in user program mode rev. 2.0, 08/02, page 598 of 788 23.8 flash memory programming/erasing a software method, using the cpu, is employed to program and erase flash memory in the on- board programming modes. depending on the flmcr1 and flmcr2 settings, the flash memory operates in one of the following four modes: program mode, program-verify mode, erase mode, and erase-verify mode. the programming control program in boot mode and the user program/erase control program in user program mode use these operating modes in combination to perform programming/erasing. flash memory programming and erasing should be performed in accordance with the descriptions in section 23.8.1, program/program-verify and section 23.8.2, erase/erase-verify, respectively. 23.8.1 program/program-verify when writing data or programs to the flash memory, the program/program-verify flowchart shown in figure 23.11 should be followed. performing programming operations according to this flowchart will enable data or programs to be written to the flash memory without subjecting this lsi to voltage stress or sacrificing program data reliability. 1. programming must be done to an empty address. do not reprogram an address to which programming has already been performed. 2. programming should be carried out 128 bytes at a time. a 128-byte data transfer must be performed even if writing fewer than 128 bytes. in this case, h'ff data must be written to the extra addresses. 3. prepare the following data storage areas in ram: a 128-byte programming data area, a 128- byte reprogramming data area, and a 128-byte additional-programming data area. perform reprogramming data computation and additional programming data computation according to figure 23.11. 4. consecutively transfer 128 bytes of data in byte units from the reprogramming data area or additional-programming data area to the flash memory. the program address and 128-byte data are latched in the flash memory. the lower 8 bits of the start address in the flash memory destination area must be h'00 or h'80. 5. the time during which the p bit is set to 1 is the programming time. figure 23.11 shows the allowable programming times. 6. the watchdog timer (wdt) is set to prevent overprogramming due to program runaway, etc. the overflow cycle should be longer than (y + z2 + a + b ) m s. 7. for a dummy write to a verify address, write 1-byte data h'ff to an address whose lower 2 bits are b'00. verify data can be read in words from the address to which a dummy write was performed. 8. the maximum number of repetitions of the program/program-verify sequence to the same bit is (n). rev. 2.0, 08/02, page 599 of 788 start end of programming set swe bit in flmcr1 start of programming write pulse application subroutine wait (x) m s sub-routine write pulse end sub set psu bit in flmcr2 wdt enable disable wdt number of writes n 1 2 3 4 5 6 7 8 9 10 11 12 13 998 999 1000 note 7: write pulse width write time (z) m s z1 z1 z1 z1 z1 z1 z2 z2 z2 z2 z2 z2 z2 z2 z2 z2 wait ( ) m s set p bit in flmcr1 wait (z1) m s, (z2) m s or (z3) m s clear p bit in flmcr1 wait ( ) m s clear psu bit in flmcr2 wait ( ) m s n = 1 m = 0 ng ng ng ng ng ok ok ok wait ( ) m s wait ( ) m s * 2 * 4 * 5 * 1 wait ( ) m s apply write pulse z1 m s or z2 m s sub-routine-call set pv bit in flmcr1 h'ff dummy write to verify address read verify data write data = verify data? * 4 * 3 * 3 * 1 transfer reprogram data to reprogram data area reprogram data computation * 4 transfer additional-programming data to additional-programming data area additional-programming data computation clear pv bit in flmcr1 clear swe bit in flmcr1 m = 1 see note 7 for pulse width m = 0 ? increment address programming failure ok clear swe bit in flmcr1 wait ( ) m s m s ok 6 3 n? ng ok 6 3 n ? wait ( ) m s n 3 (n)? n ? n + 1 original data (d) verify data (v) reprogram data (x) comments programming completed still in erased state; no action programming incomplete; reprogram note: use a z3 m s write pulse for additional programming. write 128-byte data in ram reprogram data area consecutively to flash memory ram program data storage area (128 bytes) reprogram data storage area (128 bytes) additional-programming data storage area (128 bytes) store 128-byte program data in program data area and reprogram data area apply write pulse (additional programming) 128-byte data verification completed? successively write 128-byte data from additional- programming data area in ram to flash memory reprogram data computation table reprogram data (x') verify data (v) additional- programming data (y) 1 1 1 1 0 1 0 0 0 0 1 1 comments additional programming to be executed additional programming not to be executed additional programming not to be executed 0 1 1 1 0 1 0 1 0 0 1 1 additional-programming data computation table perform programming in the erased state. do not perform additional programming on previously programmed addresses. notes: 1. data transfer is performed by byte transfer. the lower 8 bits of the first address written to must be h'00 or h'80. a 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, h'ff data must be written to the extra addresses. 2. verify data is read in 16-bit (word) units. 3. even bits for which programming has been completed will be subjected to programming once again if the result of the subseque nt verify operation is ng. 4. a 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additi onal data must be provided in ram. the contents of the reprogram data area and additional data area are modified as programming proceeds. 5. a write pulse of z1 m s or z2 m s is applied according to the progress of the programming operation. see note7 for details of the pulse widths. when writing of additional-programming data is executed, a z3 m s write pulse should be applied. reprogram data x' means reprogram data when the write pulse is applied. 6. the values of x, y, z1, z2, z3, , , , , , , and n are shown in section 28, flash memory characteristics. figure 23.11 program/program-verify flowchart rev. 2.0, 08/02, page 600 of 788 23.8.2 erase/erase-verify when erasing flash memory, the erase/erase-verify flowchart shown in figure 23.12 should be followed. 1. prewriting (setting erase block data to all 0) is not necessary. 2. erasing is performed in block units. make only a single-block specification in erase block registers 1 and 2 (ebr1 and ebr2). to erase multiple blocks, each block must be erased in turn. 3. the time during which the e bit is set to 1 is the flash memory erase time. 4. the watchdog timer (wdt) is set to prevent overprogramming due to program runaway, etc. an overflow cycle of approximately (y + z + a + b) ms is allowed. 5. for a dummy write to a verify address, write 1-byte data h'ff to an address whose lower two bits are b'00. verify data can be read in longwords from the address to which a dummy write was performed. 6. if the read data is unerased, set erase mode again, and repeat the erase/erase-verify sequence as before. the maximum number of repetitions of the erase/erase-verify sequence is n. rev. 2.0, 08/02, page 601 of 788 end of erasing start set swe bit in flmcr1 set esu bit in flmcr2 set e bit in flmcr1 wait ( x ) m s wait ( y ) m s n = 1 set ebr1 and ebr2 enable wdt * 4 * 2 * 2 * 2 * 2 * 2 * 2 * 2 * 2 * 2 * 2 wait ( z ) ms wait ( a ) m s wait ( b ) m s wait ( g ) m s set block start address as verify address wait ( e ) m s wait ( h ) m s * 5 * 3 start of erasing clear e bit in flmcr1 clear esu bit in flmcr2 set ev bit in flmcr1 h'ff dummy write to verify address read verify data clear ev bit in flmcr1 wait ( h ) m s clear ev bit in flmcr1 clear swe bit in flmcr1 disable wdt end of erasing * 1 verify data = all "1"? last address of block? all erase blocks erased? erase failure clear swe bit in flmcr1 n 3 ( n ) ? ng ng ng ng ok ok ok ok increment address n ? n + 1 wait ( q ) m s wait ( q ) m s notes: 1. prewriting (writing 0 to all data in erased block) is not necessary. 2. the values of x, y, z, a , b , g, e , h , q , and n are shown in section 28, flash memory characteristics. 3. verify data is read in 16-bit (word) units. 4. set only a single bit in ebr1 and ebr2. do not set more than one bit. 5. erasing is performed in block units. to erase multiple blocks, each block must be erased in turn. figure 23.12 erase/erase-verify flowchart rev. 2.0, 08/02, page 602 of 788 23.9 program/erase protection there are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 23.9.1 hardware protection hardware protection is a state in which programming/erasing of flash memory is forcibly disabled or aborted by a reset (including wdt overflow reset), or a transition to hardware standby mode, software standby mode, sub-active mode, sub-sleep mode or watch mode. flash memory control registers 1 and 2 (flmcr1 and flmcr2) and erase block registers 1 and 2 (ebr1 and ebr2) are initialized. in a reset via the 5(6 pin, the reset state is not entered unless the 5(6 pin is held low until oscillation stabilizes after powering on. in the case of a reset during operation, hold the 5(6 pin low for the 5(6 pulse width specified in the ac characteristics section. 23.9.2 software protection software protection can be implemented against programming/erasing of all flash memory blocks by clearing the swe bit in flmcr1 to 0. when software protection is in effect, setting the p or e bit in flmcr1 does not cause a transition to program mode or erase mode. by setting the erase block registers 1 and 2 (ebr1 and ebr2), erase protection can be set for individual blocks. when ebr1 and ebr2 are set to h'00, erase protection is set for all blocks. 23.9.3 error protection in error protection, an error is detected when the cpus runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. when the following errors are detected during programming/erasing of flash memory, the fler bit in flmcr2 is set to 1, and the error protection state is entered. when the flash memory of is read during programming/erasing (including vector read and instruction fetch) immediately after exception handling (excluding a reset) during programming/erasing when a sleep instruction is executed (transits to software standby mode, sleep mode, sub- active mode, sub-sleep mode, or watch mode) during programming/erasing when the bus ownership is released during programming/erasing the flmcr1, flmcr2, ebr1, and ebr2 settings are retained, but program mode or erase mode is aborted at the point at which the error occurred. program mode or erase mode cannot be entered by setting the p or e bit to 1. however, because the pv and ev bit settings are retained, a rev. 2.0, 08/02, page 603 of 788 transition to verify mode can be made. the error protection state can be cancelled by a reset or in hardware standby mode. 23.10 interrupts during flash memory programming/erasing in order to give the highest priority to programming/erasing operations, disable all interrupts including nmi input during flash memory programming/erasing (the p or e bit in flmcr1 is set to 1) or boot program execution* 1 . 1. if an interrupt is generated during programming/erasing, operation in accordance with the program/erase algorithm is not guaranteed. 2. cpu runaway may occur because normal vector reading cannot be performed in interrupt exception handling during programming/erasing* 2 . 3. if an interrupt occurs during boot program execution, the normal boot mode sequence cannot be executed. notes: 1. interrupt requests must be disabled inside and outside the cpu until the programming control program has completed programming. 2. the vector may not be read correctly for the following two reasons: if flash memory is read while being programmed or erased (while the p or e bit in flmcr1 is set to 1), correct read data will not be obtained (undefined values will be returned). if the interrupt entry in the vector table has not been programmed yet, interrupt exception handling will not be executed correctly. rev. 2.0, 08/02, page 604 of 788 23.11 programmer mode in programmer mode, the on-chip flash memory can be programmed/erased by a prom programmer via a socket adapter, just like for a discrete flash memory. use a prom programmer that supports the hitachi 64/128/256-kbyte flash memory on-chip mcu device*. figure 23.13 shows a memory map in programmer mode. note: for 3-v and 5-v version products, set the programming voltage of the prom programmer to 3.3v. h8s/2141b, h8s/2148b, and h8s/2161b on-chip rom area mcu mode h'000000 programmer mode h'00000 h'01ffff h'1ffff h8s/2140b and h8s/2160b on-chip rom area mcu mode h'000000 programmer mode h'00000 h'00ffff h'0ffff h8s/2145b on-chip rom area mcu mode h'000000 programmer mode h'00000 h'03ffff h'3ffff undefined value output h'1ffff figure 23.13 memory map in programmer mode 23.12 usage notes the following lists notes on the use of on-board programming modes and programmer mode. 1. perform programming/erasing with the specified voltage and timing. if a voltage higher than the rated voltage is applied, the product may be fatally damaged. for 3-v and 5-v version products, use a prom programmer that supports the hitachi 64/128/256- kbyte flash memory on-chip mcu device at 3.3 v. do not set the programmer to hn28f101 or the programming voltage to 5.0 v. 2. notes on power on/off at powering on or off the vcc power supply, fix the 5(6 pin to low and set the flash memory to hardware protection state. this power on/off timing must also be satisfied at a power-off and power-on caused by a power failure and other factors. 3. perform flash memory programming/erasing in accordance with the recommended algorithm rev. 2.0, 08/02, page 605 of 788 in the recommended algorithm, flash memory programming/erasing can be performed without subjecting this lsi to voltage stress or sacrificing program data reliability. when setting the p or e bit in flmcr1 to 1, set the watchdog timer against program runaway. 4. do not set/clear the swe bit during program execution in the flash memory. do not set/clear the swe bit during program execution in the flash memory. an interval of at least 100 m s is necessary between program execution or data reading in flash memory and swe bit clearing. when the swe bit is set to 1, flash memory data can be modified, however, flash memory data can be read only in program-verify or erase-verify mode. do not access the flash memory for a purpose other than verification during programming/erasing. do not clear the swe bit during programming, erasing, or verifying. 5. do not use interrupts during flash memory programming/erasing in order to give the highest priority to programming/erasing operation, disable all interrupts including nmi input when the flash memory is programmed or erased. 6. do not perform additional programming. programming must be performed in the erased state. program the area with 128-byte programming-unit blocks in on-board programming or programmer mode only once. perform programming in the state where the programming-unit block is fully erased. 7. ensure that the prom programmer is correctly attached before programming. if the socket, socket adapter, or product index does not match the specifications, too much current flows and the product may be damaged. 8. do not touch the socket adapter or lsi while programming. touching either of these can cause contact faults and write errors. rev. 2.0, 08/02, page 606 of 788 rev. 2.0, 08/02, page 607 of 788 section 24 masked rom this series incorporates a 64-kbyte or 128-kbyte masked rom. the on-chip rom is connected to the cpu and data transfer controller (dtc) via the 16-bit data bus. the cpu and dtc can access the on-chip rom with 8- or 16-bit width. data in the on-chip rom can always be accessed in one state. h'000000 h'000002 h'01fffe h'000001 h'000003 h'01ffff internal data bus (upper 8 bits) mode 2 mode 3 internal data bus (lower 8 bits) h'0000 h'0002 h'dffe h'0001 h'0003 h'dfff internal data bus (upper 8 bits) internal data bus (lower 8 bits) figure 24.1 block diagram of 128-kbyte masked rom (hd6432161bv) h'000000 h'000002 h'00fffe h'000001 h'000003 h'00ffff internal data bus (upper 8 bits) internal data bus (lower 8 bits) h'0000 h'0002 h'dffe h'0001 h'0003 h'dfff internal data bus (upper 8 bits) internal data bus (lower 8 bits) mode 2 mode 3 figure 24.2 block diagram of 64-kbyte masked rom (hd6432160bv) the on-chip rom is enabled or disabled according to the operating mode. the operating mode is selected by the mode select pins md1 and md0 as indicated in table 3.1. select mode 2 or 3 to enable the on-chip rom; whereas mode 1 to disable the on-chip rom. the on-chip rom is allocated in area 0. rev. 2.0, 08/02, page 608 of 788 rev. 2.0, 08/02, page 609 of 788 section 25 clock pulse generator this lsi incorporates a clock pulse generator, which generates the system clock (?), bus master clock, and internal clock. the clock pulse generator consists of an oscillator, duty correction circuit, clock select circuit, medium-speed clock divider, bus master clock select circuit, subclock input circuit, and waveform forming circuit. figure 25.1 shows a block diagram of the clock pulse generator. oscillator duty correction circuit clock select circuit medium- speed clock divider bus master clock select circuit subclock input circuit waveform forming circuit extal xtal excl ?/2 to f/32 ?sub ? wdt_1 count clock system clock to ? pin internal clock to peripheral modules bus master clock to cpu and dtc figure 25.1 block diagram of clock pulse generator the bus master clock is selected as either high-speed mode or medium-speed mode by software according to the settings of the sck2 to sck0 bits in the standby control register. for details on the standby control register, refer to section 26.1.1, standby control register (sbycr). the subclock input is controlled by software according to the excle bit setting in the low power control register. for details on the low power control register, refer to section 26.1.2, low power control register (lpwrcr). rev. 2.0, 08/02, page 610 of 788 25.1 oscillator clock pulses can be supplied either by connecting a crystal resonator, or by providing external clock input. 25.1.1 connecting crystal resonator figure 25.2 shows a typical method of connecting a crystal resonator. an appropriate damping resistance r d , given in table 25.1, should be used. an at-cut parallel-resonance crystal resonator should be used. figure 25.3 shows the equivalent circuit of a crystal resonator. a resonator having the characteristics given in table 25.2 should be used. a crystal resonator with frequency identical to that of the system clock (?) should be used. extal xtal r d c l2 c l1 c l1 = c l2 = 10 to 22 pf figure 25.2 typical connection to crystal resonator table 25.1 damping resistance values frequency (mhz) 2 4 8 10 12 16 20 r d ( w ) 1 k 500 200 0 0 0 0 xtal c l at-cut parallel-resonance crystal resonator extal c 0 lr s figure 25.3 equivalent circuit of crystal resonator rev. 2.0, 08/02, page 611 of 788 table 25.2 crystal resonator parameters frequency (mhz) 2 4 8 10 12 16 20 r s (max) ( w ) 500 120 80 70 60 50 40 c 0 (max) (pf) 7 25.1.2 external clock input method figure 25.4 shows a typical method of connecting an external clock signal. to leave the xtal pin open, incidental capacitance should be 10 pf or less. to input an inverted clock to the xtal pin, the external clock should be set to high in standby mode, subactive mode, subsleep mode, and watch mode. external clock input conditions are shown in table 25.3. the frequency of the external clock should be the same as that of the system clock (?). extal xtal external clock input open (a) example of external clock input when xtal pin left open extal xtal external clock input (b) example of external clock input when an inverted clock is input to xtal pin figure 25.4 example of external clock input rev. 2.0, 08/02, page 612 of 788 table 25.3 external clock input conditions v cc = 2.7 to 3.6 v v cc = 5.0 v 10 % % % % item symbol min max min max unit test conditions external clock input pulse width low level t exl 40 20 ns external clock input pulse width high level t exh 40 20 ns external clock rising time t exr 10 5 ns external clock falling time t exf 10 5 ns figure 25.5 0.4 0.6 0.4 0.6 t cyc ? 3 5 mhz clock pulse width low level t cl 80 80 ns ? < 5 mhz 0.4 0.6 0.4 0.6 t cyc ? 3 5 mhz clock pulse width high level t ch 80 80 ns ? < 5 mhz figure 28.6 t exh t exl t exr t exf v cc 0.5 extal figure 25.5 external clock input timing the oscillator and duty correction circuit have a function to adjust the waveform of the external clock input that is input to the extal pin. when a specified clock signal is input to the extal pin, internal clock signal output is determined after the external clock output stabilization delay time (t dext ) has passed. as the clock signal output is not determined during the t dext cycle, a reset signal should be set to low to hold it in reset state. table 25.4 shows the external clock output stabilization delay time. figure 25.6 shows the timing of the external clock output stabilization delay time. rev. 2.0, 08/02, page 613 of 788 table 25.4 external clock output stabilization delay time condition: v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ss = av ss = 0 v item symbol min. max. unit remarks external clock output stabilization delay time t dext * 500 m s figure 25.6 note: * t dext includes a 5(6 pulse width (t resw ). t dext * (internal and external) extal v cc 2.7 v v ih ? note: * the external clock output stabilization delay time (t dext ) includes a pulse width (t resw ). figure 25.6 timing of external clock output stabilization delay time 25.2 duty correction circuit the duty correction circuit is valid when the oscillating frequency is 5 mhz or more. it corrects the duty of a clock that is output from the oscillator, and generates the system clock (?). 25.3 medium-speed clock divider the medium-speed clock divider divides the system clock (?), and generates ?/2, ?/4, ?/8, ?/16, and ?/32 clocks. rev. 2.0, 08/02, page 614 of 788 25.4 bus master clock select circuit the bus master clock select circuit selects a clock to supply the bus master with either the system clock (?) or medium-speed clock (?/2, ?/4, ?/8, ?/16, or ?/32) by the sck2 to sck0 bits in sbycr. 25.5 subclock input circuit the subclock input circuit controls subclock input from the excl pin. to use the subclock, a 32.768-khz external clock should be input from the excl pin. at this time, the p96ddr bit in p9ddr should be cleared to 0, and the excle bit in lpwrcr should be set to 1. subclock input conditions are shown in table 25.5. when the subclock is not used, subclock input should not be enabled. table 25.5 subclock input conditions vcc = 2.7 to 5.5 v item symbol min typ max unit measurement condition subclock input pulse width low level t excll 15.26 m s subclock input pulse width high level t exclh 15.26 m s subclock input rising time t exclr 10ns subclock input falling time t exclf 10ns figure 25.7 t exclh t excll t exclr t exclf v cc 0.5 excl figure 25.7 subclock input timing 25.6 subclock waveform forming circuit to remove noise from the subclock input at the excl pin, the subclock is sampled by a divided ? clock. the sampling frequency is set by the nesel bit in lpwrcr. the subclock is not sampled in subactive mode, subsleep mode, or watch mode. rev. 2.0, 08/02, page 615 of 788 25.7 clock select circuit the clock select circuit selects the system clock that is used in this lsi. a clock generated by an oscillator to which the extal and xtal pins are input is selected as a system clock when returning from high-speed mode, medium-speed mode, sleep mode, reset state, or standby mode. a subclock input from the excl pin is selected as a system clock in subactive mode, subsleep mode, or watch mode. at this time, modules such as the cpu, tmr_0, tmr_1, wdt_0, wdt_1, ports, and interrupt controller and their functions operate depending on the ?sub. the count clock and sampling clock for each timer are divided ?sub clocks. 25.8 processing for x1 and x2 pins the x1 and x2 pins should be open as shown in figure 25.8. x1 x2 open open figure 25.8 processing for x1 and x2 pins rev. 2.0, 08/02, page 616 of 788 25.9 usage notes 25.9.1 note on resonator since all kinds of characteristics of the resonator are closely related to the board design by the user, use the example of resonator connection in this document for only reference; be sure to use an resonator that has been sufficiently evaluated by the user. consult with the resonator manufacturer about the resonator circuit ratings which vary depending on the stray capacitances of the resonator and installation circuit. make sure the voltage applied to the oscillator pins does not exceed the maximum rating. 25.9.2 notes on board design when using a crystal resonator, the crystal resonator and its load capacitors should be placed as close as possible to the xtal and extal pins. other signal lines should be routed away from the oscillator circuit to prevent inductive interference with the correct oscillation as shown in figure 25.9. c l2 signal a signal b c l1 this lsi xtal extal avoid figure 25.9 note on board design of oscillator circuit section rev. 2.0, 08/02, page 617 of 788 section 26 power-down modes for operating modes after the reset state is cancelled, this lsi has not only the normal program execution state but also seven power-down modes in which power dissipation is significantly reduced. in addition, there is also module stop mode in which reduced power dissipation can be achieved by individually stopping on-chip peripheral modules. medium-speed mode system clock frequency for the cpu operation can be selected as ?/2, ?/4, ?/8, ?/16,or ?/32. subactive mode the cpu operates based on the subclock and on-chip peripheral modules other than tmr_0, tmr_1, wdt_0, and wdt_1 stop operating. sleep mode the cpu stops but on-chip peripheral modules continue operating. subsleep mode the cpu and on-chip peripheral modules other than tmr_0, tmr_1, wdt_0, and wdt_1 stop operating. watch mode the cpu and on-chip peripheral modules other than wdt_1 stop operating. software standby mode clock oscillation stops, and the cpu and on-chip peripheral modules stop operating. hardware standby mode clock oscillation stops, and the cpu and on-chip peripheral modules enter reset state. module stop mode independently of above operating modes, on-chip peripheral modules that are not used can be stopped individually. 26.1 register descriptions power-down modes are controlled by the following registers. to access sbycr, lpwrcr, mstpcrh, and mstpcrl, the flshe bit in the serial timer control register (stcr) must be cleared to 0. for details on stcr, see section 3.2.3, serial timer control register (stcr). standby control register (sbycr) low power control register (lpwrcr) module stop control register h (mstpcrh) module stop control register l (mstpcrl) rev. 2.0, 08/02, page 618 of 788 26.1.1 standby control register (sbycr) sbycr controls power-down modes. bit bit name initial value r/w description 7 ssby 0 r/w software standby specifies the operating mode to be entered after executing the sleep instruction. when the sleep instruction is executed in high-speed mode or medium-speed mode: 0: shifts to sleep mode 1: shifts to software standby mode, subactive mode, or watch mode when the sleep instruction is executed in subactive mode: 0: shifts to subsleep mode 1: shifts to watch mode or high-speed mode note that the ssby bit is not changed even if a mode transition occurs by an interrupt. 6 5 4 sts2 sts1 sts0 0 0 0 r/w r/w r/w standby timer select 2 to 0 selects the wait time for clock stabilization from clock oscillation start when canceling software standby mode, watch mode, or subactive mode. select a wait time of 8 ms (oscillation stabilization time) or more, depending on the operating frequency. table 26.1 shows the relationship between the sts2 to sts0 values and wait time. with an external clock, there are no specific wait requirements. normally the minimum value is recommended. 3 ? 0rreserved this bit is always read as 0, and cannot be modified. rev. 2.0, 08/02, page 619 of 788 bit bit name initial value r/w description 2 1 0 sck2 sck1 sck0 0 0 0 r/w r/w r/w system clock select 2 to 0 selects a clock for the bus master in high-speed mode or medium-speed mode. when making a transition to subactive mode or watch mode, sck2 to sck0 must be cleared to 0. 000: high-speed mode 001: medium-speed clock: ?/2 010: medium-speed clock: ?/4 011: medium-speed clock: ?/8 100: medium-speed clock: ?/16 101: medium-speed clock: ?/32 11x: legend x: don't care table 26.1 operating frequency and wait time sts2 sts1 sts0 wait time 20 mhz 10 mhz 8 mhz 6 mhz 4 mhz 2 mhz unit 0 0 0 8192 states 0.4 0.8 1.0 1.3 20. 4.1 0 0 1 16384 states 0.8 1.6 2.0 2.7 4.1 8.2 0 1 0 32768 states 2.0 3.3 4.1 5.5 8.2 16.4 0 1 1 65536 states 4.1 6.6 8.2 10.9 16.4 32.8 1 0 0 131072 states 8.2 13.1 16.4 21.8 32.8 65.5 1 0 1 262144 states 16.4 26.2 32.8 43.6 65.6 131.2 ms 1 1 0 reserved ??????? 1 1 1 16 states * 0.8 1.6 2.0 2.7 4.0 8.0 m s shaded cells indicate the recommended specification. note: * this setting cannot be made in the flash-memory version of this lsi. rev. 2.0, 08/02, page 620 of 788 26.1.2 low-power control register (lpwrcr) lpwrcr controls power-down modes. bit bit name initial value r/w description 7 dton 0 r/w direct transfer on flag specifies the operating mode to be entered after executing the sleep instruction. when the sleep instruction is executed in high-speed mode or medium-speed mode: 0: shifts to sleep mode, software standby mode, or watch mode 1: shifts directly to subactive mode, or shifts to sleep mode or software standby mode when the sleep instruction is executed in subactive mode: 0: shifts to subsleep mode or watch mode 1: shifts directly to high-speed mode, or shifts to subsleep mode 6 lson 0 r/w low-speed on flag specifies the operating mode to be entered after executing the sleep instruction. this bit also controls whether to shift to high-speed mode or subactive mode when watch mode is cancelled. when the sleep instruction is executed in high-speed mode or medium-speed mode: 0: shifts to sleep mode, software standby mode, or watch mode 1: shifts to watch mode or subactive mode when the sleep instruction is executed in subactive mode: 0: shifts directly to watch mode or high-speed mode 1: shifts to subsleep mode or watch mode when watch mode is cancelled: 0: shifts to high-speed mode 1: shifts to subactive mode rev. 2.0, 08/02, page 621 of 788 bit bit name initial value r/w description 5 nesel 0 r/w noise elimination sampling frequency select selects the frequency by which the subclock (?sub) input from the excl pin is sampled using the clock (?) generated by the system clock pulse generator. clear this bit to 0 when ? is 5 mhz or more. 0: sampling using ?/32 clock 1: sampling using ?/4 clock 4 excle 0 r/w subclock input enable enables/disables subclock input from the excl pin. 0: disables subclock input from the excl pin 1: enables subclock input from the excl pin 3 ? ? ? ? 0r/wreserved an undefined value is read from this bit. this bit should not be set to 1. 2 to 0 ? ? ? ? all 0 r reserved these bits are always read as 0 and cannot be modified. 26.1.3 module stop control registers h and l (mstpcrh, mstpcrl) mstpcrh and mstpcrl specify on-chip peripheral modules to shift to module stop mode in module units. each module can enter module stop mode by setting the corresponding bit to 1. mstpcrh bit bit name initial value r/w corresponding module 7 mstp15 0 * r/w 6 mstp14 0 r/w data transfer controller (dtc) 5 mstp13 1 r/w 16-bit free-running timer (frt) 4 mstp12 1 r/w 8-bit timers (tmr_0, tmr_1) 3 mstp11 1 r/w 8-bit pwm timer (pwm), 14-bit pwm timer (pwmx) 2 mstp10 1 r/w d/a converter 1 mstp9 1 r/w a/d converter 0 mstp8 1 r/w 8-bit timers (tmr_x, tmr_y), timer connection note: * do not set this bit to 1. rev. 2.0, 08/02, page 622 of 788 mstpcrl bit bit name initial value r/w corresponding module 7 mstp7 1 r/w serial communication interface_0 (sci_0) 6 mstp6 1 r/w serial communication interface_1 (sci_1) 5 mstp5 1 r/w serial communication interface_2 (sci_2) 4 mstp4 1 r/w i 2 c bus interface_0 (iic_0) 3 mstp3 1 r/w i 2 c bus interface_1 (iic_1) 2 mstp2 1 r/w host interface (xbs), keyboard buffer controller, keyboard matrix interrupt mask register (kmimr), keyboard matrix interrupt mask register a (kmimra), port 6 pull-up mos control register (kmpcr) 1 mstp1 1 * r/w ? 0 mstp0 1 r/w host interface (lpc), wake-up event interrupt mask register b (wuemrb) note: * this bit can be read from or written to, however, operation is not affected. 26.2 mode transitions and lsi states figure 26.1 shows the enabled mode transition diagram. the mode transition from program execution state to program halt state is performed by the sleep instruction. the mode transition from program halt state to program execution state is performed by an interrupt. the 67%< input causes a mode transition from any state to hardware standby mode. the 5(6 input causes a mode transition from a state other than hardware standby mode to the reset state. table 26.2 shows the lsi internal states in each operating mode. rev. 2.0, 08/02, page 623 of 788 program halt state program execution state sck2 to sck0 are 0 sck2 to sck0 are not 0 sleep instruction ssby = 1, pss = 1, dton = 1, lson = 1 clock switching exception handling sleep instruction ssby = 1, pss = 1, dton = 1, lson = 0 after the oscillation stabilization time (sts2 to sts0), clock switching exception handling sleep instruction sleep instruction external interrupt * 3 any interrupt sleep instruction sleep instruction sleep instruction interrupt * 1 lson bit = 0 interrupt * 2 interrupt * 1 lson bit = 1 stby pin = high res pin = low stby pin = low ssby = 0, lson = 0 ssby = 1, pss = 0, lson = 0 ssby = 0, pss = 1, lson = 1 ssby = 1, pss = 1, dton = 0 res pin = high : transition after exception processing : power-down mode reset state high-speed mode (main clock) medium-speed mode (main clock) subactive mode (subclock) subsleep mode (subclock) hardware standby mode software standby mode sleep mode (main clock) watch mode (subclock) notes: 1. 2. 3. nmi, irq0 to irq2, irq6, irq7, and wdt1 interrupts nmi, irq0 to irq7, wdt0, wdt1, tmr0, and tmr1 interrupts nmi, irq0 to irq2, irq6, and irq7 interrupts ? when a transition is made between modes by means of an interrupt, the transition cannot be made on interrupt source generation alone. ensure that interrupt handling is performed after accepting the interrupt request. ? always select high-speed mode before making a transition to watch mode or sub-active mode. figure 26.1 mode transition diagram rev. 2.0, 08/02, page 624 of 788 table 26.2 lsi internal states in each mode function high- speed medium- speed sleep module stop watch sub- active sub- sleep software standby hardware standby system clock pulse generator function- ing function- ing function- ing function- ing halted halted halted halted halted subclock pulse generator function- ing function- ing function- ing function- ing function- ing function- ing function- ing halted halted instruction execution halted halted halted halted halted cpu registers function- ing medium- speed operation retained function- ing retained subclock operation retained retained undefined nmi irq0 to irq7 kin0 to kin15 external interrupts wue0 to wue7 function- ing function- ing function- ing function- ing function- ing function- ing function- ing function- ing halted dtc medium- speed operation function- ing/halted (retained) halted (retained) halted (retained) halted (retained) wdt_1 subclock operation wdt_0 function- ing tmr_0, tmr_1 subclock operation subclock operation frt tmr_x, tmr_y timer connection iic_0 iic_1 lpc function- ing/halted (retained) halted (retained) halted (retained) halted (retained) halted (retained) sci_0 sci_1 peripheral modules sci_2 function- ing function- ing function- ing function- ing/halted (reset) halted (reset) halted (reset) halted (reset) halted (reset) halted (reset) rev. 2.0, 08/02, page 625 of 788 function high- speed medium- speed sleep module stop watch sub- active sub- sleep software standby hardware standby pwm pwmx xbs, keyboard buffer controller d/a a/d function- ing function- ing/halted (reset) halted (reset) halted (reset) halted (reset) halted (reset) halted (reset) ram function- ing (dtc) function- ing retained function- ing retained retained retained peripheral modules i/o function- ing function- ing function- ing function- ing retained function- ing function- ing retained high impedance note: * halted (retained) means that internal register values are retained. the internal state is operation suspended. halted (reset) means that internal register values and internal states are initialized. in module stop mode, only modules for which a stop setting has been made are halted (reset or retained). 26.3 medium-speed mode the cpu makes a transition to medium-speed mode as soon as the current bus cycle ends according to the setting of the sck2 to sck0 bits in sbycr. in medium-speed mode, the cpu operates on the operating clock (?/2, ?/4, ?/8, ?/16, or ?/32). on-chip peripheral modules other than the bus masters always operate on the system clock (?). in medium-speed mode, a bus access is executed in the specified number of states with respect to the bus master operating clock. for example, if ?/4 is selected as the operating clock, on-chip memory is accessed in 4 states, and internal i/o registers in 8 states. by clearing all of bits sck2 to sck0 to 0, a transition is made to high-speed mode at the end of the current bus cycle. if a sleep instruction is executed when the ssby bit in sbycr is cleared to 0, and the lson bit in lpwrcr is cleared to 0, a transition is made to sleep mode. when sleep mode is cleared by an interrupt, medium-speed mode is restored. when the sleep instruction is executed with the ssby bit set to 1, the lson bit cleared to 0, and the pss bit in tcsr (wdt_1) cleared to 0, operation shifts to software standby mode. when software standby mode is cleared by an external interrupt, medium-speed mode is restored. when the 5(6 pin is set low and medium-speed mode is cancelled, operation shifts to the reset state. the same applies in the case of a reset caused by overflow of the watchdog timer. rev. 2.0, 08/02, page 626 of 788 when the 67%< pin is driven low, medium-speed mode is cancelled and a transition is made to hardware standby mode. figure 26.2 shows an example of medium-speed mode timing. ?, bus master clock peripheral module clock internal address bus internal write signal medium-speed mode sbycr sbycr figure 26.2 medium-speed mode timing 26.4 sleep mode the cpu makes a transition to sleep mode if the sleep instruction is executed when the ssby bit in sbycr is cleared to 0 and the lson bit in lpwrcr is cleared to 0. in sleep mode, cpu operation stops but the peripheral modules do not stop. the contents of the cpus internal registers are retained. sleep mode is exited by any interrupt, the 5(6 # pin, or the 67%< pin. when an interrupt occurs, sleep mode is exited and interrupt exception handling starts. sleep mode is not exited if the interrupt is disabled, or interrupts other than nmi are masked by the cpu. setting the 5(6 pin level low cancels sleep mode and selects the reset state. after the oscillation stabilization time has passed, driving the 5(6 pin high causes the cpu to start reset exception handling. when the 67%< pin level is driven low, sleep mode is cancelled and a transition is made to hardware standby mode. rev. 2.0, 08/02, page 627 of 788 26.5 software standby mode the cpu makes a transition to software standby mode when the sleep instruction is executed while the ssby bit in sbycr is set to 1, the lson bit in lpwrcr is cleared to 0, and the pss bit in tcsr (wdt_1) is cleared to 0. in software standby mode, the cpu, on-chip peripheral modules, and clock pulse generator all stop. however, the contents of the cpus internal registers, on-chip ram data, i/o ports, and the states of on-chip peripheral modules other than the sci, pwm, and pwmx, are retained as long as the prescribed voltage is supplied. software standby mode is cleared by an external interrupt (nmi, irq0 to irq2, irq6, or irq7), the 5(6 pin input, or 67%< pin input. when an external interrupt request signal is input, system clock oscillation starts, and after the elapse of the time set in bits sts2 to sts0 in sbycr, software standby mode is cleared, and interrupt exception handling is started. when clearing software standby mode with an irq0 to irq2, irq6, or irq7 interrupt, set the corresponding enable bit to 1 and ensure that no interrupt with a higher priority than interrupts irq0 to irq2, irq6, and irq7 is generated. software standby mode cannot be cleared if an interrupt enable bit corresponding to an irq0 to irq2, irq6, or irq7 interrupt is cleared to 0 or if the interrupt has been masked on the cpu side. when the 5(6 pin is driven low, system clock oscillation is started. at the same time as system clock oscillation starts, the system clock is supplied to the entire lsi. note that the 5(6 pin must be held low until clock oscillation stabilizes. when the 5(6 pin goes high after clock oscillation stabilizes, the cpu begins reset exception handling. when the 67%< pin is driven low, software standby mode is cancelled and a transition is made to hardware standby mode. figure 26.3 shows an example in which a transition is made to software standby mode at the falling edge of the nmi pin, and software standby mode is cleared at the rising edge of the nmi pin. in this example, an nmi interrupt is accepted with the nmieg bit in syscr cleared to 0 (falling edge specification), then the nmieg bit is set to 1 (rising edge specification), the ssby bit is set to 1, and a sleep instruction is executed, causing a transition to software standby mode. software standby mode is then cleared at the rising edge of the nmi pin. rev. 2.0, 08/02, page 628 of 788 oscillator ? nmi nmieg ssby nmi exception handling nmieg = 1 ssby = 1 sleep instruction software standby mode (power-down mode) oscillation stabilization time t osc2 nmi exception handling figure 26.3 application example in software standby mode 26.6 hardware standby mode the cpu makes a transition to hardware standby mode from any mode when the 67%< pin is driven low. in hardware standby mode, all functions enter the reset state. as long as the prescribed voltage is supplied, on-chip ram data is retained. the i/o ports are set to the high-impedance state. in order to retain on-chip ram data, the rame bit in syscr should be cleared to 0 before driving the 67%< pin low. do not change the state of the mode pins (md1 and md0) while this lsi is in hardware standby mode. hardware standby mode is cleared by the 67%< pin input or the 5(6 pin input. when the 67%< pin is driven high while the 5(6 pin is low, clock oscillation is started. ensure that the 5(6 pin is held low until system clock oscillation stabilizes. when the 5(6 pin is subsequently driven high after the clock oscillation stabilization time has passed, reset exception handling starts. rev. 2.0, 08/02, page 629 of 788 figure 26.4 shows an example of hardware standby mode timing. oscillator res stby oscillation stabilization time reset exception handling figure 26.4 hardware standby mode timing 26.7 watch mode the cpu makes a transition to watch mode when the sleep instruction is executed in high-speed mode or subactive mode with the ssby bit in sbycr set to 1, the dton bit in lpwrcr cleared to 0, and the pss bit in tcsr (wdt_1) set to 1. in watch mode, the cpu is stopped and peripheral modules other than wdt_1 are also stopped. the contents of the cpus internal registers, several on-chip peripheral module registers, and on- chip ram data are retained and the i/o ports retain their values before transition as long as the prescribed voltage is supplied. watch mode is exited by an interrupt (wovi1, nmi, irq0 to irq2, irq6, or irq7), 5(6 pin input, or 67%< pin input. when an interrupt occurs, watch mode is exited and a transition is made to high-speed mode or medium-speed mode when the lson bit in lpwrcr cleared to 0 or to subactive mode when the lson bit is set to 1. when a transition is made to high-speed mode, a stable clock is supplied to the entire lsi and interrupt exception handling starts after the time set in the sts2 to sts0 bits in sbycr has elapsed. in the case of an irq0 to irq2, irq6, or irq7 interrupt, watch mode is not exited if the corresponding enable bit has been cleared to 0. in the case of interrupts from the on- chip peripheral modules, watch mode is not exited if the interrupt enable register has been set to disable the reception of that interrupt, or the interrupt is masked by the cpu. when the 5(6 pin is driven low, system clock oscillation starts. simultaneously with the start of system clock oscillation, the system clock is supplied to the entire lsi. note that the 5(6 pin must rev. 2.0, 08/02, page 630 of 788 be held low until clock oscillation is stabilized. if the 5(6 pin is driven high after the clock oscillation stabilization time has passed, the cpu begins reset exception handling. if the 67%< pin is driven low, the lsi enters hardware standby mode. 26.8 subsleep mode the cpu makes a transition to subsleep mode when the sleep instruction is executed in subactive mode with the ssby bit in sbycr cleared to 0, the lson bit in lpwrcr set to 1, and the pss bit in tcsr (wdt_1) set to 1. in subsleep mode, the cpu is stopped. peripheral modules other than tmr_0, tmr_1, wdt_0, and wdt_1 are also stopped. the contents of the cpus internal registers, several on-chip peripheral module registers, and on-chip ram data are retained and the i/o ports retain their values before transition as long as the prescribed voltage is supplied. subsleep mode is exited by an interrupt (interrupts by on-chip peripheral modules, nmi, irq0 to irq7), the 5(6 pin input, or the 67%< pin input. when an interrupt occurs, subsleep mode is exited and interrupt exception handling starts. in the case of an irq0 to irq7 interrupt, subsleep mode is not exited if the corresponding enable bit has been cleared to 0. in the case of interrupts from the on-chip peripheral modules, subsleep mode is not exited if the interrupt enable register has been set to disable the reception of that interrupt, or the interrupt is masked by the cpu. when the 5(6 pin is driven low, system clock oscillation starts. simultaneously with the start of system clock oscillation, the system clock is supplied to the entire lsi. note that the 5(6 pin must be held low until clock oscillation is stabilized. if the 5(6 pin is driven high after the clock oscillation stabilization time has passed, the cpu begins reset exception handling. if the 67%< pin is driven low, the lsi enters hardware standby mode. rev. 2.0, 08/02, page 631 of 788 26.9 subactive mode the cpu makes a transition to subactive mode when the sleep instruction is executed in high- speed mode with the ssby bit in sbycr set to 1, the dton bit and lson bit in lpwrcr set to 1, and the pss bit in tcsr (wdt_1) set to 1. when an interrupt occurs in watch mode, and if the lson bit in lpwrcr is 1, a direct transition is made to subactive mode. similarly, if an interrupt occurs in subsleep mode, a transition is made to subactive mode. in subactive mode, the cpu operates at a low speed based on the subclock and sequentially executes programs. peripheral modules other than tmr_0, tmr_1, wdt_0, and wdt_1 are also stopped. when operating the cpu in subactive mode, the sck2 to sck0 bits in sbycr must be cleared to 0. subactive mode is exited by the sleep instruction, 5(6 pin input, or 67%< pin input. when the sleep instruction is executed with the ssby bit in sbycr set to 1, the dton bit in lpwrcr cleared to 0, and the pss bit in tcsr (wdt_1) set to 1, the cpu exits subactive mode and a transition is made to watch mode. when the sleep instruction is executed with the ssby bit in sbycr cleared to 0, the lson bit in lpwrcr set to 1, and the pss bit in tcsr (wdt_1) set to 1, a transition is made to subsleep mode. when the sleep instruction is executed with the ssby bit in sbycr set to 1, the dton bit and lson bit in lpwrcr set to 10, and the pss bit in tcsr (wdt_1) set to 1, a direct transition is made to high-speed mode. for details of direct transitions, see section 26.11, direct transitions. when the 5(6 pin is driven low, system clock oscillation starts. simultaneously with the start of system clock oscillation, the system clock is supplied to the entire lsi. note that the 5(6 pin must be held low until the clock oscillation is stabilized. if the 5(6 pin is driven high after the clock oscillation stabilization time has passed, the cpu begins reset exception handling. if the 67%< pin is driven low, the lsi enters hardware standby mode. rev. 2.0, 08/02, page 632 of 788 26.10 module stop mode module stop mode can be individually set for each on-chip peripheral module. when the corresponding mstp bit in mstpcr is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. in turn, when the corresponding mstp bit is cleared to 0, module stop mode is cancelled and the module operation resumes at the end of the bus cycle. in module stop mode, the internal states of modules other than the sci, d/a converter, a/d converter, pwm, and pwmx are retained. after the reset state is cancelled, all modules other than dtc are in module stop mode. while an on-chip peripheral module is in module stop mode, read/write access to its registers is disabled. 26.11 direct transitions the cpu executes programs in three modes: high-speed, medium-speed, and subactive. when a direct transition is made from high-speed mode to subactive mode, there is no interruption of program execution. a direct transition is enabled by setting the dton bit in lpwrcr to 1 and then executing the sleep instruction. after a transition, direct transition exception handling starts. the cpu makes a transition to subactive mode when the sleep instruction is executed in high- speed mode with the ssby bit in sbycr set to 1, the lson bit and dton bit in lpwrcr set to 11, and the pss bit in tscr (wdt_1) set to 1. to make a direct transition to high-speed mode after the time set in the sts2 to sts0 bits in sbycr has elapsed, execute the sleep instruction in subactive mode with the ssby bit in sbycr set to 1, the lson bit and dton bit in lpwrcr set to 01, and the pss bit in tscr (wdt_1) set to 1. rev. 2.0, 08/02, page 633 of 788 26.12 usage notes 26.12.1 i/o port status the status of the i/o ports is retained in software standby mode. therefore, when a high level is output, the current consumption is not reduced by the amount of current to support the high level output. 26.12.2 current consumption when waiting for oscillation stabilization the current consumption increases during oscillation stabilization. 26.12.3 dtc module stop mode if the dtc module stop mode specification and dtc bus request occur simultaneously, the bus is released to the dtc and the mstp bit cannot be set to 1. after completing the dtc bus cycle, set the mstp bit to 1 again. rev. 2.0, 08/02, page 634 of 788 rev. 2.0, 08/02, page 635 of 790 section 27 list of registers the register list gives information on the on-chip i/o register addresses, how the register bits are configured, and the register states in each operating mode. the information is given as shown below. 1. register addresses (address order) registers are listed from the lower allocation addresses. the msb-side address is indicated for 16-bit addresses. registers are classified by functional modules. the access size is indicated. 2. register bits bit configurations of the registers are described in the same order as the register addresses (address order) above. reserved bits are indicated by ? in the bit name column. the bit number in the bit-name column indicates that the whole register is allocated as a counter or for holding data. 16-bit registers are indicated from the bit on the msb side. 3. register states in each operating mode register states are described in the same order as the register addresses (address order) above. the register states described here are for the basic operating modes. if there is a specific reset for an on-chip peripheral module, refer to the section on that on-chip peripheral module. 4. register select conditions register states are described in the same order as the register addresses (address order) above. for details on the register select conditions, refer to section 3.2.2, system control register (syscr), 3.2.3, serial timer control register (stcr), 26.1.3, module stop control registers h, l (mstpcrh, mstpcrl), and the register descriptions for each module. 27.1 register addresses (address order) the data bus width indicates the numbers of bits by which the register is accessed. the number of access states indicates the number of states based on the specified reference clock. rev. 2.0, 08/02, page 636 of 790 register name abbreviation number of bits address module data bus width number of access states port g open drain control register pgnocr * 1 8h'fe16port83 port e open drain control register penocr * 1 8h'fe18port83 port f open drain control register pfnocr * 1 8h'fe19port83 port c open drain control register pcnocr * 1 8h'fe1cport83 port d open drain control register pdnocr * 1 8h'fe1dport83 bidirectional data register 0mw twr0mw 8 h'fe20 lpc 8 3 bidirectional data register 0sw twr0sw 8 h'fe20 lpc 8 3 bidirectional data register 1 twr1 8 h'fe21 lpc 8 3 bidirectional data register 2 twr2 8 h'fe22 lpc 8 3 bidirectional data register 3 twr3 8 h'fe23 lpc 8 3 bidirectional data register 4 twr4 8 h'fe24 lpc 8 3 bidirectional data register 5 twr5 8 h'fe25 lpc 8 3 bidirectional data register 6 twr6 8 h'fe26 lpc 8 3 bidirectional data register 7 twr7 8 h'fe27 lpc 8 3 bidirectional data register 8 twr8 8 h'fe28 lpc 8 3 bidirectional data register 9 twr9 8 h'fe29 lpc 8 3 bidirectional data register 10 twr10 8 h'fe2a lpc 8 3 bidirectional data register 11 twr11 8 h'fe2b lpc 8 3 bidirectional data register 12 twr12 8 h'fe2c lpc 8 3 bidirectional data register 13 twr13 8 h'fe2d lpc 8 3 bidirectional data register 14 twr14 8 h'fe2e lpc 8 3 bidirectional data register 15 twr15 8 h'fe2f lpc 8 3 input data register 3 idr3 8 h'fe30 lpc 8 3 output data register 3 odr3 8 h'fe31 lpc 8 3 status register 3 str3 8 h'fe32 lpc 8 3 lpc channel address register h ladr3h 8 h'fe34 lpc 8 3 lpc channel address register l ladr3l 8 h'fe35 lpc 8 3 serirq control register 0 sirqcr0 8 h'fe36 lpc 8 3 serirq control register 1 sirqcr1 8 h'fe37 lpc 8 3 input data register 1 idr1 8 h'fe38 lpc 8 3 output data register 1 odr1 8 h'fe39 lpc 8 3 status register 1 str1 8 h'fe3a lpc 8 3 rev. 2.0, 08/02, page 637 of 790 register name abbreviation number of bits address module data bus width number of access states input data register 2 idr2 8 h'fe3c lpc 8 3 output data register 2 odr2 8 h'fe3d lpc 8 3 status register 2 str2 8 h'fe3e lpc 8 3 host interface select register hisel 8 h'fe3f lpc 8 3 host interface control register 0 hicr0 8 h'fe40 lpc 8 3 host interface control register 1 hicr1 8 h'fe41 lpc 8 3 host interface control register 2 hicr2 8 h'fe42 lpc 8 3 host interface control register 3 hicr3 8 h'fe43 lpc 8 3 wakeup event interrupt mask register b wuemrb * 2 8h'fe44int83 port g output data register pgodr * 1 8h'fe46port83 port g input data register pgpin * 1 8h'fe47 (read) port 8 3 port g data direction register pgddr * 1 8h'fe47 (write) port 8 3 port e output data register peodr * 1 8h'fe48port83 port f output data register pfodr * 1 8h'fe49port83 port e input data register pepin * 1 8h'fe4a (read) port 8 3 port e data direction register peddr * 1 8h'fe4a (write) port 8 3 port f input data register pfpin * 1 8h'fe4b (read) port 8 3 port f data direction register pfddr * 1 8h'fe4b (write) port 8 3 port c output data register pcodr * 1 8h'fe4cport83 port d output data register pdodr * 1 8h'fe4dport83 port c input data register pcpin * 1 8h'fe4e (read) port 8 3 port c data direction register pcddr * 1 8h'fe4e (write) port 8 3 port d input data register pdpin * 1 8h'fe4f (read) port 8 3 port d data direction register pdddr * 1 8h'fe4f (write) port 8 3 rev. 2.0, 08/02, page 638 of 790 register name abbreviation number of bits address module bus width number of access states host interface control register 2 hicr2 8 h'fe80 xbs 8 2 input data register_3 idr_3 8 h'fe81 xbs 8 2 output data register_3 odr_3 8 h'fe82 xbs 8 2 status register_3 str_3 8 h'fe83 xbs 8 2 input data register_4 idr_4 8 h'fe84 xbs 8 2 output data register_4 odr_4 8 h'fe85 xbs 8 2 status register_4 str_4 8 h'fe86 xbs 8 2 i 2 c bus extended control register_0 icxr_0 8 h'fed4 iic_0 8 2 i 2 c bus extended control register_1 icxr_1 8 h'fed5 iic_1 8 2 keyboard control register h_0 kbcrh_0 8 h'fed8 keyboard buffer controller_ 0 82 keyboard control register l_0 kbcrl_0 8 h'fed9 keyboard buffer controller_ 0 82 keyboard data buffer register_0 kbbr_0 8 h'feda keyboard buffer controller_ 0 82 keyboard control register h_1 kbcrh_1 8 h'fedc keyboard buffer controller_ 1 82 keyboard control register l_1 kbcrl_1 8 h'fedd keyboard buffer controller_ 1 82 keyboard data buffer register_1 kbbr_1 8 h'fede keyboard buffer controller_ 1 82 keyboard control register h_2 kbcrh_2 8 h'fee0 keyboard buffer controller_ 2 82 rev. 2.0, 08/02, page 639 of 790 register name abbreviation number of bits address module data bus width number of access states keyboard control register l_2 kbcrl_2 8 h'fee1 keyboard buffer controller_ 2 82 keyboard data buffer register_2 kbbr_2 8 h'fee2 keyboard buffer controller_ 2 82 keyboard comparator control register kbcomp 8 h'fee4 irda/ extended a/d 82 ddc switch register ddcswr 8 h'fee6 iic_0 8 2 interrupt control register a icra 8 h'fee8 int 8 2 interrupt control register b icrb 8 h'fee9 int 8 2 interrupt control register c icrc 8 h'feea int 8 2 irq status register isr 8 h'feeb int 8 2 irq sense control register h iscrh 8 h'feec int 8 2 irq sense control register l iscrl 8 h'feed int 8 2 dtc enable register a dtcera 8 h'feee dtc 8 2 dtc enable register b dtcerb 8 h'feef dtc 8 2 dtc enable register c dtcerc 8 h'fef0 dtc 8 2 dtc enable register d dtcerd 8 h'fef1 dtc 8 2 dtc enable register e dtcere 8 h'fef2 dtc 8 2 dtc vector register dtvecr 8 h'fef3 dtc 8 2 address break control register abrkcr 8 h'fef4 int 8 2 break address register a bara 8 h'fef5 int 8 2 break address register b barb 8 h'fef6 int 8 2 break address register c barc 8 h'fef7 int 8 2 flash memory control register 1 flmcr1 8 h'ff80 flash 8 2 flash memory control register 2 flmcr2 8 h'ff81 flash 8 2 peripheral clock select register pcsr 8 h'ff82 pwm 8 2 erase block register 1 ebr1 8 h'ff82 flash 8 2 system control register 2 syscr2 8 h'ff83 system 8 2 erase block register 2 ebr2 8 h'ff83 flash 8 2 rev. 2.0, 08/02, page 640 of 790 register name abbreviation number of bits address module data bus width number of access states standby control register sbycr 8 h'ff84 system 8 2 low power control register lpwrcr 8 h'ff85 system 8 2 module stop control register h mstpcrh 8 h'ff86 system 8 2 module stop control register l mstpcrl 8 h'ff87 system 8 2 serial mode register_1 smr_1 8 h'ff88 sci_1 8 2 i 2 c bus control register_1 iccr_1 8 h'ff88 iic_1 8 2 bit rate register_1 brr_1 8 h'ff89 sci_1 8 2 i 2 c bus status register_1 icsr_1 8 h'ff89 iic_1 8 2 serial control register_1 scr_1 8 h'ff8a sci_1 8 2 transmit data register_1 tdr_1 8 h'ff8b sci_1 8 2 serial status register_1 ssr_1 8 h'ff8c sci_1 8 2 receive data register_1 rdr_1 8 h'ff8d sci_1 8 2 smart card mode register_1 scmr_1 8 h'ff8e sci_1 8 2 i 2 c bus data register_1 icdr_1 8 h'ff8e iic_1 8 2 second slave address register_1 sarx_1 8 h'ff8e iic_1 8 2 i 2 c bus mode register_1 icmr_1 8 h'ff8f iic_1 8 2 slave address register_1 sar_1 8 h'ff8f iic_1 8 2 timer interrupt enable register tier 8 h'ff90 frt 8 2 timer control/status register tcsr 8 h'ff91 frt 8 2 free running counter h frch 8 h'ff92 frt 8 2 free running counter l frcl 8 h'ff93 frt 8 2 output control register ah ocrah 8 h'ff94 frt 8 2 output control register bh ocrbh 8 h'ff94 frt 8 2 output control register al ocral 8 h'ff95 frt 8 2 output control register bl ocrbl 8 h'ff95 frt 8 2 timer control register tcr 8 h'ff96 frt 8 2 timer output compare control register tocr 8 h'ff97 frt 8 2 input capture register ah icrah 8 h'ff98 frt 8 2 output control register arh ocrarh 8 h'ff98 frt 8 2 input capture register al icral 8 h'ff99 frt 8 2 output control register arl ocrarl 8 h'ff99 frt 8 2 input capture register bh icrbh 8 h'ff9a frt 8 2 rev. 2.0, 08/02, page 641 of 790 register name abbreviation number of bits address module data bus width number of access states output control register afh ocrafh 8 h'ff9a frt 8 2 input capture register bl icrbl 8 h'ff9b frt 8 2 output control register afl ocrafl 8 h'ff9b frt 8 2 input capture register ch icrch 8 h'ff9c frt 8 2 output compare register dmh ocrdmh 8 h'ff9c frt 8 2 input capture register cl icrcl 8 h'ff9d frt 8 2 output compare register dml ocrdml 8 h'ff9d frt 8 2 input capture register dh icrdh 8 h'ff9e frt 8 2 input capture register dl icrdl 8 h'ff9f frt 8 2 serial mode register_2 smr_2 8 h'ffa0 sci_2 8 2 pwm (d/a) control register dacr 8 h'ffa0 pwmx 8 2 pwm (d/a) data register ah dadrah 8 h'ffa0 pwmx 8 2 pwm (d/a) data register al dadral 8 h'ffa1 pwmx 8 2 bit rate register_2 brr_2 8 h'ffa1 sci_2 8 2 serial control register_2 scr_2 8 h'ffa2 sci_2 8 2 transmit data register_2 tdr_2 8 h'ffa3 sci_2 8 2 serial status register_2 ssr_2 8 h'ffa4 sci_2 8 2 receive data register_2 rdr_2 8 h'ffa5 sci_2 8 2 smart card mode register_2 scmr_2 8 h'ffa6 sci_2 8 2 pwm (d/a) counter h dacnth 8 h'ffa6 pwmx 8 2 pwm (d/a) data register bh dadrbh 8 h'ffa6 pwmx 8 2 pwm (d/a) counter l dacntl 8 h'ffa7 pwmx 8 2 pwm (d/a) data register bl dadrbl 8 h'ffa7 pwmx 8 2 timer control/status register_0 tcsr_0 8 h'ffa8 wdt 8 2 timer counter_0 tcnt_0 8 h'ffa8 (write) wdt_0 8 2 timer counter_0 tcnt_0 8 h'ffa9 (read) wdt_0 8 2 port a output data register paodr 8 h'ffaa port 8 2 port a input data register papin 8 h'ffab port 8 2 port a data direction register paddr 8 h'ffab port 8 2 port 1 pull-up mos control register p1pcr 8 h'ffac port 8 2 rev. 2.0, 08/02, page 642 of 790 register name abbreviation number of bits address module data bus width number of access states port 2 pull-up mos control register p2pcr 8 h'ffad port 8 2 port 3 pull-up mos control register p3pcr 8 h'ffae port 8 2 port 1 data direction register p1ddr 8 h'ffb0 port 8 2 port 2 data direction register p2ddr 8 h'ffb1 port 8 2 port 1 data register p1dr 8 h'ffb2 port 8 2 port 2 data register p2dr 8 h'ffb3 port 8 2 port 3 data direction register p3ddr 8 h'ffb4 port 8 2 port 4 data direction register p4ddr 8 h'ffb5 port 8 2 port 3 data register p3dr 8 h'ffb6 port 8 2 port 4 data register p4dr 8 h'ffb7 port 8 2 port 5 data direction register p5ddr 8 h'ffb8 port 8 2 port 6 data direction register p6ddr 8 h'ffb9 port 8 2 port 5 data register p5dr 8 h'ffba port 8 2 port 6 data register p6dr 8 h'ffbb port 8 2 port b output data register pbodr 8 h'ffbc port 8 2 port b input data register pbpin 8 h'ffbd (read) port 8 2 port 8 data direction register p8ddr 8 h'ffbd (write) port 8 2 port 7 input data register p7pin 8 h'ffbe (read) port 8 2 port b data direction register pbddr 8 h'ffbe (write) port 8 2 port 8 data register p8dr 8 h'ffbf port 8 2 port 9 data direction register p9ddr 8 h'ffc0 port 8 2 port 9 data register p9dr 8 h'ffc1 port 8 2 interrupt enable register ier 8 h'ffc2 int 8 2 serial timer control register stcr 8 h'ffc3 system 8 2 system control register syscr 8 h'ffc4 system 8 2 mode control register mdcr 8 h'ffc5 system 8 2 bus control register bcr 8 h'ffc6 bsc 8 2 wait state control register wscr 8 h'ffc7 bsc 8 2 timer control register_0 tcr_0 8 h'ffc8 tmr_0 8 2 rev. 2.0, 08/02, page 643 of 790 register name abbreviation number of bits address module data bus width number of access states timer control register_1 tcr_1 8 h'ffc9 tmr_1 8 2 timer control/status register_0 tcsr_0 8 h'ffca tmr_0 8 2 timer control/status register_1 tcsr_1 8 h'ffcb tmr_1 16 2 time constant register a_0 tcora_0 8 h'ffcc tmr_0 16 2 time constant register a_1 tcora_1 8 h'ffcd tmr_1 16 2 time constant register b_0 tcorb_0 8 h'ffce tmr_0 16 2 time constant register b_1 tcorb_1 8 h'ffcf tmr_1 16 2 timer counter_0 tcnt_0 8 h'ffd0 tmr_0 16 2 timer counter_1 tcnt_1 8 h'ffd1 tmr_1 16 2 pwm output enable register b pwoerb 8 h'ffd2 pwm 8 2 pwm output enable register a pwoera 8 h'ffd3 pwm 8 2 pwm data polarity register b pwdprb 8 h'ffd4 pwm 8 2 pwm data polarity register a pwdpra 8 h'ffd5 pwm 8 2 pwm register select pwsl 8 h'ffd6 pwm 8 2 pwm data registers 0 to 15 pwdr0 to pwdr15 8 h'ffd7 pwm 8 2 serial mode register_0 smr_0 8 h'ffd8 sci_0 8 2 i 2 c bus control register_0 iccr_0 8 h'ffd8 iic_0 8 2 bit rate register_0 brr_0 8 h'ffd9 sci_0 8 2 i 2 c bus status register_0 icsr_0 8 h'ffd9 iic_0 8 2 serial control register_0 scr_0 8 h'ffda sci_0 8 2 transmit data register_0 tdr_0 8 h'ffdb sci_0 8 2 serial status register_0 ssr_0 8 h'ffdc sci_0 8 2 receive data register_0 rdr_0 8 h'ffdd sci_0 8 2 smart card mode register_0 scmr_0 8 h'ffde sci_0 8 2 i 2 c bus data register_0 icdr_0 8 h'ffde iic_0 8 2 second slave address register_0 sarx_0 8 h'ffde iic_0 8 2 i 2 c bus mode register_0 icmr_0 8 h'ffdf iic_0 8 2 slave address register_0 sar_0 8 h'ffdf iic_0 8 2 a/d data register ah addrah 8 h'ffe0 a/d converter 82 rev. 2.0, 08/02, page 644 of 790 register name abbreviation number of bits address module data bus width number of access states a/d data register al addral 8 h'ffe1 a/d converter 82 a/d data register bh addrbh 8 h'ffe2 a/d converter 82 a/d data register bl addrbl 8 h'ffe3 a/d converter 82 a/d data register ch addrch 8 h'ffe4 a/d converter 82 a/d data register cl addrcl 8 h'ffe5 a/d converter 82 a/d data register dh addrdh 8 h'ffe6 a/d converter 82 a/d data register dl addrdl 8 h'ffe7 a/d converter 82 a/d control/status register adcsr 8 h'ffe8 a/d converter 82 a/d control register adcr 8 h'ffe9 a/d converter 82 timer control/status register_1 tcsr_1 8 h'ffea wdt_1 8 2 timer counter_1 tcnt_1 8 h'ffea (write) wdt_1 8 2 timer counter_1 tcnt_1 8 h'ffeb (read) wdt_1 8 2 host interface control register hicr 8 h'fff0 xbs 8 2 timer control register_x tcr_x 8 h'fff0 tmr_x 16 2 timer control register_y tcr_y 8 h'fff0 tmr_y 16 2 keyboard matrix interrupt register 6 kmimr 8 h'fff1 int 8 2 timer control/status register_x tcsr_x 8 h'fff1 tmr_x 16 2 timer control/status register_y tcsr_y 8 h'fff1 tmr_y 16 2 pull-up mos control register kmpcr 8 h'fff2 port 8 2 input capture register r ticrr 8 h'fff2 tmr_x 16 2 time constant register a_y tcora_y 8 h'fff2 tmr_y 16 2 keyboard matrix interrupt register a kmimra 8 h'fff3 int 8 2 input capture register f ticrf 8 h'fff3 tmr_x 16 2 time constant register b_y tcorb_y 8 h'fff3 tmr_y 16 2 rev. 2.0, 08/02, page 645 of 790 register name abbreviation number of bits address module data bus width number of access states input data register_1 idr_1 8 h'fff4 xbs 8 2 timer counter_x tcnt_x 8 h'fff4 tmr_x 16 2 timer counter_y tcnt_y 8 h'fff4 tmr_y 16 2 output data register_1 odr_1 8 h'fff5 xbs 8 2 timer constant register c tcorc 8 h'fff5 tmr_x 16 2 timer input select register tisr 8 h'fff5 tmr_y 16 2 status register_1 str_1 8 h'fff6 xbs 8 2 timer constant register a_x tcora_x 8 h'fff6 tmr_x 16 2 timer constant register b_x tcorb_x 8 h'fff7 tmr_x 16 2 d/a data register 0 dadr0 8 h'fff8 d/a converter 82 d/a data register 1 dadr1 8 h'fff9 d/a converter 82 d/a control register dacr 8 h'fffa d/a converter 82 input data register_2 idr_2 8 h'fffc xbs 8 2 timer connection register i tconri 8 h'fffc timer connection 82 output data register_2 odr_2 8 h'fffd xbs 8 2 timer connection register o tconro 8 h'fffd timer connection 82 status register_2 str_2 8 h'fffe xbs 8 2 timer connection register s tconrs 8 h'fffe timer connection 82 edge sense register sedgr 8 h'ffff timer connection 82 notes: 1. can be used on the h8s/2160b and h8s/2161b. 2. not supported by the h8s/2148b. rev. 2.0, 08/02, page 646 of 790 27.2 register bits register addresses and bit names of the on-chip peripheral modules are described below. 16-bit registers are shown as 2 lines. register abbreviation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module pgnocr * 1 pg7nocr pg6nocr pg5nocr pg4nocr pg3nocr pg2nocr pg1nocr pg0nocr penocr * 1 pe7nocr pe6nocr pe5nocr pe4nocr pe3nocr pe2nocr pe1nocr pe0nocr pfnocr * 1 pf7nocr pf6nocr pf5nocr pf4nocr pf3nocr pf2nocr pf1nocr pf0nocr pcnocr * 1 pc7nocr pc6nocr pc5nocr pc4nocr pc3nocr pc2nocr pc1nocr pc0nocr pdnocr * 1 pd7nocr pd6nocr pd5nocr pd4nocr pd3nocr pd2nocr pd1nocr pd0nocr port twr0mw bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 twr0sw bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 twr1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 twr2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 twr3 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 twr4 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 twr5 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 twr6 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 twr7 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 twr8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 twr9 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 twr10 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 twr11 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 twr12 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 twr13 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 twr14 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 twr15 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 idr3 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 odr3 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 str3 * 2 ibf3b obf3b mwmf swmf c/ ' 3 dbu32 ibf3a obf3a str3 * 3 dbu37 dbu36 dbu35 dbu34 c/ ' 3 dbu32 ibf3a obf3a ladr3h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ladr3l bit 7 bit 6 bit 5 bit 4 bit 3 ? bit 1 twre lpc rev. 2.0, 08/02, page 647 of 790 register abbreviation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module sirqcr0 q/ & selreq iedir smie3b smie3a smie2 irq12e1 irq1e1 sirqcr1 irq11e3 irq10e3 irq9e3 irq6e3 irq11e2 irq10e2 irq9e2 irq6e2 idr1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 odr1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 str1 dbu17 dbu16 dbu15 dbu14 c/ ' 1 dbu12 ibf1 obf1 idr2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 odr2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 str2 dbu27 dbu26 dbu25 dbu24 c/ ' 2 dbu22 ibf2 obf2 hisel selstr3 selirq11 selirq10 selirq9 selirq6 selsmi selirq12 selirq1 hicr0 lpc3e lpc2e lpc1e fga20e sdwne pmee lsmie lscie hicr1 lpcbsy clkreq irqbsy lrstb sdwnb pmeb lsmib lscib hicr2 ga20 lrst sdwn abrt ibfie3 ibfie2 ibfie1 errie hicr3 lframe clkrun serirq lreset lpcpd pme lsmi lsci lpc wuemrb * 5 wuemr7 wuemr6 wuemr5 wuemr4 wuemr3 wuemr2 wuemr1 wuemr0 int pgodr * 1 pg7odr pg6odr pg5odr pg4odr pg3odr pg2odr pg1odr pg0odr pgpin * 1 pg7pin pg6pin pg5pin pg4pin pg3pin pg2pin pg1pin pg0pin pgddr * 1 pg7ddr pg6ddr pg5ddr pg4ddr pg3ddr pg2ddr pg1ddr pg0ddr peodr * 1 pe7odr pe6odr pe5odr pe4odr pe3odr pe2odr pe1odr pe0odr pfodr * 1 pf7odr pf6odr pf5odr pf4odr pf3odr pf2odr pf1odr pf0odr pepin * 1 pe7pin pe6pin pe5pin pe4pin pe3pin pe2pin pe1pin pe0pin peddr * 1 pe7ddr pe6ddr pe5ddr pe4ddr pe3ddr pe2ddr pe1ddr pe0ddr pfpin * 1 pf7pin pf6pin pf5pin pf4pin pf3pin pf2pin pf1pin pf0pin pfddr * 1 pf7ddr pf6ddr pf5ddr pf4ddr pf3ddr pf2ddr pf1ddr pf0ddr pcodr * 1 pc7odr pc6odr pc5odr pc4odr pc3odr pc2odr pc1odr pc0odr pdodr * 1 pd7odr pd6odr pd5odr pd4odr pd3odr pd2odr pd1odr pd0odr pcpin * 1 pc7pin pc6pin pc5pin pc4pin pc3pin pc2pin pc1pin pc0pin pcddr * 1 pc7ddr pc6ddr pc5ddr pc4ddr pc3ddr pc2ddr pc1ddr pc0ddr pdpin * 1 pd7pin pd6pin pd5pin pd4pin pd3pin pd2pin pd1pin pd0pin pdddr * 1 pd7ddr pd6ddr pd5ddr pd4ddr pd3ddr pd2ddr pd1ddr pd0ddr port hicr2ibfie4ibfie3 idr_3 idr7 idr6 idr5 idr4 idr3 idr2 idr1 idr0 odr_3 odr7 odr6 odr5 odr4 odr3 odr2 odr1 odr0 str_3 dbu dbu dbu dbu c/ ' dbu ibf obf xbs rev. 2.0, 08/02, page 648 of 790 register abbreviation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module idr_4 idr7 idr6 idr5 idr4 idr3 idr2 idr1 idr0 odr_4 odr7 odr6 odr5 odr4 odr3 odr2 odr1 odr0 str_4 dbu dbu dbu dbu c/ ' dbu ibf obf xbs icxr_0 stopim hnds icdrf icdre alie alsl fnc1 fnc0 iic_0 icxr_1 stopim hnds icdrf icdre alie alsl fnc1 fnc0 iic_1 kbcrh_0 kbioe kclki kdi kbfsel kbie kbf per kbs kbcrl_0 kbe kclko kdo rxcr3 rxcr2 rxcr1 rxcr0 kbbr_0 kb7 kb6 kb5 kb4 kb3 kb2 kb1 kb0 keyboard buffer controller _0 kbcrh_1 kbioe kclki kdi kbfsel kbie kbf per kbs kbcrl_1 kbe kclko kdo rxcr3 rxcr2 rxcr1 rxcr0 kbbr_1 kb7 kb6 kb5 kb4 kb3 kb2 kb1 kb0 keyboard buffer controller _1 kbcrh_2 kbioe kclki kdi kbfsel kbie kbf per kbs kbcrl_2 kbe kclko kdo rxcr3 rxcr2 rxcr1 rxcr0 kbbr_2 kb7 kb6 kb5 kb4 kb3 kb2 kb1 kb0 keyboard buffer controller _2 kbcomp ire ircks2 ircks1 ircks0 kbade kbch2 kbch1 kbch0 irda/ expanded a/d ddcswr swe sw ie if clr3 clr2 clr1 clr0 iic_0 icra icra7 icra6 icra5 icra4 icra3 icra2 icra1 icra0 icrb icrb7 icrb6 icrb5 icrb4 icrb3 icrb2 icrb1 icrb0 icrc icrc7 icrc6 icrc5 icrc4 icrc3 icrc2 icrc1 icrc0 isr irq7f irq6f irq5f irq4f irq3f irq2f irq1f irq0f iscrh irq7scb irq7sca irq6scb irq6sca irq5scb irq5sca irq4scb irq4sca iscrl irq3scb irq3sca irq2scb irq2sca irq1scb irq1sca irq0scb irq0sca int dtcera dtcea7 dtcea6 dtcea5 dtcea4 dtcea3 dtcea2 dtcea1 dtcea0 dtcerb dtceb7 dtceb6 dtceb5 dtceb4 dtceb3 dtceb2 dtceb1 dtceb0 dtcerc dtcec7 dtcec6 dtcec5 dtcec4 dtcec3 dtcec2 dtcec1 dtcec0 dtcerd dtced7 dtced6 dtced5 dtced4 dtced3 dtced2 dtced1 dtced0 dtcere dtcee7 dtcee6 dtcee5 dtcee4 dtcee3 dtcee2 dtcee1 dtcee0 dtvecr swdte dtvec6 dtvec5 dtvec4 dtvec3 dtvec2 dtvec1 dtvec0 dtc abrkcrcmfbie bara a23 a22 a21 a20 a19 a18 a17 a16 barb a15 a14 a13 a12 a11 a10 a9 a8 int rev. 2.0, 08/02, page 649 of 790 register abbreviation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module barc a7a6a5a4a3a2a1 int flmcr1 fwe swe ev pv e p flmcr2fleresupsu flash pcsr pwckbpwckapwm ebr1 * 4 eb11eb10eb9eb8flash syscr2 kwul1 kwul0 p6pue sde cs4e cs3e hi12e system ebr2 eb7 eb6 eb5 eb4 eb3 eb2 eb1 eb0 flash sbycr ssby sts2 sts1 sts0 sck2 sck1 sck0 lpwrcr dton lson nesel excle mstpcrh mstp15 mstp14 mstp13 mstp12 mstp11 mstp10 mstp9 mstp8 mstpcrl mstp7 mstp6 mstp5 mstp4 mstp3 mstp2 mstp1 mstp0 system smr_1 c/ $ chr pe o/ ( stop mp cks1 cks0 sci_1 iccr_1 ice ieic mst trs acke bbsy iric scp iic_1 brr_1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sci_1 icsr_1 estp stop irtr aasx al aas adz ackb iic_1 scr_1 tie rie te re mpie teie cke1 cke0 tdr_1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ssr_1 tdre rdrf orer fer per tend mpb mpbt rdr_1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 scmr_1 sdir sinv smif sci_1 icdr_1 icdr7 icdr6 icdr5 icdr4 icdr3 icdr2 icdr1 icdr0 sarx_1 svax6 svax5 svax4 svax3 svax2 svax1 svax0 fsx icmr_1 mls wait cks2 cks1 cks0 bc2 bc1 bc0 sar_1 sva6 sva5 sva4 sva3 sva2 sva1 sva0 fs iic_1 tier iciae icibe icice icide ociae ocibe ovie tcsr icfa icfb icfc icfd ocfa ocfb ovf cclra frch bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 frcl bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ocrah bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ocrbh bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ocral bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ocrbl bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tcr iedga iedgb iedgc iedgd bufea bufeb cks1 cks0 frt rev. 2.0, 08/02, page 650 of 790 register abbreviation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module tocr icrdms ocrams icrs ocrs oea oeb olvla olvlb icrah bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ocrarh bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 icral bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ocrarl bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 icrbh bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ocrafh bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 icrbl bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ocrafl bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 icrch bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ocrdmh bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 icrcl bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ocrdml bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 icrdh bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 icrdl bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 frt smr_2 c/ $ chr pe o/ ( stop mp cks1 cks0 sci_2 dacr test pwme oeb oea os cks dadrah da13 da12 da11 da10 da9 da8 da7 da6 dadral da5 da4 da3 da2 da1 da0 cfs pwmx brr_2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 scr_2 tie rie te re mpie teie cke1 cke0 tdr_2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ssr_2 tdre rdrf orer fer per tend mpb mpbt rdr_2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 scmr_2sdirsinvsmif sci_2 dacnth uc7 uc6 uc5 uc4 uc3 uc2 uc1 uc0 dadrbh da13 da12 da11 da10 da9 da8 da7 da6 dacntl uc8 uc9 uc10 uc11 uc12 uc13 regs dadrbl da5 da4 da3 da2 da1 da0 cfs regs pwmx tcsr_0 ovf wt/ ,7 tme rst/ 10, cks2 cks1 cks0 tcnt_0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wdt_0 paodr pa7odr pa6odr pa5odr pa4odr pa3odr pa2odr pa1odr pa0odr papin pa7pin pa6pin pa5pin pa4pin pa3pin pa2pin pa1pin pa0pin port rev. 2.0, 08/02, page 651 of 790 register abbreviation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module paddr pa7ddr pa6ddr pa5ddr pa4ddr pa3ddr pa2ddr pa1ddr pa0ddr p1pcr p17pcr p16pcr p15pcr p14pcr p13pcr p12pcr p11pcr p10pcr p2pcr p27pcr p26pcr p25pcr p24pcr p23pcr p22pcr p21pcr p20pcr p3pcr p37pcr p36pcr p35pcr p34pcr p33pcr p32pcr p31pcr p30pcr p1ddr p17ddr p16ddr p15ddr p14ddr p13ddr p12ddr p11ddr p10ddr p2ddr p27ddr p26ddr p25ddr p24ddr p23ddr p22ddr p21ddr p20ddr p1dr p17dr p16dr p15dr p14dr p13dr p12dr p11dr p10dr p2dr p27dr p26dr p25dr p24dr p23dr p22dr p21dr p20dr p3ddr p37ddr p36ddr p35ddr p34ddr p33ddr p32ddr p31ddr p30ddr p4ddr p47ddr p46ddr p45ddr p44ddr p43ddr p42ddr p41ddr p40ddr p3dr p37dr p36dr p35dr p34dr p33dr p32dr p31dr p30dr p4dr p47dr p46dr p45dr p44dr p43dr p42dr p41dr p40dr p5ddr p52ddr p51ddr p50ddr p6ddr p67ddr p66ddr p65ddr p64ddr p63ddr p62ddr p61ddr p60ddr p5dr p52dr p51dr p50dr p6dr p67dr p66dr p65dr p64dr p63dr p62dr p61dr p60dr pbodr pb7odr pb6odr pb5odr pb4odr pb3odr pb2odr pb1odr pb0odr pbpin pb7pin pb6pin pb5pin pb4pin pb3pin pb2pin pb1pin pb0pin p8ddr p86ddr p85ddr p84ddr p83ddr p82ddr p81ddr p80ddr p7pin p77pin p76pin p75pin p74pin p73pin p72pin p71pin p70pin pbddr pb7ddr pb6ddr pb5ddr pb4ddr pb3ddr pb2ddr pb1ddr pb0ddr p8dr p86dr p85dr p84dr p83dr p82dr p81dr p80dr p9ddr p97ddr p96ddr p95ddr p94ddr p93ddr p92ddr p91ddr p90ddr p9dr p97dr p96dr p95dr p94dr p93dr p92dr p91dr p90dr port ier irq7e irq6e irq5e irq4e irq3e irq2e irq1e irq0e int stcr iics iicx1 iicx0 iice flshe icks1 icks0 syscr cs2e iose intm1 intm0 xrst nmieg hie rame mdcr expe mds1mds0 system bcr icis0 brstrm brsts1 brsts0 ios1 ios0 wscr abw ast wms1 wms0 wc1 wc0 bsc tcr_0 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 tcr_1 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 tcsr_0 cmfb cmfa ovf adte os3 os2 os1 os0 tmr_0, tmr_1 rev. 2.0, 08/02, page 652 of 790 register abbreviation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module tcsr_1 cmfb cmfa ovf os3 os2 os1 os0 tcora_0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tcora_1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tcorb_0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tcorb_1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tcnt_0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tcnt_1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tmr_0, tmr_1 pwoerb oe15 oe14 oe13 oe12 oe11 oe10 oe9 oe8 pwoera oe7 oe6 oe5 oe4 oe3 oe2 oe1 oe0 pwdprb os15 os14 os13 os12 os11 os10 os9 os8 pwdpra os7 os6 os5 os4 os3 os2 os1 os0 pwsl pwcke pwcks rs3 rs2 rs1 rs0 pwdr0C15 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pwm smr_0 c/ $ chr pe o/ ( stop mp cks1 cks0 sci_0 iccr_0 ice ieic mst trs acke bbsy iric scp iic_0 brr_0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sci_0 icsr_0 estp stop irtr aasx al aas adz ackb iic_0 scr_0 tie rie te re mpie teie cke1 cke0 tdr_0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ssr_0 tdre rdrf orer fer per tend mpb mpbt rdr_0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 scmr_0sdirsinvsmif sci_0 icdr_0 icdr7 icdr6 icdr5 icdr4 icdr3 icdr2 icdr1 icdr0 sarx_0 svax6 svax5 svax4 svax3 svax2 svax1 svax0 fsx icmr_0 mls wait cks2 cks1 cks0 bc2 bc1 bc0 sar_0 sva6 sva5 sva4 sva3 sva2 sva1 sva0 fs iic_0 addrah ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 addral ad1 ad0 addrbh ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 addrbl ad1 ad0 addrch ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 addrcl ad1 ad0 addrdh ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 a/d converter rev. 2.0, 08/02, page 653 of 790 register abbreviation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module addrdl ad1 ad0 adcsr adf adie adst scan cks ch2 ch1 ch0 adcr trgs1 trgs0 a/d converter tcsr_1 ovf wt/ ,7 tme pss rst/ 10, cks2 cks1 cks0 tcnt_1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wdt_1 hicr ibfie2 ibfie1 fga20e xbs tcr_x cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 tmr_x tcr_y cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 tmr_y kmimr kmimr7 kmimr6 kmimr5 kmimr4 kmimr3 kmimr2 kmimr1 kmimr0 int tcsr_x cmfb cmfa ovf icf os3 os2 os1 os0 tmr_x tcsr_y cmfb cmfa ovf icie os3 os2 os1 os0 tmr_y kmpcr kmimr7 kmimr6 kmimr5 kmimr4 kmimr3 kmimr2 kmimr1 kmimr0 port ticrr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tmr_x tcora_y bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tmr_y kmimra kmimr15 kmimr14 kmimr13 kmimr12 kmimr11 kmimr10 kmimr9 kmimr8 int ticrf bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tmr_x tcorb_y bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tmr_y idr_1 idr7 idr6 idr5 idr4 idr3 idr2 idr1 idr0 xbs tcnt_x bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tmr_x tcnt_y bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tmr_y odr_1 odr7 odr6 odr5 odr4 odr3 odr2 odr1 odr0 xbs tcorc bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tmr_x tisr istmr_y str_1 dbu17 dbu16 dbu15 dbu14 c/ ' 1 dbu12 ibf1 obf1 xbs tcora_x bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tcorb_x bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tmr_x dadr_0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dadr_1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dacr daoe1 daoe0 dae d/a converter idr_2 idr7 idr6 idr5 idr4 idr3 idr2 idr1 idr0 xbs tconri simod1 simod0 scone icst hfinv vfinv hiinv viinv timer connection odr_2 odr7 odr6 odr5 odr4 odr3 odr2 odr1 odr0 xbs rev. 2.0, 08/02, page 654 of 790 register abbreviation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module tconro hoe voe cloe cboe hoinv voinv cloinv cboinv timer connection str_2 dbu27 dbu26 dbu25 dbu24 c/ ' 2 dbu22 ibf2 obf2 xbs tconrs tmrx/y isgene homod1 homod0 vomod1 vomod0 clmod1 clmod0 sedgr vedg hedg cedg hfedg vfedg preqf ihi ivi timer connection notes: 1. can be used on the h8s/2160b and h8s/2161b. 2. when twre = 1 or selstr3 = 0 in ladr3l 3. when twre = 0 and selstr3 = 1 in ladr3l 4. all bits are reserved in the 64-kbyte flash memory version. the eb11 and eb10 bits are reserved in the 128-kbyte flash memory version. 5. not supported by the h8s/2148b. rev. 2.0, 08/02, page 655 of 790 27.3 register states in each operating mode register abbrevia- tion reset high-speed/ medium- speed watch sleep sub- active sub-sleep module stop software standby hardware standby module pgnocr * 1 initialized initialized penocr * 1 initialized initialized pfnocr * 1 initialized initialized pcnocr * 1 initialized initialized pdnocr * 1 initialized initialized port twr0mw twr0sw twr1 twr2 twr3 twr4 twr5 twr6 twr7 twr8 twr9 twr10 twr11 twr12 twr13 twr14 twr15 idr3 odr3 str3 initialized initialized ladr3h initialized initialized ladr3l initialized initialized sirqcr0 initialized initialized sirqcr1 initialized initialized idr1 odr1 lpc rev. 2.0, 08/02, page 656 of 790 register abbrevia- tion reset high-speed/ medium- speed watch sleep sub- active sub-sleep module stop software standby hardware standby module str1 initialized initialized idr2 odr2 str2 initialized initialized hisel initialized initialized hicr0 initialized initialized hicr1 initialized initialized hicr2 initialized initialized hicr3 lpc wuemrb * 2 initialized initialized int pgodr * 1 initialized initialized pgpin * 1 pgddr * 1 initialized initialized peodr * 1 initialized initialized pfodr * 1 initialized initialized pepin * 1 peddr * 1 initialized initialized pfpin * 1 pfddr * 1 initialized initialized pcodr * 1 initialized initialized pdodr * 1 initialized initialized pcpin * 1 pcddr * 1 initialized initialized pdpin * 1 pdddr * 1 initialized initialized port hicr2 initialized initialized idr_3 odr_3 str_3 initialized initialized idr_4 initialized odr_4 initialized str_4 initialized initialized xbs rev. 2.0, 08/02, page 657 of 790 register abbrevia- tion reset high-speed/ medium- speed watch sleep sub- active sub-sleep module stop software standby hardware standby module icxr_0 initialized initialized iic_0 icxr_1 initialized initialized iic_1 kbcrh_0 initialized initialized initialized initialized initialized initialized initialized kbcrl_0 initialized initialized initialized initialized initialized initialized initialized kbbr_0 initialized initialized initialized initialized initialized initialized initialized keyboard buffer controller_0 kbcrh_1 initialized initialized initialized initialized initialized initialized initialized kbcrl_1 initialized initialized initialized initialized initialized initialized initialized kbbr_1 initialized initialized initialized initialized initialized initialized initialized keyboard buffer controller_1 kbcrh_2 initialized initialized initialized initialized initialized initialized initialized kbcrl_2 initialized initialized initialized initialized initialized initialized initialized kbbr_2 initialized initialized initialized initialized initialized initialized initialized keyboard buffer controller_2 kbcomp initialized initialized irda/ a/d converter ddcswr initialized initialized iic_0 icra initialized initialized icrb initialized initialized icrc initialized initialized isr initialized initialized iscrh initialized initialized iscrl initialized initialized int dtcera initialized initialized dtcerb initialized initialized dtcerc initialized initialized dtcerd initialized initialized dtcere initialized initialized dtvecr initialized initialized dtc abrkcr initialized initialized bara initialized initialized barb initialized initialized barc initialized initialized int flmcr1 initialized initialized initialized initialized initialized initialized flmcr2 initialized initialized initialized initialized initialized initialized flash rev. 2.0, 08/02, page 658 of 790 register abbrevia- tion reset high-speed/ medium- speed watch sleep sub- active sub-sleep module stop software standby hardware standby module pcsr initialized initialized pwm ebr1 initialized initialized initialized initialized initialized initialized flash syscr2 initialized initialized system ebr2 initialized initialized initialized initialized initialized initialized flash sbycr initialized initialized lpwrcr initialized initialized mstpcrh initialized initialized mstpcrl initialized initialized system smr_1 initialized initialized initialized initialized initialized initialized initialized sci_1 iccr_1 initialized initialized iic_1 brr_1 initialized initialized initialized initialized initialized initialized initialized sci_1 icsr_1 initialized initialized iic_1 scr_1 initialized initialized initialized initialized initialized initialized initialized tdr_1 initialized initialized initialized initialized initialized initialized initialized ssr_1 initialized initialized initialized initialized initialized initialized initialized rdr_1 initialized initialized initialized initialized initialized initialized initialized scmr_1 initialized initialized initialized initialized initialized initialized initialized sci_1 icdr_1 sarx_1 initialized initialized icmr_1 initialized initialized sar_1 initialized initialized iic_1 tier initialized initialized tcsr initialized initialized frch initialized initialized frcl initialized initialized ocrah initialized initialized ocrbh initialized initialized ocral initialized initialized ocrbl initialized initialized tcr initialized initialized tocr initialized initialized icrah initialized initialized ocrarh initialized initialized frt rev. 2.0, 08/02, page 659 of 790 register abbrevia- tion reset high-speed/ medium- speed watch sleep sub- active sub-sleep module stop software standby hardware standby module icral initialized initialized ocrarl initialized initialized icrbh initialized initialized ocrafh initialized initialized icrbl initialized initialized ocrafl initialized initialized icrch initialized initialized ocrdmh initialized initialized icrcl initialized initialized ocrdml initialized initialized icrdh initialized initialized icrdl initialized initialized frt smr_2 initialized initialized initialized initialized initialized initialized initialized sci_2 dacr initialized initialized initialized initialized initialized initialized initialized dadrah initialized initialized initialized initialized initialized initialized initialized dadral initialized initialized initialized initialized initialized initialized initialized pwmx brr_2 initialized initialized initialized initialized initialized initialized initialized scr_2 initialized initialized initialized initialized initialized initialized initialized tdr_2 initialized initialized initialized initialized initialized initialized initialized ssr_2 initialized initialized initialized initialized initialized initialized initialized rdr_2 initialized initialized initialized initialized initialized initialized initialized scmr_2 initialized initialized sci_2 dacnth initialized initialized initialized initialized initialized initialized initialized dadrbh initialized initialized initialized initialized initialized initialized initialized dacntl initialized initialized initialized initialized initialized initialized initialized dadrbl initialized initialized initialized initialized initialized initialized initialized pwmx tcsr_0 initialized initialized tcnt_0 initialized initialized wdt_0 paodr initialized initialized papin paddr initialized initialized p1pcr initialized initialized p2pcr initialized initialized port rev. 2.0, 08/02, page 660 of 790 register abbrevia- tion reset high-speed/ medium- speed watch sleep sub- active sub-sleep module stop software standby hardware standby module p3pcr initialized initialized p1ddr initialized initialized p2ddr initialized initialized p1dr initialized initialized p2dr initialized initialized p3ddr initialized initialized p4ddr initialized initialized p3dr initialized initialized p4dr initialized initialized p5ddr initialized initialized p6ddr initialized initialized p5dr initialized initialized p6dr initialized initialized pbodr initialized initialized pbpin p8ddr initialized initialized p7pin pbddr initialized initialized p8dr initialized initialized p9ddr initialized initialized p9dr initialized initialized port ier initialized initialized int stcr initialized initialized syscr initialized initialized mdcr initialized initialized system bcr initialized initialized wscr initialized initialized bsc tcr_0 initialized initialized tcr_1 initialized initialized tcsr_0 initialized initialized tcsr_1 initialized initialized tcora_0 initialized initialized tcora_1 initialized initialized tmr_0, tmr_1 rev. 2.0, 08/02, page 661 of 790 register abbrevia- tion reset high-speed/ medium- speed watch sleep sub- active sub-sleep module stop software standby hardware standby module tcorb_0 initialized initialized tcorb_1 initialized initialized tcnt_0 initialized initialized tcnt_1 initialized initialized tmr_0, tmr_1 pwoerb initialized initialized pwoera initialized initialized pwdprb initialized initialized pwdpra initialized initialized pwsl initialized initialized initialized initialized initialized initialized initialized pwdr0 to pwdr15 initialized initialized initialized initialized initialized initialized initialized pwm smr_0 initialized initialized initialized initialized initialized initialized initialized sci_0 iccr_0 initialized initialized iic_0 brr_0 initialized initialized initialized initialized initialized initialized initialized sci_0 icsr_0 initialized initialized iic_0 scr _ 0 initialized initialized initialized initialized initialized initialized initialized tdr _ 0 initialized initialized initialized initialized initialized initialized initialized ssr _ 0 initialized initialized initialized initialized initialized initialized initialized rdr _ 0 initialized initialized initialized initialized initialized initialized initialized scmr _ 0 initialized initialized initialized initialized initialized initialized initialized sci_0 icdr _ 0 sarx _ 0 initialized initialized icmr _ 0 initialized initialized sar _ 0 initialized initialized iic_0 addrah initialized initialized initialized initialized initialized initialized initialized addral initialized initialized initialized initialized initialized initialized initialized addrbh initialized initialized initialized initialized initialized initialized initialized addrbl initialized initialized initialized initialized initialized initialized initialized addrch initialized initialized initialized initialized initialized initialized initialized addrcl initialized initialized initialized initialized initialized initialized initialized addrdh initialized initialized initialized initialized initialized initialized initialized addrdl initialized initialized initialized initialized initialized initialized initialized adcsr initialized initialized initialized initialized initialized initialized initialized a/d converter rev. 2.0, 08/02, page 662 of 790 register abbrevia- tion reset high-speed/ medium- speed watch sleep sub- active sub-sleep module stop software standby hardware standby module adcr initialized initialized initialized initialized initialized initialized initialized a/d converter tcsr_1 initialized initialized tcnt_1 initialized initialized wdt_1 hicr initialized initialized xbs tcr_x initialized initialized tmr_x tcr_y initialized initialized tmr_y kmimr initialized initialized int tcsr_x initialized initialized tmr_x tcsr_y initialized initialized tmr_y kmpcr initialized initialized port ticrr initialized initialized tmr_x tcora_y initialized initialized tmr_y kmimra initialized initialized int ticrf initialized initialized tmr_x tcorb_y initialized initialized tmr_y idr_1 xbs tcnt_x initialized initialized tmr_x tcnt_y initialized initialized tmr_y odr_1 xbs tcorc initialized initialized tmr_x tisr initialized initialized tmr_y str_1 initialized initialized xbs tcora_x initialized initialized tcorb_x initialized initialized tmr_x dadr0 initialized initialized dadr1 initialized initialized dacr initialized initialized d/a converter idr_2 xbs tconri initialized initialized timer connection odr_2 xbs rev. 2.0, 08/02, page 663 of 790 register abbrevia- tion reset high-speed/ medium- speed watch sleep sub- active sub-sleep module stop software standby hardware standby module tconro initialized initialized timer connection str_2 initialized initialized xbs tconrs initialized initialized sedgr initialized initialized timer connection notes: 1. can be used on the h8s/2160b and h8s/2161b. 2. not supported by the h8s/2148b. rev. 2.0, 08/02, page 664 of 790 27.4 register select conditions lower address register name h8s/2140b, h8s/2141b, h8s/2145b, h8s/2148b register select condition h8s/2160b, h8s2161b register select condition module name h'fe16 pgnocr h'fe18 penocr h'fe19 pfnocr h'fe1c pcnocr h'fe1d pdnocr no condition port twr0mw h'fe20 twr0sw h'fe21 twr1 h'fe22 twr2 h'fe23 twr3 h'fe24 twr4 h'fe25 twr5 h'fe26 twr6 h'fe27 twr7 h'fe28 twr8 h'fe29 twr9 h'fe2a twr10 h'fe2b twr11 h'fe2c twr12 h'fe2d twr13 h'fe2e twr14 h'fe2f twr15 mstp = 0, (hi12e = 0) * mstp = 0, (hi12e = 0) * lpc rev. 2.0, 08/02, page 665 of 790 lower address register name h8s/2140b, h8s/2141b, h8s/2145b, h8s/2148b register select condition h8s/2160b, h8s2161b register select condition module name h'fe30 idr3 h'fe31 odr3 h'fe32 str3 h'fe34 ladr3h h'fe35 ladr3l h'fe36 sirqcr0 h'fe37 sirqcr1 h'fe38 idr1 h'fe39 odr1 h'fe3a str1 h'fe3c idr2 h'fe3d odr2 h'fe3e str2 h'fe3f hisel h'fe40 hicr0 h'fe41 hicr1 h'fe42 hicr2 h'fe43 hicr3 mstp = 0, (hi12e = 0) * mstp = 0, (hi12e = 0) * lpc h'fe44 wuemrb no condition int h'fe46 pgodr h'fe47 pgpin (read) pgddr (write) h'fe48 peodr h'fe49 pfodr pepin (read) h'fe4a peddr (write) pfpin (read) h'fe4b pfddr (write) h'fe4c pcodr h'fe4d pdodr no condition port rev. 2.0, 08/02, page 666 of 790 lower address register name h8s/2140b, h8s/2141b, h8s/2145b, h8s/2148b register select condition h8s/2160b, h8s2161b register select condition module name pcpin (read) h'fe4e pcddr (write) pdpin (read) h'fe4f pdddr (write) no condition port h'fe80 hicr2 h'fe81 idr_3 h'fe82 odr_3 h'fe83 str_3 h'fe84 idr_4 h'fe85 odr_4 h'fe86 str_4 mstp2 = 0 mstp2 = 0 xbs h'fed4 icxr_0 iic_0 h'fed5 icxr_1 no condition no condition iic_1 h'fed8 kbcrh_0 h'fed9 kbcrl_0 h'feda kbbr_0 h'fedc kbcrh_1 h'fedd kbcrl_1 h'fede kbbr_1 h'fee0 kbcrh_2 h'fee1 kbcrl_2 h'fee2 kbbr_2 mstp2 = 0 mstp2 = 0 keyboard buffer controller h'fee4 kbcomp no condition no condition irda/expanded a/d h'fee6 ddcswr mstp4 = 0 mstp4 = 0 iic_0 h'fee8 icra h'fee9 icrb h'feea icrc h'feeb isr h'feec iscrh h'feed iscrl no condition no condition int rev. 2.0, 08/02, page 667 of 790 lower address register name h8s/2140b, h8s/2141b, h8s/2145b, h8s/2148b register select condition h8s/2160b, h8s2161b register select condition module name h'feee dtcera h'feef dtcerb h'fef0 dtcerc h'fef1 dtcerd h'fef2 dtcere h'fef3 dtvecr no condition no condition dtc h'fef4 abrkcr h'fef5 bara h'fef6 barb h'fef7 barc no condition no condition int h'ff80 flmcr1 h'ff81 flmcr2 flshe = 1 in stcr flshe = 1 in stcr flash pcsr flshe = 0 in stcr flshe = 0 in stcr pwm h'ff82 ebr1 flshe = 1 in stcr flshe = 1 in stcr flash syscr2 flshe = 0 in stcr flshe = 0 in stcr system h'ff83 ebr2 flshe = 1 in stcr flshe = 1 in stcr flash h'ff84 sbycr h'ff85 lpwrcr h'ff86 mstpcrh h'ff87 mstpcrl flshe = 0 in stcr flshe = 0 in stcr system smr_1 mstp6 = 0, iice = 0 in stcr mstp6 = 0,iice = 0 in stcr sci_1 h'ff88 iccr_1 mstp3 = 0, iice = 1 in stcr mstp3 = 0, iice = 1 in stcr iic_1 brr_1 mstp6 = 0, iice = 0 in stcr mstp6 = 0, iice = 0 in stcr sci_1 h'ff89 icsr_1 mstp3 = 0, iice = 1 in stcr mstp3 = 0, iice = 1 in stcr iic_1 rev. 2.0, 08/02, page 668 of 790 lower address register name h8s/2140b, h8s/2141b, h8s/2145b, h8s/2148b register select condition h8s/2160b, h8s2161b register select condition module name h'ff8a scr_1 h'ff8b tdr_1 h'ff8c ssr_1 h'ff8d rdr_1 mstp6 = 0 mstp6 = 0 scmr_1 mstp6 = 0, iice = 0 in stcr mstp6 = 0, iice = 0 in stcr sci_1 icdr_1 ice = 1 in iccr1 ice = 1 in iccr1 hff8e sarx_1 ice = 0 in iccr1 ice = 0 in iccr1 icmr_1 ice = 1 in iccr1 ice = 1 in iccr1 h'ff8f sar_1 mstp3 = 0, iice = 1 in stcr ice = 0 in iccr1 mstp3 = 0, iice = 1 in stcr ice = 0 in iccr1 iic_1 h'ff90 tier h'ff91 tcsr h'ff92 frch h'ff93 frcl mstp13 = 0 mstp13 = 0 frt ocrah ocrs = 0 in tocr ocrs = 0 in tocr h'ff94 ocrbh ocrs = 1 in tocr ocrs = 1 in tocr ocral ocrs = 0 in tocr ocrs = 0 in tocr h'ff95 ocrbl ocrs = 1 in tocr ocrs = 1 in tocr h'ff96 tcr h'ff97 tocr icrah icrs = 0 in tocr icrs = 0 in tocr h'ff98 ocrarh mstp13 = 0 icrs = 1 in tocr mstp13 = 0 icrs = 1 in tocr frt rev. 2.0, 08/02, page 669 of 790 lower address register name h8s/2140b, h8s/2141b, h8s/2145b, h8s/2148b register select condition h8s/2160b, h8s2161b register select condition module name icral icrs = 0 in tocr icrs = 0 in tocr h'ff99 ocrarl icrs = 1 in tocr icrs = 1 in tocr icrbh icrs = 0 in tocr icrs = 0 in tocr h'ff9a ocrafh icrs = 1 in tocr icrs = 1 in tocr icrbl icrs = 0 in tocr icrs = 0 in tocr h'ff9b ocrafl icrs = 1 in tocr icrs = 1 in tocr icrch icrs = 0 in tocr icrs = 0 in tocr h'ff9c ocrdmh icrs = 1 in tocr icrs = 1 in tocr icrcl icrs = 0 in tocr icrs = 0 in tocr h'ff9d ocrdml icrs = 1 in tocr icrs = 1 in tocr h'ff9e icrdh h'ff9f icrdl mstp13 = 0 mstp13 = 0 frt smr_2 mstp5 = 0, iice = 0 in stcr mstp5 = 0, iice = 0 in stcr sci_2 dadrah regs = 0 in dacnt/ dadrb regs = 0 in dacnt/ dadrb h'ffa0 dacr mstp11 = 0, iice = 1 in stcr regs = 1 in dacnt/ dadrb mstp11 = 0, iice = 1 in stcr regs = 1 in dacnt/ dadrb pwmx brr_2 mstp5 = 0, iice = 0 in stcr mstp5 = 0, iice = 0 in stcr sci_2 h'ffa1 dadral mstp11 = 0, iice = 1 in stcr regs = 0 in dacnt/ dadrb mstp11 = 0, iice = 1 in stcr regs = 0 in dacnt/ dadrb pwmx rev. 2.0, 08/02, page 670 of 790 lower address register name h8s/2140b, h8s/2141b, h8s/2145b, h8s/2148b register select condition h8s/2160b, h8s2161b register select condition module name h'ffa2 scr_2 h'ffa3 tdr_2 h'ffa4 ssr_2 h'ffa5 rdr_2 mstp5 = 0 mstp5 = 0 sci_2 scmr_2 mstp5 = 0, iice = 0 in stcr mstp5 = 0, iice = 0 in stcr sci_2 dadrbh regs = 0 in dacnt/ dadrb regs = 0 in dacnt/ dadrb h'ffa6 dacnth regs = 1 in dacnt/ dadrb regs = 1 in dacnt/ dadrb dadrbl regs = 0 in dacnt/ dadrb regs = 0 in dacnt/ dadrb h'ffa7 dacntl mstp11 = 0, iice = 1 in stcr regs = 1 in dacnt/ dadrb mstp11 = 0, iice = 1 in stcr regs = 1 in dacnt/ dadrb pwmx tcsr_0 h'ffa8 tcnt_0 (write) h'ffa9 tcnt_0 (read) no condition no condition wdt_0 h'ffaa paodr papin (read) h'ffab paddr (write) h'ffac p1pcr h'ffad p2pcr h'ffae p3pcr h'ffb0 p1ddr h'ffb1 p2ddr h'ffb2 p1dr h'ffb3 p2dr h'ffb4 p3ddr h'ffb5 p4ddr no condition no condition port rev. 2.0, 08/02, page 671 of 790 lower address register name h8s/2140b, h8s/2141b, h8s/2145b, h8s/2148b register select condition h8s/2160b, h8s2161b register select condition module name h'ffb6 p3dr h'ffb7 p4dr h'ffb8 p5ddr h'ffb9 p6ddr h'ffba p5dr h'ffbb p6dr h'ffbc pbodr p8ddr (write) h'ffbd pbpin (read) p7pin (read) h'ffbe pbddr (write) h'ffbf p8dr h'ffc0 p9ddr h'ffc1 p9dr no condition no condition port h'ffc2 ier no condition no condition int h'ffc3 stcr h'ffc4 syscr h'ffc5 mdcr no condition no condition system h'ffc6 bcr h'ffc7 wscr no condition no condition bsc h'ffc8 tcr_0 h'ffc9 tcr_1 h'ffca tcsr_0 h'ffcb tcsr_1 h'ffcc tcora_0 h'ffcd tcora_1 h'ffce tcorb_0 h'ffcf tcorb_1 h'ffd0 tcnt_0 h'ffd1 tcnt_1 mstp12 = 0 mstp12 = 0 tmr_0, tmr_1 rev. 2.0, 08/02, page 672 of 790 lower address register name h8s/2140b, h8s/2141b, h8s/2145b, h8s/2148b register select condition h8s/2160b, h8s2161b register select condition module name h'ffd2 pwoerb h'ffd3 pwoera h'ffd4 pwdprb h'ffd5 pwdpra no condition no condition pwm h'ffd6 pwsl h'ffd7 pwdr0 to pwdr15 mstp11 = 0 mstp11 = 0 pwm smr_0 mstp7 = 0, iice = 0 in stcr mstp7 = 0, iice = 0 in stcr sci_0 h'ffd8 iccr_0 mstp4 = 0, iice = 1 in stcr mstp4 = 0, iice = 1 in stcr iic_0 brr_0 mstp7 = 0, iice = 0 in stcr mstp7 = 0, iice = 0 in stcr sci_0 h'ffd9 icsr_0 mstp4 = 0, iice = 1 in stcr mstp4 = 0, iice = 1 in stcr iic_0 h'ffda scr_0 h'ffdb tdr_0 h'ffdc ssr_0 h'ffdd rdr_0 mstp7 = 0 mstp7 = 0 h'ffde scmr_0 mstp7 = 0, iice = 0 in stcr mstp7 = 0, iice = 0 in stcr sci_0 icdr_0 ice = 1 in iccr0 ice = 1 in iccr0 sarx_0 mstp4 = 0, iice = 1 in stcr ice = 0 in iccr0 mstp4 = 0, iice = 1 in stcr ice = 0 in iccr0 icmr_0 ice = 1 in iccr0 ice = 1 in iccr0 h'ffdf sar_0 mstp4 = 0, iice = 1 in stcr ice = 0 in iccr0 mstp4 = 0, iice = 1 in stcr ice = 0 in iccr0 iic_0 rev. 2.0, 08/02, page 673 of 790 lower address register name h8s/2140b, h8s/2141b, h8s/2145b, h8s/2148b register select condition h8s/2160b, h8s2161b register select condition module name h'ffe0 addrah h'ffe1 addral h'ffe2 addrbh h'ffe3 addrbl h'ffe4 addrch h'ffe5 addrcl h'ffe6 addrdh h'ffe7 addrdl h'ffe8 adcsr h'ffe9 adcr mstp9 = 0 mstp9 = 0 a/d tcsr_1 h'ffea tcnt_1 (write) h'ffeb tcnt_1 (read) no condition no condition wdt_1 h'fff0 hicr mstp2 = 0, hie = 1 in syscr mstp2 = 0, hie = 1 in syscr xbs tcr_x tmrx/y = 0 in tconrs tmrx/y = 0 in tconrs tmr_x tcr_y mstp8 = 0, hie = 0 in syscr tmrx/y = 1 in tconrs mstp8 = 0, hie = 0 in syscr tmrx/y = 1 in tconrs tmr_y kmimr mstp2 = 0, hie = 1 in syscr mstp2 = 0, hie = 1 in syscr int tcsr_x tmrx/y = 0 in tconrs tmrx/y = 0 in tconrs tmr_x h'fff1 tcsr_y mstp8 = 0, hie = 0 in syscr tmrx/y = 1 in tconrs mstp8 = 0, hie = 0 in syscr tmrx/y = 1 in tconrs tmr_y rev. 2.0, 08/02, page 674 of 790 lower address register name h8s/2140b, h8s/2141b, h8s/2145b, h8s/2148b register select condition h8s/2160b, h8s2161b register select condition module name kmpcr mstp2 = 0, hie = 1 in syscr mstp2 = 0, hie = 1 in syscr port ticrr tmrx/y = 0 in tconrs tmrx/y = 0 in tconrs tmr_x h'fff2 tcora_y mstp8 = 0, hie = 0 in syscr tmrx/y = 1 in tconrs mstp8 = 0, hie = 0 in syscr tmrx/y = 1 in tconrs tmr_y kmimra mstp2 = 0, hie = 1 in syscr mstp2 = 0, hie = 1 in syscr int ticrf tmrx/y = 0 in tconrs tmrx/y = 0 in tconrs tmr_x h'fff3 tcorb_y mstp8 = 0, hie = 0 in syscr tmrx/y = 1 in tconrs mstp8 = 0, hie = 0 in syscr tmrx/y = 1 in tconrs tmr_y idr_1 mstp2 = 0, hie = 1 in syscr mstp2 = 0, hie = 1 in syscr xbs tcnt_x tmrx/y = 0 in tconrs tmrx/y = 0 in tconrs tmr_x h'fff4 tcnt_y mstp8 = 0, hie = 0 in syscr tmrx/y = 1 in tconrs mstp8 = 0, hie = 0 in syscr tmrx/y = 1 in tconrs tmr_y odr_1 mstp2 = 0, hie = 1 in syscr mstp2 = 0, hie = 1 in syscr xbs tcorc tmrx/y = 0 in tconrs tmrx/y = 0 in tconrs tmr_x h'fff5 tisr mstp8 = 0, hie = 0 in syscr tmrx/y = 1 in tconrs mstp8 = 0, hie = 0 in syscr tmrx/y = 1 in tconrs tmr_y str_1 mstp2 = 0, hie = 1 in syscr mstp2 = 0, hie = 1 in syscr xbs h'fff6 tcora_x h'fff7 tcorb_x mstp8 = 0, hie = 0 in syscr tmrx/y = 0 in tconrs mstp8 = 0, hie = 0 in syscr tmrx/y = 0 in tconrs tmr_x rev. 2.0, 08/02, page 675 of 790 lower address register name h8s/2140b, h8s/2141b, h8s/2145b, h8s/2148b register select condition h8s/2160b, h8s2161b register select condition module name h'fff8 dadr0 h'fff9 dadr1 h'fffa dacr mstp10 = 0 mstp10 = 0 d/a idr_2 mstp2 = 0, hie = 1 in syscr mstp2 = 0, hie = 1 in syscr xbs h'fffc tconri mstp8 = 0, hie = 0 in syscr mstp8 = 0, hie = 0 in syscr timer connection odr_2 mstp2 = 0, hie = 1 in syscr mstp2 = 0, hie = 1 in syscr xbs h'fffd tconro mstp8 = 0, hie = 0 in syscr mstp8 = 0, hie = 0 in syscr timer connection str_2 mstp2 = 0, hie = 1 in syscr mstp2 = 0, hie = 1 in syscr xbs h'fffe tconrs h'ffff sedgr mstp8 = 0, hie = 0 in syscr mstp8 = 0, hie = 0 in syscr timer connection note: * although setting the xbs corresponding bits does not affected to the lpc operation, the hi12e bit in syscr2 must not be set to 1 to use the lpc according to the limitation depending on the program development tool (emulator) configuration. rev. 2.0, 08/02, page 676 of 790 rev. 2.0, 08/02, page 677 of 788 section 28 electrical characteristics 28.1 electrical characteristics of h8s/2140b, h8s/2141b, h8s/2160b, and h8s/2161b 28.1.1 absolute maximum ratings table 28.1 lists the absolute maximum ratings. table 28.1 absolute maximum ratings item symbol value unit power supply voltage v cc , v cl C0.3 to +4.3 v i/o buffer power supply voltage v cc b C0.3 to +7.0 v input voltage (except ports 6, 7, and a, p97, p86, p52, and p42) (ports c to f are added in the h8s/2160b and h8s/2161b.) v in C0.3 to v cc +0.3 v input voltage (cin input not selected for port 6) v in C0.3 to v cc +0.3 v input voltage (cin input not selected for port a) v in C0.3 to v cc b +0.3 v input voltage (cin input selected for port 6) v in C0.3 v to lower of voltages v cc + 0.3 and av cc + 0.3 v input voltage (cin input selected for port a) v in C0.3 v to lower of voltages v cc b + 0.3 and av cc + 0.3 v input voltage (p97, p86, p52, p42) (port g is added in the h8s/2160b and h8s/2161b.) v in C0.3 to +7.0 v input voltage (port 7) v in C0.3 to av cc + 0.3 v reference supply voltage av ref C0.3 to av cc + 0.3 v analog power supply voltage av cc C0.3 to +4.3 v analog input voltage v an C0.3 to av cc +0.3 v operating temperature t opr C20 to +75 c operating temperature (flash memory programming/erasing) t opr C20 to +75 c storage temperature t stg C55 to +125 c caution: permanent damage to the chip may result if absolute maximum ratings are exceeded. ensure so that the impressed voltage does not exceed 4.3 v for pins for which the maximum rating is determined by the voltage on the v cc , av cc , and v cl pins, or 7.0 v for pins for which the maximum rating is determined by v cc b. the v cc and v cl pins must be connected to the vcc power supply. rev. 2.0, 08/02, page 678 of 788 28.1.2 dc characteristics table 28.2 lists the dc characteristics. permitted output current values and bus drive characteristics are shown in tables 28.3 and 28.4, respectively. table 28.2 dc characteristics (1) conditions: v cc = 2.7 v to 3.6 v* 9 , v cc b = 2.7 v to 5.5 v, av cc * 1 = 2.7 v to 3.6 v, av ref * 1 = 2.7 v to av cc , v ss = av ss * 1 = 0 v, t a = C20 to +75c item symbol min typ max unit test conditions v t C v cc 0.2 v cc b 0.2 v t + v cc 0.7 v cc b 0.7 schmitt trigger input voltage p67 to p60 * 2 , * 6 , .,1 48 to .,1 ; * 7 , ,54 5 to ,54 3 * 3 , ,54 8 to ,54 6 v t + C v t C v cc 0.05 v cc b 0.05 v v t C v cc 0.2 v t + v cc 0.7 p67 to p60 (kwul = 00) v t + C v t C v cc 0.05 v t C v cc 0.3 v t + v cc 0.7 p67 to p60 (kwul = 01) v t + C v t C v cc 0.05 v t C v cc 0.4 v t + v cc 0.8 p67 to p60 (kwul = 10) v t + C v t C v cc 0.03 v t C v cc 0.45 v t + v cc 0.9 schmitt trigger input voltage (in level switching) * 6 p67 to p60 (kwul = 11) (1) * 8 v t + C v t C 0.05 v 5(6 , 67%< , nmi, md1, md0 v cc 0.9 v cc +0.3 extal v cc 0.7 v cc +0.3 input high voltage pa7 to pa0 * 7 (2) v ih v cc b 0.7 v cc b + 0.3 v rev. 2.0, 08/02, page 679 of 788 item symbol min typ max unit test conditions port 7 v cc 0.7 av cc + 0.3 p97, p86, p52, p42(port g is added in the h8s/2160b and h8s/2161b.) (2) v cc 0.7 5.5 input high voltage input pins except (1) and (2) above (ports c to f are added in the h8s/2160b and h8s/2161b.) v ih v cc 0.7 v cc + 0.3 v 5(6 , 67%< , md1, md0 (3) v il C0.3 v cc 0.1 v cc b 0.2 v cc b = 2.7 v to 4.0 v pa7 to pa0 C0.3 0.8 v cc b = 4.0 v to 5.5 v input low voltage nmi, extal, input pins except (1) and (3) above (ports c to g are added in the h8s/2160b and h8s/2161b.) C0.3 v cc 0.2 v v cc = 2.7 v to 3.6 v v cc C 0.5 v cc b C 0.5 vi oh = C200 a all output pins (except p97, p86, p52, and p42) * 4 , * 5 , * 8 (ports c to f are added in the h8s/2160b and h8s/2161b.) v cc C 1.0 v cc b C 1.0 vi oh = C1 ma, (v cc = 2.7 v to 3.6 v, v cc b = 2.7 v to 4.5 v) output high voltage p97, p86, p52, and p42 * 4 (port g is added in the h8s/2160b and h8s/2161b.) v oh 0.5 v i oh = C200 a rev. 2.0, 08/02, page 680 of 788 item symbol min typ max unit test conditions all output pins (except 5(62 ) * 5 (ports c to g are added in the h8s/2160b and h8s/2161b.) 0.4vi ol = 1.6 ma ports 1 to 3 1.0 v i ol = 5 ma output low voltage 5(62 v ol 0.4vi ol = 1.6 ma notes: 1. do not leave the av cc , av ref , and av ss pins open even if the a/d converter and d/a converter are not used. even if the a/d converter and d/a converter are not used, apply a value in the range 2.0 v to 3.6 v to av cc and av ref pins by connection to the power supply (v cc ), or some other method. ensure that av ref av cc . 2. p67 to p60 include peripheral module inputs multiplexed on those pins. 3. ,54 5 includes the $'75* signal multiplexed on that pin. 4. p52/sck0/scl0, p97/sda0, p86/sck1/scl1, p42/sck2/sda1, and port g are nmos push-pull outputs. when the scl0, sda0, scl1, or sda1 (ice = 1) pin is used as an output, it is nmos open-drain output. therefore, an external pull-up resistor must be connected in order to output high level. p52/sck0, p97, p86/sck1, p42/sck2 (ice = 0), and port g high levels are driven by nmos. an external pull-up resistor is necessary to provide high-level output from sck0, sck1, and sck2. 5. when iics = 0, ice = 0, and kbioe = 0. low-level output when the bus drive function is selected is determined separately. 6. the upper limit of the port 6 applied voltage is v cc + 0.3 v when cin input is not selected, and the lower of v cc + 0.3 v and av cc + 0.3 v when cin input is selected. when a pin is in output mode, the output voltage is equivalent to the applied voltage. 7. the upper limit of the port a applied voltage is v cc b + 0.3 v when cin input is not selected, and the lower of v cc b + 0.3 v and av cc + 0.3 v when cin input is selected. when a pin is in output mode, the output voltage is equivalent to the applied voltage. 8. the port a characteristics depend on v cc b, and the other pins characteristics depend on v cc . 9. for flash memory programming/erasure, the applicable range is v cc = 3.0 v to 3.6 v. rev. 2.0, 08/02, page 681 of 788 table 28.2 dc characteristics (2) conditions: v cc = 2.7 v to 3.6 v* 5 , v cc b = 2.7 v to 5.5 v, av cc * 1 = 2.7 v to 3.6 v, av ref * 1 = 2.7 v to av cc , v ss = av ss * 1 = 0 v, t a = C20 to +75c item symbol min typ max unit test conditions 5(6 10.0 67%< , nmi, md1, md0 1.0 v in = 0.5 to v cc C 0.5 v input leakage current port 7 ? i in ? 1.0 a v in = 0.5 to av cc C 0.5 v three-state leakage current (off state) ports 1 to 6, 8, 9, a * 4 , and b (ports c to g are added in the h8s/2160b and h8s/2161b.) ? i tsi ? 1.0av in = 0.5 to v cc C 0.5 v, v in = 0.5 to v cc b C 0.5 v ports 1 to 3 5 150 ports 6 (p6pue = 0) and b (ports c to f are added in the h8s/2160b and h8s/2161b.) 30 300 ports a * 4 30 600 input pull-up mos current port 6 (p6pue = 1) Ci p 3 100 a v in = 0 v, v cc = 2.7 v to 3.6 v v cc b = 2.7 v to 5.5 v 5(6 80 pf nmi 50 pf p52, p97, p42, p86, pa7 to pa2 (4) 20 pf input capacitance input pins except (4) above (ports c to g are added in the h8s/2160b and h8s/2161b.) c in 15 pf v in = 0 v, f = 1 mhz, t a = 25c normal operation 30 40 ma f = 10 mhz sleep mode 20 32 ma f = 10 mhz 15.0 t a 50c current dissipation * 2 standby mode * 3 i cc 20.0 a 50c < t a rev. 2.0, 08/02, page 682 of 788 item symbol min typ max unit test conditions during a/d, d/a conversion 1.22.0ma analog power supply current idle al cc 0.01 5.0 a av cc = 2.0 v to 3.6 v during a/d conversion 0.5 1.0 during a/d, d/a conversion 2.05.0 ma reference power supply current idle al ref 0.01 5.0 a av ref = 2.0 v to av cc 2.7 3.6 operating analog power supply voltage * 1 av cc 2.0 3.6 v idle/not used ram standby voltage v ram 2.0 v notes: 1. do not leave the av cc , av ref , and av ss pins open even if the a/d converter and d/a converter are not used. even if the a/d converter and d/a converter are not used, apply a value in the range 2.0 v to 3.6 v to av cc and av ref pins by connection to the power supply (v cc ), or some other method. ensure that av ref av cc . 2. current dissipation values are for v ih min = v cc C 0.2 v, v cc b C 0.2 v, and v il max = 0.2 v with all output pins unloaded and the on-chip pull-up moss in the off state. 3. the values are for v ram v cc < 2.7 v, v ih min = v cc C 0.2 v, v cc b C 0.2 v, and v il max = 0.2 v. 4. the port a characteristics depend on v cc b, and the other pins characteristics depend on v cc . 5. for flash memory programming/erasure, the applicable range is v cc = 3.0 v to 3.6 v. rev. 2.0, 08/02, page 683 of 788 table 28.2 dc characteristics (3) when lpc function is used conditions: v cc = 3.0 v to 3.6 v, v cc b = 2.7 v to 5.5 v, av cc * = 2.7 v to 3.6 v, av ref * = 2.7 v to av cc , v ss = av ss * 1 = 0 v, t a = C20 to +75c item symbol min max unit test conditions input high voltage p37 to p30, p83 to p80, pb1, pb0 v ih v cc 0.5 v input low voltage p37 to p30, p83 to p80, pb1, pb0 v il v cc 0.3 v output high voltage p37, p33 to p30, p82 to p80, pb1, pb0 v oh v cc 0.9 v i oh = C0.5 ma output low voltage p37, p33 to p30, p82 to p80, pb1, pb0 v ol v cc 0.1 v i ol = 1.5 ma note: * do not leave the av cc , av ref , and av ss pins open even if the a/d converter and d/a converter are not used. even if the a/d converter and d/a converter are not used, apply a value in the range 2.0 v to 3.6 v to av cc and av ref pins by connection to the power supply (v cc ), or some other method. ensure that av ref av cc . rev. 2.0, 08/02, page 684 of 788 table 28.3 permissible output currents conditions: v cc = 2.7 v to 3.6 v, v cc b = 2.7 v to 5.5 v, v ss = 0 v, t a = C20 to +75c item symbol min typ max unit scl1, scl0, sda1, sda0, ps2ac to ps2cc, ps2ad to ps2cd, pa7 to pa4 (bus drive function selected) 10 ports 1, 2, 3 2 5(62 1 permissible output low current (per pin) other output pins i ol 1 ma total of ports 1, 2, and 3 40 permissible output low current (total) total of all output pins, including the above ? i ol 60 ma permissible output high current (per pin) all output pins Ci oh 2 ma permissible output high current (total) total of all output pins ? Ci oh 30ma notes: 1. to protect chip reliability, do not exceed the output current values in table 28.3. 2. when driving a darlington pair or led, always insert a current-limiting resistor in the output line, as show in figures 28.1 and 28.2. 2 k w this lsi port darlington pair figure 28.1 darlington pair drive circuit (example) rev. 2.0, 08/02, page 685 of 788 600 w this lsi ports 1 to 3 led figure 28.2 led drive circuit (example) table 28.4 bus drive characteristics conditions: v cc = 2.7 v to 3.6 v, v ss = 0 v, ta = C20 to +75c applicable pins: scl1, scl0, sda1, sda0 (bus drive function selected) item symbol min typ max unit test conditions v t C v cc 0.3 v cc = 2.7 v to 3.6 v v t + v cc 0.7 v cc = 2.7 v to 3.6 v schmitt trigger input voltage v t + C v t C v cc 0.05 v v cc = 2.7 v to 3.6 v input high voltage v ih v cc 0.7 5.5 v v cc = 2.7 v to 3.6 v input low voltage v il C0.5 v cc 0.3 v cc = 2.7 v to 3.6 v v ol 0.5vi ol = 8 ma output low voltage 0.4 i ol = 3 ma input capacitance c in 20 pf v in = 0 v, f = 1 mhz, t a = 25c three-state leakage current (off state) | i tsi | 1.0 a v in = 0.5 to v cc C 0.5 v scl, sda output fall time t of 20 + 0.1cb 250 ns v cc = 2.7 v to 3.6 v rev. 2.0, 08/02, page 686 of 788 conditions: v cc = 2.7 v to 3.6 v, v cc b = 2.7 v to 5.5 v, v ss = 0 v, ta = C20 to +75c applicable pins: ps2ac, ps2ad, ps2bc, ps2bd, ps2cc, ps2cd, pa7 to pa4 (bus drive function selected) item symbol min typ max unit test conditions 0.8 i ol = 16 ma, v cc b = 4.5 v to 5.5 v 0.5 i ol = 8 ma output low voltage v ol 0.4 v i ol = 3 ma 28.1.3 ac characteristics figure 28.3 shows the test conditions for the ac characteristics. c chip output pin r h r l c = 30 pf: all output ports r l = 2.4 k w r h = 12 k w i/o timing test levels ? low level: 0.8 v ? high level: 2.0 v v cc figure 28.3 output load circuit rev. 2.0, 08/02, page 687 of 788 clock timing: table 28.5 shows the clock timing. the clock timing specified here covers clock (?) output and clock pulse generator (crystal) and external clock input (extal pin) oscillation settling times. for details on external clock input (extal pin and excl pin) timing, see section 25, clock pulse generator. table 28.5 clock timing condition: v cc = 2.7 v to 3.6 v, v cc b = 2.7 v to 5.5 v, v ss = 0 v, ? = 2 mhz to maximum operating frequency, t a = C20 to +75c condition 10 mhz item symbol min max unit reference clock cycle time t cyc 100 500 ns figure 28.6 clock high pulse width t ch 30 ns clock low pulse width t cl 30 ns clock rise time t cr 20ns clock fall time t cf 20ns figure 28.6 oscillation settling time at reset (crystal) t osc1 20 ms oscillation settling time in software standby (crystal) t osc2 8ms external clock output stabilization delay time t dext 500 s figure 28.7 figure 28.8 rev. 2.0, 08/02, page 688 of 788 control signal timing: table 28.6 shows the control signal timing. the only external interrupts that can operate on the subclock (? = 32.768 khz) are nmi and irq0, 1, 2, 6, and 7. table 28.6 control signal timing conditions: v cc = 2.7 v to 3.6 v, v cc b = 2.7 v to 5.5 v, v ss = 0 v, ? = 32.768 khz, 2 mhz to maximum operating frequency, t a = C20 to +75c condition 10 mhz item symbol min max unit test conditions 5(6 setup time t ress 300 ns 5(6 pulse width t resw 20 t cyc figure 28.9 nmi setup time (nmi) t nmis 250 ns nmi hold time (nmi) t nmih 10 ns nmi pulse width (exiting software standby mode) t nmiw 200 ns irq setup time ( ,54 : to ,54 3 )t irqs 250 ns irq hold time( ,54 : to ,54 3 )t irqh 10 ns irq pulse width ( ,54 : , ,54 9 , ,54 5 to ,54 3 ) (exiting software standby mode) t irqw 200 ns figure 28.10 rev. 2.0, 08/02, page 689 of 788 bus timing: table 28.7 shows the bus timing. operation in external expansion mode is not guaranteed when operating on the subclock (? = 32.768 khz). table 28.7 bus timing (1) (normal mode) conditions: v cc = 2.7 v to 3.6 v, v cc b = 2.7 v to 5.5 v, v ss = 0 v, ? = 2 mhz to maximum operating frequency, t a = C20 to +75c condition 10 mhz item symbol min max unit test conditions address delay time t ad 40ns address setup time t as 0.5 t cyc C 30 ns address hold time t ah 0.5 t cyc C 20 ns &6 delay time ( ,26 )t csd 40ns $6 delay time t asd 60ns 5' delay time 1 t rsd1 60ns 5' delay time 2 t rsd2 60ns read data setup time t rds 35 ns read data hold time t rdh 0ns read data access time 1 t acc1 1.0 t cyc C 60 ns read data access time 2 t acc2 1.5 t cyc C 50 ns read data access time 3 t acc3 2.0 t cyc C 60 ns read data access time 4 t acc4 2.5 t cyc C 50 ns read data access time 5 t acc5 3.0 t cyc C 60 ns +:5 , /:5 delay time 1 t wrd1 60ns +:5 , /:5 delay time 2 t wrd2 60ns +:5 , /:5 pulse width 1 t wsw1 1.0 t cyc C 40 ns +:5 , /:5 pulse width 2 t wsw2 1.5 t cyc C 40 ns write data delay time t wdd 60ns write data setup time t wds 0ns write data hold time t wdh 20 ns :$,7 setup time t wts 60 ns :$,7 hold time t wth 10 ns figures 28.11 to 28.15 rev. 2.0, 08/02, page 690 of 788 table 28.7 bus timing (2) (advanced mode) conditions: v cc = 2.7 v to 3.6 v, v cc b = 2.7 v to 5.5 v, v ss = 0 v, ? = 2 mhz to maximum operating frequency, t a = C20 to +75c condition 10 mhz item symbol min max unit test conditions address delay time t ad 60ns address setup time t as 0.5 t cyc C 30 ns address hold time t ah 0.5 t cyc C 20 ns &6 delay time ( ,26 )t csd 60ns $6 delay time t asd 60ns 5' delay time 1 t rsd1 60ns 5' delay time 2 t rsd2 60ns read data setup time t rds 35 ns read data hold time t rdh 0ns read data access time 1 t acc1 1.0 t cyc C 80 ns read data access time 2 t acc2 1.5 t cyc C 50 ns read data access time 3 t acc3 2.0 t cyc C 80 ns read data access time 4 t acc4 2.5 t cyc C 50 ns read data access time 5 t acc5 3.0 t cyc C 80 ns +:5 , /:5 delay time 1 t wrd1 60ns +:5 , /:5 delay time 2 t wrd2 60ns +:5 , /:5 pulse width 1 t wsw1 1.0 t cyc C 40 ns +:5 , /:5 pulse width 2 t wsw2 1.5 t cyc C 40 ns write data delay time t wdd 60ns write data setup time t wds 0ns write data hold time t wdh 20 ns :$,7 setup time t wts 60 ns :$,7 hold time t wth 10 ns figures 28.11 to 28.15 rev. 2.0, 08/02, page 691 of 788 timing of on-chip peripheral modules: tables 28.8 to 28.11 show the on-chip peripheral module timing. the only on-chip peripheral modules that can operate in subclock operation (? = 32.768 khz) are the i/o ports, external interrupts (nmi and irq0, 1, 2, 6, and 7), the watchdog timer, and the 8-bit timer (channels 0 and 1). table 28.8 timing of on-chip peripheral modules (1) conditions: v cc = 2.7 v to 3.6 v, v cc b = 2.7 v to 5.5 v, v ss = 0 v, ? = 32.768 khz * , 2 mhz to maximum operating frequency, t a = C20 to +75c condition 10 mhz item symbol min max unit test conditions output data delay time t pwd 100 input data setup time t prs 50 i/o ports input data hold time t prh 50 ns figure 28.16 timer output delay time t ftod 100 timer input setup time t ftis 50 figure 28.17 timer clock input setup time t ftcs 50 ns single edge t ftcwh 1.5 frt timer clock pulse width both edges t ftcwl 2.5 t cyc figure 28.18 timer output delay time t tmod 100 figure 28.19 timer reset input setup time t tmrs 50 figure 28.21 timer clock input setup time t tmcs 50 ns single edge t tmcwh 1.5 tmr timer clock pulse width both edges t tmcwl 2.5 t cyc figure 28.20 pwm, pwmx pulse output delay time t pwod 100 ns figure 28.22 asynchronous t scyc 4 input clock cycle synchronous 6 t cyc input clock pulse width t sckw 0.4 0.6 t scyc input clock rise time t sckr 1.5 sci input clock fall time t sckf 1.5 t cyc figure 28.23 rev. 2.0, 08/02, page 692 of 788 condition 10 mhz item symbol min max unit test conditions transmit data delay time (synchronous) t txd 100 ns receive data setup time (synchronous) t rxs 100 ns sci receive data hold time (synchronous) t rxh 100 ns figure 28.24 a/d converter trigger input setup time t trgs 50 ns figure 28.25 5(62 output delay time t resd 200 ns wdt 5(62 output pulse width t resow 132 t cyc figure 28.26 note: * only peripheral modules that can be used in subclock operation table 28.8 timing of on-chip peripheral modules (2) condition: v cc = 2.7 v to 3.6 v, v cc b = 2.7 v to 5.5 v, v ss = 0 v, ? = 2 mhz to maximum operating frequency, t a = C20 to +75c condition 10 mhz item symbol min max unit test conditions &6 /ha0 setup time t har 10 ns &6 /ha0 hold time t hra 10 ns ,25 pulse width t hrpw 220 ns hdb delay time t hrd 200 ns hdb hold time t hrf 040ns xbs read cycle hirq delay time t hirq 200 ns &6 /ha0 setup time t haw 10 ns &6 /ha0 hold time t hwa 10 ns ,2: pulse width t hwpw 100 ns fast a20 gate not used 50 ns hdb setup time fast a20 gate used t hdw 85 ns hdb hold time t hwd 25 ns xbs write cycle ga20 delay time t hga 180 ns figure 28.27 rev. 2.0, 08/02, page 693 of 788 table 28.9 keyboard buffer controller timing conditions: v cc = 2.7 v to 3.6 v, v cc b = 2.7 v to 5.5 v, v ss = 0 v, ? = 2 mhz to maximum operating frequency, t a = C20 to +75c ratings item symbol min typ max unit test conditions notes kclk, kd output fall time t kbf 20 + 0.1cb 250 ns kclk, kd input data hold time t kbih 150 ns kclk, kd input data setup time t kbis 150 ns kclk, kd output delay time t kbod 450 ns kclk, kd capacitive load c b 400 pf figure 28.28 table 28.10 i 2 c bus timing conditions: v cc = 2.7 v to 3.6 v, v ss = 0 v, ? = 5 mhz to maximum operating frequency, t a = C20 to +75c ratings item symbol min typ max unit test conditions notes scl input cycle time t scl 12 t cyc scl input high pulse width t sclh 3t cyc scl input low pulse width t scll 5t cyc scl, sda input rise time t sr 7.5 * t cyc scl, sda input fall time t sf 300 ns scl, sda input spike pulse elimination time t sp 1 t cyc sda input bus free time t buf 5t cyc start condition input hold time t stah 3t cyc retransmission start condition input setup time t stas 3t cyc stop condition input setup time t stos 3t cyc data input setup time t sdas 0.5 t cyc data input hold time t sdah 0ns scl, sda capacitive load c b 400 pf figure 28.29 note: * 17.5 t cyc can be set according to the clock selected for use by the i 2 c module. for details, see section 16.6, usage notes. rev. 2.0, 08/02, page 694 of 788 table 28.11 lpc module timing conditions: v cc = 3.0 v to 3.6 v, v ss = 0 v, ? = 2 mhz to maximum operating frequency, t a = C20 to +75c item symbol min typ max unit test conditions input clock cycle t lcyc 30 input clock pulse width (h) t lckh 11 input clock pulse width (l) t lckl 11 transmit signal delay time t txd 211 transmit signal floating delay time t off 28 receive signal setup time t rxs 7 lpc receive signal hold time t rxh 0 ns figure 28.30 28.1.4 a/d conversion characteristics tables 28.12 and 28.13 list the a/d conversion characteristics. table 28.12 a/d conversion characteristics (an7 to an0 input: 134/266-state conversion) conditions: v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, av ref = 2.7 v to av cc , v cc b = 2.7 v to 5.5 v, v ss = av ss = 0 v, ? = 2 mhz to maximum operating frequency, t a = C20 to +75c condition 10 mhz item min typ max unit resolution 10 bits conversion time 13.4 s analog input capacitance 20 pf permissible signal-source impedance 5 k w nonlinearity error 7.0 lsb offset error 7.5 lsb full-scale error 7.5 lsb quantization error 0.5 lsb absolute accuracy 8.0 lsb rev. 2.0, 08/02, page 695 of 788 table 28.13 a/d conversion characteristics (cin15 to cin0 input: 134/266-state conversion) conditions: v cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, av ref = 3.0 v to av cc , v cc b = 3.0 v to 5.5 v, v ss = av ss = 0 v, ? = 2 mhz to maximum operating frequency, t a = C20 to +75c condition 10 mhz item min typ max unit resolution 10 bits conversion time 13.4 s analog input capacitance 20 pf permissible signal-source impedance 5 k w nonlinearity error 11.0 lsb offset error 11.5 lsb full-scale error 11.5 lsb quantization error 0.5 lsb absolute accuracy 12.0 lsb 28.1.5 d/a conversion characteristics table 28.14 lists the d/a conversion characteristics. table 28.14 d/a conversion characteristics conditions: v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, av ref = 2.7 v to av cc , v cc b = 2.7 v to 5.5 v, v ss = av ss = 0 v, ? = 2 mhz to maximum operating frequency, t a = C20 to +75c condition 10 mhz item min typ max unit resolution 8 bits conversion time with 20 pf load capacitance 10 s with 2 m w load resistance 2.0 3.0 absolute accuracy with 4 m w load resistance 2.0 lsb rev. 2.0, 08/02, page 696 of 788 28.1.6 flash memory characteristics table 28.15 shows the flash memory characteristics. table 28.15 flash memory characteristics conditions: v cc = 3.0 v to 3.6 v, v ss = 0 v, t a = C20 to +75c item symbol min typ max unit test condition programming time * 1 , * 2 , * 4 t p 10 200 ms/ 128 bytes erase time * 1 , * 3 , * 6 t e 100 1200 ms/ block reprogramming count n wec 100 times wait time after swe-bit setting * 1 x1s wait time after psu-bit setting * 1 y50s z1 28 30 32 s 1 n 6 z2 198 200 202 s 7 n 1000 wait time after p-bit setting * 1 , * 4 z3 8 10 12 s additional write wait time after p-bit clear * 1 a 5s wait time after psu-bit clear * 1 b 5s wait time after pv-bit setting * 1 g 4s wait time after dummy write * 1 e 2s wait time after pv-bit clear * 1 h 2s wait time after swe-bit clear * 1 q 100 s programming maximum programming count * 1 , * 4 , * 5 n 1000 times rev. 2.0, 08/02, page 697 of 788 item symbol min typ max unit test conditions wait time after swe-bit setting * 1 x1s wait time after esu-bit setting * 1 y 100 s wait time after e-bit setting * 1 , * 6 z 10 100 ms wait time after e-bit clear * 1 a 10 s wait time after esu-bit clear * 1 b 10 s wait time after ev-bit setting * 1 g 20 s wait time after dummy write * 1 e 2s wait time after ev-bit clear * 1 h 4s wait time after swe-bit clear * 1 q 100 s erase maximum erase count * 1 , * 6 , * 7 n 120 times notes: 1. set the times according to the program/erase algorithms. 2. programming time per 128 bytes (shows the total period for which the p-bit in flmcr1 is set. it does not include the programming verification time.) 3. block erase time (shows the total period for which the e-bit in flmcr1 is set. it does not include the erase verification time.) 4. maximum programming time (t p (max)) t p (max) = (wait time after p-bit setting (z1) + (z3)) 6 + wait time after p-bit setting (z2) ((n) C 6) 5. the maximun number of writes (n) should be set according to the actual set value of z1, z2 and z3 to allow programming within the maximum programming time (t p (max)). the wait time after p-bit setting (z1, z2, and z3) should be alternated according to the number of writes (n) as follows: 1 n 6 z1 = 30s, z3 = 10s 7 n 1000 z2 = 200s 6. maximum erase time (t e (max)) t e (max) = wait time after e-bit setting (z) maximum erase count (n) 7. the maximum number of erases (n) should be set according to the actual set value of z to allow erasing within the maximum erase time (t e (max)). rev. 2.0, 08/02, page 698 of 788 28.1.7 usage note the method of connecting an external capacitor is shown in figure 28.4. connect the system power supply to the vcl pin together with the vcc pins. vcl vss 0.01 f 10 f bypass capacitor vcc power supply < vcc = 2.7 v to 3.6 v > connect the vcc power supply to the chip's vcl pin in the same way as the vcc pins. it is recommended that a bypass capacitor be connected to the power supply pins. (values are reference values.) figure 28.4 connection of vcl capacitor rev. 2.0, 08/02, page 699 of 788 28.2 electrical characteristics of h8s/2145b and h8s/2148b 28.2.1 absolute maximum ratings table 28.16 lists the absolute maximum ratings. table 28.16 absolute maximum ratings item symbol value unit power supply voltage * 1 v cc C0.3 to +7.0 v i/o buffer power supply voltage (power supply for port a) v cc b C0.3 to +7.0 v power supply voltage (3-v version product) * 1 v cc C0.3 to +4.3 v power supply voltage (vcl pin) * 2 v cl C0.3 to +4.3 v input voltage (except ports 6, 7, and a, p97, p86, p52, p42) v in C0.3 to v cc +0.3 v input voltage (cin input not selected for port 6) v in C0.3 to v cc +0.3 v input voltage (cin input not selected for port a) v in C0.3 to v cc b +0.3 v input voltage (cin input selected for port 6) v in C0.3 v to lower of voltages v cc + 0.3 and av cc + 0.3 v input voltage (cin input selected for port a) v in C0.3 v to lower of voltages v cc b + 0.3 and av cc + 0.3 v input voltage (p97, p86, p52, p42) v in C0.3 to +7.0 v input voltage (port 7) v in C0.3 to av cc + 0.3 v reference supply voltage av ref C0.3 to av cc + 0.3 v analog power supply voltage av cc C0.3 to +7.0 v analog power supply voltage (3-v version product) av cc C0.3 to +4.3 v analog input voltage v an C0.3 to av cc +0.3 v normal specification product: C20 to +75 operating temperature t opr wide range temperature specification product: C40 to +85 c normal specification product: C20 to +75 operating temperature (flash memory programming/erasing) t opr wide range temperature specification product: C40 to +85 c storage temperature t stg C55 to +125 c caution: permanent damage to the chip may result if absolute maximum ratings are exceeded. rev. 2.0, 08/02, page 700 of 788 ensure that for 5-v/4-v version products, the input pin voltage does not exceed 7.0 v, and for 3-v version products, all the input voltage except for port a does not exceed 4.3 v. notes: 1. voltage applied to the vcc1 pin. since both the vcc1 pin and vcl pin are connected to the vcc power supply on low-power voltage (3-v) products, vcl ratings should not be exceeded. 2. power supply voltage pin used for operation within the chip. do not apply power supply voltage to the vcl pin on 5-v/4-v products. be sure to insert an external capacitor between the vcl pin and gnd to regulate the internal voltage. rev. 2.0, 08/02, page 701 of 788 28.2.2 dc characteristics table 28.17 lists the dc characteristics. permitted output current values and bus drive characteristics are shown in tables 28.18 and 28.19, respectively. table 28.17 dc characteristics (1) conditions: v cc = 5.0 v 10 %, v cc b = 5.0 v 10 %, av cc * 1 = 5.0 v 10 %, av ref * 1 = 4.5 v to av cc , v ss = av ss * 1 = 0 v, t a = C20 to +75c (normal specification product), t a = C40 to +85c (wide range temperature specification product) item symbol min typ max unit test conditions p67 to p60 (kwul = 00) * 2 , * 6 , .,1 48 to .,1 ; * 7 , * 8 v t C 1.0 v t + v cc 0.7 v cc b 0.7 schmitt trigger input voltage ,54 5 to ,54 3 * 3 , ,54 8 to ,54 6 v t + C v t C 0.4 v v t C v cc 0.3 v t + v cc 0.7 p67 to p60 (kwul = 01) v t + C v t C v cc 0.05 v t C v cc 0.4 v t + v cc 0.8 p67 to p60 (kwul = 10) v t + C v t C v cc 0.03 v t C v cc 0.45 v t + v cc 0.9 schmitt trigger input voltage (in level switching) * 6 p67 to p60 (kwul = 11) (1) v t + C v t C 0.05 v 5(6 , 67%< , nmi, md1, md0 v cc C 0.7 v cc + 0.3 extal v cc 0.7 v cc + 0.3 pa7 to pa0 * 7 v cc b 0.7 v cc b + 0.3 port 7 2.0 av cc + 0.3 p97, p86, p52, p42 (2) v cc 0.7 5.5 input high voltage input pins except (1) and (2) above v ih 2.0 v cc + 0.3 v rev. 2.0, 08/02, page 702 of 788 item symbol min typ max unit test conditions 5(6 , 67%< , md1, md0 C0.3 0.5 pa7 to pa0 (3) C0.3 1.0 input low voltage nmi, extal, input pins except (1) and (3) above v il C0.3 0.8 v v cc C 0.5 v cc b C 0.5 vi oh = C200 a all output pins (except p97, p86, p52, and p42) * 5 , * 8 3.5 v i oh = C1 ma, output high voltage p97, p86, p52, and p42 * 4 v oh 2.0 v i oh = C200 a all output pins (except 5(62 ) * 5 0.4vi ol = 1.6 ma ports 1 to 3 1.0 v i ol = 10 ma output low voltage 5(62 v ol 0.4vi ol = 2.6 ma notes: 1. do not leave the av cc , av ref , and av ss pins open even if the a/d converter and d/a converter are not used. even if the a/d converter and d/a converter are not used, apply a value in the range 2.0 v to 5.5 v to av cc and av ref pins by connection to the power supply (v cc ), or some other method. ensure that av ref av cc . 2. p67 to p60 include peripheral module inputs multiplexed on those pins. 3. ,54 5 includes the $'75* signal multiplexed on that pin. 4. p52/sck0/scl0, p97/sda0, p86/sck1/scl1, p42/sck2/sda1, and port g are nmos push-pull outputs. when the scl0, sda0, scl1, or sda1 (ice = 1) pin is used as an output, it is nmos open-drain output. therefore, an external pull-up resistor must be connected in order to output high level. p52/sck0, p97, p86/sck1, p42/sck2 (ice = 0), and port g high levels are driven by nmos. when the sck0, sck1, or sck2 pin is used as an output, an external pull-up resistor must be connected in order to output high level. 5. when iics = 0, ice = 0, and kbioe = 0. low-level output when the bus drive function is selected is determined separately. 6. the upper limit of the port 6 applied voltage is v cc + 0.3 v when cin input is not selected, and the lower of v cc + 0.3 v and av cc + 0.3 v when cin input is selected. when a pin is in output mode, the output voltage is equivalent to the applied voltage. 7. the upper limit of the port a applied voltage is v cc b + 0.3 v when cin input is not selected, and the lower of v cc b + 0.3 v and av cc + 0.3 v when cin input is selected. when a pin is in output mode, the output voltage is equivalent to the applied voltage. 8. the port a characteristics depend on v cc b, and the other pins characteristics depend on v cc in output mode. rev. 2.0, 08/02, page 703 of 788 table 28.17 dc characteristics (2) conditions: v cc = 5.0 v 10 %, v cc b = 5.0 v 10 %, av cc * 1 = 5.0 v 10 %, av ref * 1 = 4.5 v to av cc , v ss = av ss * 1 = 0 v, t a = C20 to +75c (normal specification product), t a = C40 to +85c (wide range temperature specification product) item symbol min typ max unit test conditions 5(6 10.0 67%< , nmi, md1, md0 1.0 v in = 0.5 to v cc C 0.5 v input leakage current port 7 ? i in ? 1.0 a v in = 0.5 to av cc C 0.5 v three-state leakage current (off state) ports 1 to 6 ports 8, 9, a * 4 , b ? i tsi ? 1.0av in = 0.5 to v cc C 0.5 v, v in = 0.5 to v cc b C 0.5 v ports 1 to 3 30 300 a ports a * 4 , b, 6 (p6pue = 0) 60 600 a input pull-up mos current port 6 (p6pue = 1) Ci p 15 200 a v in = 0 v 5(6 80 nmi 50 p52, p97, p42, p86, pa7 to pa2 (4) 20 input capacitance input pins except (4) above c in 15 pf v in = 0 v, f = 1 mhz, t a = 25c normal operation 55 70 ma f = 20 mhz sleep mode 36 55 ma f = 20 mhz 1.05.0 t a 50c current dissipation * 2 standby mode * 3 i cc 20.0 a during a/d, d/a conversion 1.22.0ma 50c < t a analog power supply current idle al cc 0.01 5.0 a av cc = 2.0 v to 5.5 v rev. 2.0, 08/02, page 704 of 788 item symbol min typ max unit test conditions during a/d conversion 0.5 1.0 during a/d, d/a conversion 2.05.0 ma reference power supply current idle al ref 0.01 5.0 a av ref = 2.0 v to av cc 4.5 5.5 operating analog power supply voltage * 1 av cc 2.0 5.5 v idle/not used ram standby voltage v ram 2.0 v notes: 1. do not leave the av cc , av ref , and av ss pins open even if the a/d converter and d/a converter are not used. even if the a/d converter and d/a converter are not used, apply a value in the range 2.0 v to 5.5 v to av cc and av ref pins by connection to the power supply (v cc ), or some other method. ensure that av ref av cc . 2. current dissipation values are for v ih min = v cc C 0.2 v, v cc b C 0.2 v, and v il max = 0.2 v with all output pins unloaded and the on-chip pull-up moss in the off state. 3. the values are for v ram v cc < 4.5 v, v ih min = v cc C 0.2 v, v cc b C 0.2 v, and v il max = 0.2 v. 4. the port a characteristics depend on v cc b, and the other pins characteristics depend on v cc . rev. 2.0, 08/02, page 705 of 788 table 28.17 dc characteristics (3) conditions: v cc = 4.0 v to 5.5 v, v cc b = 4.0 v to 5.5 v, av cc * 1 = 4.0 v to 5.5 v, av ref * 1 = 4.0 v to av cc , v ss = av ss * 1 = 0 v, t a = C20 to +75c (normal specification product), t a = C40 to +85c (wide range temperature specification product) item symbol min typ max unit test conditions v t C 1.0 v v t + v cc 0.7 v cc b 0.7 v t + C v t C 0.4 v v cc = 4.5 v to 5.5 v, v cc b = 4.5 v to 5.5 v v t C 0.8 v t + v cc 0.7 v cc b 0.7 schmitt trigger input voltage p67 to p60 (kwul = 00) * 2 , * 6 , .,1 48 to .,1 ; * 7 , * 8 , ,54 5 to ,54 3 * 3 , ,54 8 to ,54 6 v t + C v t C 0.3 vv cc = 4.0 v to 4.5 v, v cc b = 4.0 v to 4.5 v v t C v cc 0.3 v t + v cc 0.7 p67 to p60 (kwul = 01) v t + C v t C v cc 0.05 v t C v cc 0.4 v t + v cc 0.8 p67 to p60 (kwul = 10) v t + C v t C v cc 0.03 v t C v cc 0.45 v t + v cc 0.9 schmitt trigger input voltage (in level switching) * 6 p67 to p60 (kwul = 11) (1) v t + C v t C 0.05 vv cc = 4.0 v to 5.5 v 5(6 , 67%< , nmi, md1, md0 v cc C 0.7 v cc +0.3 extal v cc 0.7 v cc + 0.3 pa7 to pa0 * 7 v cc b 0.7 v cc b + 0.3 port 7 2.0 av cc + 0.3 p97, p86, p52, p42 v cc 0.7 5.5 input high voltage input pins except (1) and (2) above (2) v ih 2.0 v cc +0.3 v rev. 2.0, 08/02, page 706 of 788 item symbol min typ max unit test conditions C0.3 0.5 5(6 , 67%< , md1, md0 C0.3 1.0 v cc b = 4.5 v to 5.5 v pa7 to pa0 (3) C0.3 0.8 v cc b = 4.0 v to 4.5 v input low voltage nmi, extal, input pins except (1) and (3) above v il C0.3 0.8 v v cc C 0.5 v cc b C 0.5 vi oh = C200 a 3.5 v i oh = C1 ma, v cc = 4.5 v to 5.5 v, v cc b = 4.5 v to 5.5 v all output pins (except p97, p86, p52, and p42) * 4 , * 5 , * 8 3.0 v i oh = C1 ma, v cc = 4.0 v to 4.5 v, v cc b = 4.0 v to 4.5 v output high voltage p97, p86, p52, and p42 * 4 v oh 1.5 v i oh = C200 a all output pins (except 5(62 ) * 5 0.4vi ol = 1.6 ma ports 1 to 3 1.0 v i ol = 10 ma output low voltage 5(62 v ol 0.4vi ol = 2.6 ma notes: 1. do not leave the av cc , av ref , and av ss pins open even if the a/d converter and d/a converter are not used. even if the a/d converter and d/a converter are not used, apply a value in the range 2.0 v to 5.5 v to av cc and av ref pins by connection to the power supply (v cc ), or some other method. ensure that av ref av cc . 2. p67 to p60 include peripheral module inputs multiplexed on those pins. 3. ,54 5 includes the $'75* signal multiplexed on that pin. 4. p52/sck0/scl0, p97/sda0, p86/sck1/scl1, p42/sck2/sda1, and port g are nmos push-pull outputs. when the scl0, sda0, scl1, or sda1 (ice = 1) pin is used as an output, it is nmos open-drain output. therefore, an external pull-up resistor must be connected in order to output high level. p52/sck0, p97, p86/sck1, p42/sck2 (ice = 0), and port g high levels are driven by nmos. rev. 2.0, 08/02, page 707 of 788 when the sck0, sck1, or sck2 pin is used as an output, an external pull-up resistor must be connected in order to output high level. 5. when iics = 0, ice = 0, and kbioe = 0. low-level output when the bus drive function is selected is determined separately. 6. the upper limit of the port 6 applied voltage is v cc + 0.3 v when cin input is not selected, and the lower of v cc + 0.3 v and av cc + 0.3 v when cin input is selected. when a pin is in output mode, the output voltage is equivalent to the applied voltage. 7. the upper limit of the port a applied voltage is v cc b + 0.3 v when cin input is not selected, and the lower of v cc b + 0.3 v and av cc + 0.3 v when cin input is selected. when a pin is in output mode, the output voltage is equivalent to the applied voltage. 8. the port a characteristics depend on v cc b, and the other pins characteristics depend on v cc . rev. 2.0, 08/02, page 708 of 788 table 28.17 dc characteristics (4) conditions: v cc = 4.0 v to 5.5 v, v cc b = 4.0 v to 5.5 v, av cc * 1 = 4.0 v to 5.5 v, av ref * 1 = 4.0 v to av cc , v ss = av ss * 1 = 0 v, t a = C20 to +75c (normal specification product), t a = C40 to +85c (wide range temperature specification product) item symbol min typ max unit test conditions 5(6 10.0 67%< , nmi, md1, md0 1.0 v in = 0.5 to v cc C0.5 v input leakage current port 7 ? i in ? 1.0 a v in = 0.5 to av cc C 0.5 v three-state leakage current (off state) ports 1 to 6 ports 8, 9, a * 4 , b ? i tsi ? 1.0av in = 0.5 to v cc C 0.5 v, v in = 0.5 to v cc b C 0.5 v ports 1 to 3 30 300 ports a * 4 , b, 6 (p6pue = 0) 60 600 port 6 (p6pue = 1) 15 200 a v in = 0 v, v cc = 4.5 v to 5.5 v, v cc b = 4.5 v to 5.5 v ports 1 to 3 20 200 ports a * 4 , b, 6 (p6pue = 0) 40 500 input pull-up mos current port 6 (p6pue = 1) Ci p 10 150 a v in = 0 v, v cc = 4.0 v to 4.5 v, v cc b = 4.0 v to 4.5 v 5(6 80 nmi 50 p52, p97, p42, p86, pa7 to pa2 (4) 20 input capacitance input pins except (4) above c in 15 pf v in = 0 v, f = 1 mhz, t a = 25c normal operation 45 58 ma f = 16 mhz sleep mode 30 46 ma f = 16 mhz 1.05.0 t a 50c current dissipation * 2 standby mode * 3 i cc 20.0 a 50c < t a rev. 2.0, 08/02, page 709 of 788 item symbol min typ max unit test conditions during a/d, d/a conversion 1.22.0ma analog power supply current idle al cc 0.01 5.0 a av cc = 2.0 v to 5.5 v during a/d conversion 0.5 1.0 during a/d, d/a conversion 2.05.0 ma reference power supply current idle al ref 0.01 5.0 a av ref = 2.0 v to av cc 4.0 5.5 operating analog power supply voltage * 1 av cc 2.0 5.5 v idle/not used ram standby voltage v ram 2.0 v notes: 1. do not leave the av cc , av ref , and av ss pins open even if the a/d converter and d/a converter are not used. even if the a/d converter and d/a converter are not used, apply a value in the range 2.0 v to 5.5 v to av cc and av ref pins by connection to the power supply (v cc ), or some other method. ensure that av ref av cc . 2. current dissipation values are for v ih min = v cc C 0.2 v, v cc b C 0.2 v, and v il max = 0.2 v with all output pins unloaded and the on-chip pull-up moss in the off state. 3. current dissipation values are for v ih min = v cc C 0.2 v, v cc b C 0.2 v, and v il max = 0.2 v with all output pins unloaded and the on-chip pull-up moss in the off state. 4. the port a characteristics depend on vccb, and the other pins characteristics depend on vcc. rev. 2.0, 08/02, page 710 of 788 table 28.17 dc characteristics (5) conditions: v cc = 2.7 v to 3.6 v* 9 , v cc b = 2.7 v to 5.5 v, av cc * 1 = 2.7 v to 3.6 v, av ref = 2.7 v to 3.6 v, v ss = av ss * 1 = 0 v, t a = C20 to +75c item symbol min typ max unit test conditions v t C v cc 0.2 v cc b 0.2 schmitt trigger input voltage p67 to p60 (kwul = 00) * 2 , * 6 , .,1 48 to .,1 ; * 7 , * 8 , ,54 5 to ,54 3 * 3 , ,54 8 to ,54 6 v t + v cc 0.7 v cc b 0.7 v v t C v cc 0.3 v t + v cc 0.7 p67 to p60 (kwul = 01) v t + C v t C v cc 0.05 v t C v cc 0.4 v t + v cc 0.8 p67 to p60 (kwul = 10) v t + C v t C v cc 0.03 v t C v cc 0.45 v t + v cc 0.9 schmitt trigger input voltage (in level switching) * 6 p67 to p60 (kwul = 11) (1) v t + C v t C 0.05 v 5(6 , 67%< , nmi, md1, md0 v cc 0.9 v cc + 0.3 extal v cc 0.7 v cc + 0.3 pa7 to pa0 * 7 v cc b 0.7 v cc b + 0.3 port 7 v cc 0.7 av cc + 0.3 p97, p86, p52, p42 (2) v cc 0.7 5.5 input high voltage input pins except (1) and (2) above v ih v cc 0.7 v cc +0.3 v rev. 2.0, 08/02, page 711 of 788 item symbol min typ max unit test conditions 5(6 , 67%< , md1, md0 C0.3 v cc 0.1 v cc b 0.2 v cc b = 2.7 v to 4.0 v pa7 to pa0 (3) C0.3 0.8 v cc b = 4.0 v to 5.5 v input low voltage nmi, extal, input pins except (1) and (3) above v il C0.3 v cc 0.2 v v cc = 2.7 v to 3.6 v v cc C 0.5 v cc b C 0.5 vi oh = C200 a all output pins (except p97, p86, p52, and p42) * 4 , * 5 , * 8 v cc C 1.0 v cc b C 1.0 vi oh = C1 ma, v cc = 2.7 v to 3.6 v, v cc b = 2.7 v to 4.0 v, output high voltage p97, p86, p52, and p42 * 4 v oh 0.5 v i oh = C200 a all output pins (except 5(62 ) * 5 0.4vi ol = 1.6 ma ports 1 to 3 1.0 v i ol = 5 ma output low voltage 5(62 v ol 0.4vi ol = 1.6 ma notes: 1. do not leave the av cc , av ref , and av ss pins open even if the a/d converter and d/a converter are not used. even if the a/d converter and d/a converter are not used, apply a value in the range 2.0 v to 3.6 v to av cc and av ref pins by connection to the power supply (v cc ), or some other method. ensure that av ref av cc . 2. p67 to p60 include peripheral module inputs multiplexed on those pins. 3. ,54 5 includes the $'75* signal multiplexed on that pin. 4. p52/sck0/scl0, p97/sda0, p86/sck1/scl1, p42/sck2/sda1, and port g are nmos push-pull outputs. when the scl0, sda0, scl1, or sda1 (ice = 1) pin is used as an output, it is nmos open-drain output. therefore, an external pull-up resistor must be connected in order to output high level. p52/sck0, p97, p86/sck1, p42/sck2 (ice = 0), and port g high levels are driven by nmos. when the sck0, sck1, or sck 2 pin is used as an output, an external pull-up resistor must be connected in order to output high level. 5. when iics = 0, ice = 0, and kbioe = 0. low-level output when the bus drive function is selected is determined separately. rev. 2.0, 08/02, page 712 of 788 6. the upper limit of the port 6 applied voltage is v cc + 0.3 v when cin input is not selected, and the lower of v cc + 0.3 v and av cc + 0.3 v when cin input is selected. when a pin is in output mode, the output voltage is equivalent to the applied voltage. 7. the upper limit of the port a applied voltage is v cc b + 0.3 v when cin input is not selected, and the lower of v cc b + 0.3 v and av cc + 0.3 v when cin input is selected. when a pin is in output mode, the output voltage is equivalent to the applied voltage. 8. the port a characteristics depend on v cc b, and the other pins characteristics depend on v cc . 9. for flash memory programming/erasure, the applicable range is v cc = 3.0 v to 3.6 v. rev. 2.0, 08/02, page 713 of 788 table 28.17 dc characteristics (6) conditions: v cc = 2.7 v to 3.6 v* 5 , v cc b = 2.7 v to 5.5 v, av cc * 1 = 2.7 v to 3.6 v, av ref * 1 = 2.7 v to 3.6 v, v ss = av ss * 1 = 0 v, t a = C20 to +75c item symbol min typ max unit test conditions 5(6 10.0 67%< , nmi, md1, md0 1.0 v in = 0.5 to v cc C 0.5 v input leakage current port 7 ? i in ? 1.0 a v in = 0.5 to av cc C 0.5 v three-state leakage current (off state) ports 1 to 6 ports 8, 9, a * 4 , b ? i tsi ? 1.0av in = 0.5 to v cc C 0.5 v, v in = 0.5 to v cc b C 0.5 v ports 1 to 3 5 150 ports a * 4 , b, 6 (p6pue = 0) 30 300 input pull-up mos current port 6 (p6pue = 1) Ci p 3 100 a v in = 0 v, v cc = 2.7 v to 3.6 v, v cc b = 2.7 v to 3.6 v 5(6 80 nmi 50 p52, p97, p42, p86, pa7 to pa2 (4) 20 input capacitance input pins except (4) above c in 15 pf v in = 0 v, f = 1 mhz, t a = 25c normal operation 30 40 ma f = 10 mhz sleep mode 20 32 ma f = 10 mhz 1.05.0 t a 50c current dissipation * 2 standby mode * 3 i cc 20.0 a 50c < t a during a/d, d/a conversion 1.22.0ma analog power supply current idle al cc 0.01 5.0 a av cc = 2.0 v to 3.6 v rev. 2.0, 08/02, page 714 of 788 item symbol min typ max unit test conditions during a/d conversion 0.5 1.0 during a/d, d/a conversion 2.05.0 ma reference power supply current idle al ref 0.01 5.0 a av ref = 2.0 v to av cc av cc 2.7 3.6 operating analog power supply voltage * 1 2.0 3.6 v idle/not used ram standby voltage v ram 2.0 v notes: 1. do not leave the av cc , av ref , and av ss pins open even if the a/d converter and d/a converter are not used. even if the a/d converter and d/a converter are not used, apply a value in the range 2.0 v to 3.6 v to av cc and av ref pins by connection to the power supply (v cc ), or some other method. ensure that av ref av cc . 2. current dissipation values are for v ih min = v cc C 0.2 v, v cc b C 0.2 v, and v il max = 0.2 v with all output pins unloaded and the on-chip pull-up moss in the off state. 3. the values are for v ram v cc < 2.7 v, v ih min = v cc C 0.2 v, v cc b C 0.2 v, and v il max = 0.2 v. 4. the port a characteristics depend on vccb, and the other pins characteristics depend on vcc. 5. for flash memory programming/erasure, the applicable range is v cc = 3.0 v to 3.6 v. rev. 2.0, 08/02, page 715 of 788 table 28.17 dc characteristics (7) (3-v version of h8s/2145bv) when lpc function is used conditions: v cc = 3.0 v to 3.6 v, v cc b = 2.7 v to 5.5 v, av cc * = 2.7 v to 3.6 v, av ref * = 2.7 v to av cc , v ss = av ss * 1 = 0 v, t a = C20 to +75c item symbol min max unit test conditions input high voltage p37 to p30, p83 to p80, pb1, pb0 v ih v cc 0.5 v input low voltage p37 to p30, p83 to p80, pb1, pb0 v il v cc 0.3 v output high voltage p37, p33 to p30, p82 to p80, pb1, pb0 v oh v cc 0.9 v i oh = C0.5 ma output low voltage p37, p33 to p30, p82 to p80, pb1, pb0 v ol v cc 0.1 v i ol = 1.5 ma note: * do not leave the av cc , av ref , and av ss pins open even if the a/d converter and d/a converter are not used. even if the a/d converter and d/a converter are not used, apply a value in the range 2.0 v to 3.6 v to av cc and av ref pins by connection to the power supply (v cc ), or some other method. ensure that av ref av cc . rev. 2.0, 08/02, page 716 of 788 table 28.18 permissible output currents conditions: v cc = 4.0 v to 5.5 v, v cc b = 4.0 v to 5.5 v, v ss = 0 v, t a = C20 to +75c (normal specification product), t a = C40 to +85c (wide range temperature specification product) item symbol min typ max unit scl1, scl0, sda1, sda0, ps2ac to ps2cc, ps2ad to ps2cd, pa7 to pa4 (bus drive function selected) 20 ports 1, 2, 3 10 5(62 3 permissible output low current (per pin) other output pins i ol 2 ma total of ports 1, 2, and 3 80 permissible output low current (total) total of all output pins, including the above ? i ol 120 ma permissible output high current (per pin) all output pins Ci oh 2 ma permissible output high current (total) total of all output pins ? Ci oh 40ma rev. 2.0, 08/02, page 717 of 788 conditions: v cc = 2.7 v to 3.6 v, v cc b = 2.7 v to 5.5 v, v ss = 0 v, t a = C20 to +75c item symbol min typ max unit scl1, scl0, sda1, sda0, ps2ac to ps2cc, ps2ad to ps2cd, pa7 to pa4 (bus drive function selected) 10 ports 1, 2, 3 2 5(62 1 permissible output low current (per pin) other output pins i ol 1 ma total of ports 1, 2, and 3 40 ma permissible output low current (total) total of all output pins, including the above ? i ol 60ma permissible output high current (per pin) all output pins Ci oh 2 ma permissible output high current (total) total of all output pins ? Ci oh 30ma notes: 1. to protect chip reliability, do not exceed the output current values in table 28.18. 2. when driving a darlington pair or led, always insert a current-limiting resistor in the output line, as show in figures 28.1 and 28.2. rev. 2.0, 08/02, page 718 of 788 table 28.19 bus drive characteristics conditions: v cc = 4.0 v to 5.5 v, v cc = 2.7 v to 3.6 v (3-v version product), v ss = 0 v applicable pins: scl1, scl0, sda1, sda0 (bus drive function selected) item symbol min typ max unit test conditions v t C v cc 0.3 v t + v cc 0.7 schmitt trigger input voltage v t + C v t C v cc 0.05 v input high voltage v ih v cc 0.7 5.5 input low voltage v il C0.5 v cc 0.3 v 0.8 i ol = 16 ma, v cc = 4.5 v to 5.5 v 0.5 i ol = 8 ma output low voltage v ol 0.4 v i ol = 3 ma input capacitance c in 20 pf v in = 0 v, f = 1 mhz, t a = 25c three-state leakage current (off state) | i tsi | 1.0 a v in = 0.5 to v cc C 0.5 v scl, sda output fall time t of 20 + 0.1cb 250 ns conditions: v cc = 4.0 v to 5.5 v, v cc = 2.7 v to 3.6 v (3-v version product), v cc b = 2.7 v to 5.5 v, v ss = 0 v applicable pins: ps2ac, ps2ad, ps2bc, ps2bd, ps2cc, ps2cd, pa7 to pa4 (bus drive function selected) item symbol min typ max unit test conditions 0.8 i ol = 16 ma, v cc b = 4.5 v to 5.5 v 0.5 i ol = 8 ma output low voltage v ol 0.4 v i ol = 3 ma rev. 2.0, 08/02, page 719 of 788 28.2.3 ac characteristics the following shows the clock timing, control signal timing, bus timing, and on-chip peripheral function timing. for the ac characteristics test conditions, see figure 28.3. clock timing: table 28.20 shows the clock timing. the clock timing specified here covers clock (?) output and clock pulse generator (crystal) and external clock input (extal pin) oscillation settling times. for details of external clock input (extal pin and excl pin) timing, see section 25, clock pulse generator. table 28.20 clock timing condition a: v cc = 5.0 v 10%, v cc b = 5.0 v 10%, v ss = 0 v, ? = 2 mhz to maximum operating frequency, t a = C20 to +75c (normal specification product), t a = C40 to +85c (wide range temperature specification product) condition b: v cc = 4.0 v to 5.5 v, v cc b = 4.0 v to 5.5 v, v ss = 0 v, ? = 2 mhz to maximum operating frequency, t a = C20 to +75c (normal specification product), t a = C40 to +85c (wide range temperature specification product) condition c: v cc = 2.7 v to 3.6 v, v cc b = 2.7 v to 5.5 v, v ss = 0 v, ? = 2 mhz to maximum operating frequency, t a = C20 to +75c condition a condition b condition c 10 mhz 16 mhz 20 mhz item symbol min max min max min max unit test conditions clock cycle time t cyc 100 500 62.5 500 50 500 ns figure 28.6 clock high pulse width t ch 30 20 17 ns clock low pulse width t cl 30 20 17 ns clock rise time t cr 20 10 8 ns clock fall time t cf 20 10 8 ns figure 28.6 oscillation settling time at reset (crystal) t osc1 20 10 10 ms figure 28.7 oscillation settling time in software standby (crystal) t osc2 888 ms external clock output stabilization delay time t dext 500 500 500 s figure 28.8 rev. 2.0, 08/02, page 720 of 788 control signal timing: table 28.21 shows the control signal timing. the only external interrupts that can operate on the subclock (? = 32.768 khz) are nmi and irq0, 1, 2, 6, and 7. table 28.21 control signal timing condition a: v cc = 5.0 v 10%, v cc b = 5.0 v 10%, v ss = 0 v, ? = 32.768 khz, 2 mhz to maximum operating frequency, t a = C20 to +75c (normal specification product), t a = C40 to +85c (wide range temperature specification product) condition b: v cc = 4.0 v to 5.5 v, v cc b = 4.0 v to 5.5 v, v ss = 0 v, ? = 32.768 khz, 2 mhz to maximum operating frequency, t a = C20 to +75c (normal specification product), t a = C40 to +85c (wide range temperature specification product) condition c: v cc = 2.7 v to 3.6 v, v cc b = 2.7 v to 5.5 v, v ss = 0 v, ? = 32.768 khz, 2 mhz to maximum operating frequency, t a = C20 to +75c condition a condition b condition c 10 mhz 16 mhz 20 mhz item symbol min max min max min max unit test conditions 5(6 setup time t ress 300 200 200 ns 5(6 pulse width t resw 20 20 20 t cyc figure 28.9 nmi setup time (nmi) t nmis 250 150 150 ns nmi hold time (nmi) t nmih 10 10 10 ns nmi pulse width (nmi) (exiting software standby mode) t nmiw 200 200 200 ns irq setup time ( ,54 : to ,54 3 ) t irqs 250 150 150 ns irq hold time ( ,54 : to ,54 3 ) t irqh 10 10 10 ns irq pulse width ( ,54 : , ,54 9 , ,54 5 to ,54 3 ) (exiting software standby mode) t irqw 200 200 200 ns figure 28.10 rev. 2.0, 08/02, page 721 of 788 bus timing: table 28.22 shows the bus timing. operation in external expansion mode is not guaranteed when operating on the subclock (? = 32.768 khz). table 28.22 bus timing (1) (normal mode) condition a: v cc = 5.0 v 10%, v cc b = 5.0 v 10%, v ss = 0 v, ? = 2 mhz to maximum operating frequency, t a = C20 to +75c (normal specification product), t a = C40 to +85c (wide range temperature specification product) condition b: v cc = 4.0 v to 5.5 v, v cc b = 4.0 v to 5.5 v, v ss = 0 v, ? = 2 mhz to maximum operating frequency, t a = C20 to +75c (normal specification product), t a = C40 to +85c (wide range temperature specification product) condition c: v cc = 2.7 v to 3.6 v, v cc b = 2.7 v to 5.5 v, v ss = 0 v, ? = 2 mhz to maximum operating frequency, t a = C20 to +75c condition a condition b condition c 10 mhz 16 mhz 20 mhz item symbol min max min max min max unit test conditions address delay time t ad 403020ns address setup time t as 0.5 tcyc C 30 0.5 t cyc C 20 0.5 t cyc C 15 ns address hold time t ah 0.5 t cyc C 20 0.5 t cyc C 15 0.5 t cyc C 10 ns &6 delay time ( ,26 )t csd 403020ns $6 delay time t asd 604530ns 5' delay time 1 t rsd1 604530ns 5' delay time 2 t rsd2 604530ns read data setup time t rds 35 20 15 ns read data hold time t rdh 000ns read data access time 1 t acc1 1.0 t cyc C 60 1.0 t cyc C 40 1.0 t cyc C 30 ns read data access time 2 t acc2 1.5 t cyc C 50 1.5 t cyc C 35 1.5 t cyc C 25 ns figures 28.11 to 28.15 rev. 2.0, 08/02, page 722 of 788 condition a condition b condition c 10 mhz 16 mhz 20 mhz item symbol min max min max min max unit test conditions read data access time 3 t acc3 2.0 t cyc C 60 2.0 t cyc C 40 2.0 t cyc C 30 ns read data access time 4 t acc4 2.5 t cyc C 50 2.5 t cyc C 35 2.5 t cyc C 25 ns read data access time 5 t acc5 3.0 t cyc C 60 3.0 t cyc C 40 3.0 t cyc C 30 ns +:5 , /:5 delay time 1 t wrd1 604530ns +:5 , /:5 delay time 2 t wrd2 604530ns +:5 , /:5 pulse width 1 t wsw1 1.0 t cyc C 40 1.0 t cyc C 30 1.0 t cyc C 20 ns +:5 , /:5 pulse width 2 t wsw2 1.5 t cyc C 40 1.5 t cyc C 30 1.5 t cyc C 20 ns write data delay time t wdd 604530ns write data setup time t wds 000ns write data hold time t wdh 20 15 10 ns :$,7 setup time t wts 60 45 30 ns :$,7 hold time t wth 10 5 5 ns figures 28.9 to 28.13 rev. 2.0, 08/02, page 723 of 788 table 28.22 bus timing (2) (advanced mode) condition a: v cc = 5.0 v 10 %, v cc b = 5.0 v 10 %, v ss = 0 v, ? = 2 mhz to maximum operating frequency, t a = C20 to +75c (normal specification product), t a = C40 to +85c (wide range temperature specification product) condition b: v cc = 4.0 v to 5.5 v, v cc b = 4.0 v to 5.5 v, v ss = 0 v, ? = 2 mhz to maximum operating frequency, t a = C20 to +75c (normal specification product), t a = C40 to +85c (wide range temperature specification product) condition c: v cc = 2.7 v to 3.6 v, v cc b = 2.7 v to 5.5 v, v ss = 0 v, ? = 2 mhz to maximum operating frequency, t a = C20 to +75c condition a condition b condition c 10 mhz 16 mhz 20 mhz item symbol min max min max min max unit test conditions address delay time t ad 604530ns address setup time t as 0.5 t cyc C 50 0.5 t cyc C 35 0.5 t cyc C 25 ns address hold time t ah 0.5 t cyc C 20 0.5 t cyc C 15 0.5 t cyc C 10 ns &6 delay time ( ,26 )t csd 604530ns $6 delay time t asd 604530ns 5' delay time 1 t rsd1 604530ns 5' delay time 2 t rsd2 604530ns read data setup time t rds 35 20 15 ns read data hold time t rdh 000ns read data access time 1 t acc1 1.0 t cyc C 80 1.0 t cyc C 55 1.0 t cyc C 40 ns read data access time 2 t acc2 1.5 t cyc C 50 2.5 t cyc C 35 2.5 t cyc C 25 ns read data access time 3 t acc3 2.0 t cyc C 80 3.0 t cyc C 55 3.0 t cyc C 40 ns figures 28.11 to 28.15 rev. 2.0, 08/02, page 724 of 788 condition a condition b condition c 10 mhz 16 mhz 20 mhz item symbol min max min max min max unit test conditions read data access time 4 t acc4 2.5 t cyc C 50 2.5 t cyc C 35 2.5 t cyc C 25 ns read data access time 5 t acc5 3.0 t cyc C 80 3.0 t cyc C 55 3.0 t cyc C 40 ns +:5 , /:5 delay time 1 t wrd1 604530ns +:5 , /:5 delay time 2 t wrd2 604530ns +:5 , /:5 pulse width 1 t wsw1 1.0 t cyc C 40 1.0 t cyc C 30 1.0 t cyc C 20 ns +:5 , /:5 pulse width 2 t wsw2 1.5 t cyc C 40 1.5 t cyc C 30 1.5 t cyc C 20 ns write data delay time t wdd 604530ns write data setup time t wds 000ns write data hold time t wdh 20 15 10 ns :$,7 setup time t wts 60 45 30 ns :$,7 hold time t wth 10 5 5 ns figures 28.11 to 28.15 rev. 2.0, 08/02, page 725 of 788 timing of on-chip peripheral modules: tables 28.23 to 28.26 show the on-chip peripheral module timing. the only on-chip peripheral modules that can operate in subclock operation (? = 32.768 khz) are the i/o ports, external interrupts (nmi and irq0, 1, 2, 6, and 7), the watchdog timer, and the 8-bit timer (channels 0 and 1). table 28.23 timing of on-chip peripheral modules (1) condition a: v cc = 5.0 v 10 %, v cc b = 5.0 v 10 %, v ss = 0 v, ? = 32.768 khz*, 2 mhz to maximum operating frequency, t a = C20 to +75c (normal specification product), t a = C40 to +85c (wide range temperature specification product) condition b: v cc = 4.0 v to 5.5 v, v cc b = 4.0 v to 5.5 v, v ss = 0 v, ? = 32.768 khz*, 2 mhz to maximum operating frequency, t a = C20 to +75c (normal specification product), t a = C40 to +85c (wide range temperature specification product) condition c: v cc = 2.7 v to 3.6 v, v cc b = 2.7 v to 5.5 v, v ss = 0 v, ? = 32.768 khz*, 2 mhz to maximum operating frequency, t a = C20 to +75c condition a condition b condition c 10 mhz 16 mhz 20 mhz item sym- bol min max min max min max unit test conditions output data delay time t pwd 100 50 50 input data setup time t prs 50 30 30 i/o ports input data hold time t prh 50 30 30 ns figure 28.16 timer output delay time t ftod 100 50 50 timer input setup time t ftis 50 30 30 figure 28.17 timer clock input setup time t ftcs 50 30 30 ns single edge t ftcwh 1.5 1.5 1.5 frt timer clock pulse width both edges t ftcwl 2.5 2.5 2.5 t cyc figure 28.18 timer output delay time t tmod 100 50 50 figure 28.19 timer reset input setup time t tmrs 50 30 30 figure 28.21 tmr timer clock input setup time t tmcs 50 30 30 ns figure 28.20 rev. 2.0, 08/02, page 726 of 788 condition a condition b condition c 10 mhz 16 mhz 20 mhz item sym- bol min max min max min max unit test conditions single edge t tmcwh 1.5 1.5 1.5 tmr timer clock pulse width both edges t tmcwl 2.5 2.5 2.5 t cyc figure 28.20 pwm, pwmx pulse output delay time t pwod 100 50 50 ns figure 28.22 asynchronous t scyc 444 input clock cycle synchronous 666 t cyc input clock pulse width t sckw 0.4 0.6 0.4 0.6 0.4 0.6 t cscyc input clock rise time t sckr 1.5 1.5 1.5 input clock fall time t sckf 1.5 1.5 1.5 t cyc figure 28.23 transmit data delay time (clocked synchronous) t txd 100 50 50 receive data setup time (clocked synchronous) t rxs 100 50 50 sci receive data hold time (clocked synchronous) t rxh 100 50 50 ns figure 28.24 a/d converter trigger input setup time t trgs 50 30 30 ns figure 28.25 5(62 output delay time t resd 200 120 100 ns wdt 5(62 output pulse width t resow 132 132 132 t cyc figure 28.26 note: * only peripheral modules that can be used in subclock operation rev. 2.0, 08/02, page 727 of 788 table 28.23 timing of on-chip peripheral modules (2) condition a: v cc = 5.0 v 10 %, v cc b = 5.0 v 10 %, v ss = 0 v, 2 mhz to maximum operating frequency, t a = C20 to +75c (normal specification product), t a = C40 to +85c (wide range temperature specification product) condition b: v cc = 4.0 v to 5.5 v, v cc b = 4.0 v to 5.5 v, v ss = 0 v, 2 mhz to maximum operating frequency, t a = C20 to +75c (normal specification product), t a = C40 to +85c (wide range temperature specification product) condition c: v cc = 2.7 v to 3.6 v, v cc b = 2.7 v to 5.5 v, v ss = 0 v, ? = 2 mhz to maximum operating frequency, t a = C20 to +75c condition a condition b condition c 10 mhz 16 mhz 20 mhz item sym- bol min max min max min max unit test conditions &6 /ha0 setup time t har 10 10 10 &6 /ha0 hold time t hra 10 10 10 ,25 pulse width t hrpw 220 120 120 hdb delay time t hrd 200 100 100 hdb hold time t hrf 040025025 hif read cycle hirq delay time t hirq 200 120 120 &6 /ha0 setup time t haw 10 10 10 &6 /ha0 hold time t hwa 10 10 10 ,2: pulse width t hwpw 100 60 60 fast a20 gate not used 50 30 30 hdb setup time fast a20 gate used t hdw 85 55 45 hdb hold time t hwd 25 15 15 hif write cycle ga20 delay time t hga 180 90 90 ns figure 28.27 rev. 2.0, 08/02, page 728 of 788 table 28.24 keyboard buffer controller timing conditions: v cc = 4.0 v to 5.5 v, v cc = 2.7 v to 3.6 v (3-v product), v cc b = 2.7 v to 5.5 v, v ss = 0 v, ? = 2 mhz to maximum operating frequency, t a = C20 to +75c ratings item symbol min typ max unit test conditions notes kclk, kd output fall time t kbf 20 + 0.1cb 250 ns kclk, kd input data hold time t kbih 150 ns kclk, kd input data setup time t kbis 150 ns kclk, kd output delay time t kbod 450 ns kclk, kd capacitive load c b 400 pf figure 28.28 table 28.25 i 2 c bus timing conditions: v cc = 4.0 v to 5.5 v, v cc = 2.7 v to 3.6 v (3-v product), v ss = 0 v, ? = 5 mhz to maximum operating frequency, ratings item symbol min typ max unit test conditions notes scl input cycle time t scl 12 t cyc scl input high pulse width t sclh 3t cyc scl input low pulse width t scll 5t cyc scl, sda input rise time t sr 7.5 * t cyc scl, sda input fall time t sf 300 ns scl, sda input spike pulse elimination time t sp 1 t cyc sda input bus free time t buf 5t cyc start condition input hold time t stah 3t cyc retransmission start condition input setup time t stas 3t cyc stop condition input setup time t stos 3t cyc data input setup time t sdas 0.5 t cyc data input hold time t sdah 0ns scl, sda capacitive load c b 400 pf figure 28.29 note: * 17.5t cyc can be set according to the clock selected for use by the i 2 c module. for details, see section 16.6, usage notes. rev. 2.0, 08/02, page 729 of 788 table 28.26 lpc module timing (for h8s/2145b only) conditions: v cc = 3.0 v to 3.6 v, v ss = 0 v, ? = 2 mhz to maximum operating frequency, t a = C20 to +75c item symbol min typ max unit test conditions input clock cycle t lcyc 30 input clock pulse width (h) t lckh 11 input clock pulse width (l) t lckl 11 transmit signal delay time t txd 211 transmit signal floating delay time t off 28 receive signal setup time t rxs 7 lpc receive signal hold time t rxh 0 ns figure 28.30 rev. 2.0, 08/02, page 730 of 788 28.2.4 a/d conversion characteristics tables 28.27 and 28.28 list the a/d conversion characteristics. table 28.27 a/d conversion characteristics (an7 to an0 input: 134/266-state conversion) condition a: v cc = 5.0 v 10%, av cc = 5.0 v 10%, av ref = 4.5 v to av cc , v ss = av ss = 0 v, ? = 2 mhz to maximum operating frequency, t a = C20 to +75c (normal specification product), t a = C40 to +85c (wide range temperature specification product) condition b: v cc = 4.0 v to 5.5 v, av cc = 4.0 v to 5.5 v, av ref = 4.0 v to av cc , v ss = av ss = 0 v, ? = 2 mhz to maximum operating frequency, t a = C20 to +75c (normal specification product), t a = C40 to +85c (wide range temperature specification product) condition c: v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, av ref = 2.7 v to av cc , v ss = av ss = 0 v,, ? = 2 mhz to maximum operating frequency, t a = C20 to +75c condition c condition b condition a 10 mhz 16 mhz 20 mhz item min typ max min typ max min typ max unit resolution 10 10 10 bits conversion time * 3 13.48.46.7s analog input capacitance 202020pf 10 * 1 10 * 1 permissible signal- source impedance 5 5 * 2 5 * 2 k w nonlinearity error 7.0 3.0 3.0 lsb offset error 7.5 3.5 3.5 lsb full-scale error 7.5 3.5 3.5 lsb quantization error 0.5 0.5 0.5 lsb absolute accuracy 8.0 4.0 4.0 lsb notes: 1. when conversion time 3 11.17 s (cks = 0, or ? 12 mhz at cks = 1) 2. when conversion time < 11.17 s (? > 12 mhz at cks = 1) 3. at the maximum operating frequency in single mode. rev. 2.0, 08/02, page 731 of 788 table 28.28 a/d conversion characteristics (cin15 to cin0 input: 134/266-state conversion) condition a: v cc = 5.0 v 10%, av cc = 5.0 v 10%, av ref = 4.5 v to av cc , v ss = av ss = 0 v, ? = 2 mhz to maximum operating frequency, t a = C20 to +75c (normal specification product), t a = C40 to +85c (wide range temperature specification product) condition b: v cc = 4.0 v to 5.5 v, av cc = 4.0 v to 5.5 v, av ref = 4.0 v to av cc , v ss = av ss = 0 v, ? = 2 mhz to maximum operating frequency, t a = C20 to +75c (normal specification product), t a = C40 to +85c (wide range temperature specification product) condition c: v cc = 3.0 v to 3.6 v* 4 , av cc = 3.0 v to 3.6 v* 4 , av ref = 3.0 v to av cc * 4 , v cc b = 3.0 v to 5.5 v* 4 , v ss = av ss = 0 v, ? = 2 mhz to maximum operating frequency, t a = C20 to +75c condition c condition b condition a 10 mhz 16 mhz 20 mhz item min typ max min typ max min typ max unit resolution 10 10 10 bits conversion time * 3 13.48.46.7s analog input capacitance 202020pf 10 * 1 10 * 1 permissible signal- source impedance 5 5 * 2 5 * 2 k w nonlinearity error 11.0 5.0 5.0 lsb offset error 11.5 5.5 5.5 lsb full-scale error 11.5 5.5 5.5 lsb quantization error 0.5 0.5 0.5 lsb absolute accuracy 12.0 6.0 6.0 lsb notes: 1. when conversion time 3 11.17 s (cks = 0, or ? 12 mhz at cks = 1) 2. when conversion time < 11.17 s (? > 12 mhz at cks = 1) 3. at the maximum operating frequency in single mode. 4. when using cin, ensure that v cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, av ref = 3.0 v to 3.6 v, v cc b = 3.0 v to 5.5 v. rev. 2.0, 08/02, page 732 of 788 28.2.5 d/a conversion characteristics table 28.29 lists the d/a conversion characteristics. table 28.29 d/a conversion characteristics condition a: v cc = 5.0 v 10%, av cc = 5.0 v 10%, av ref = 4.5 v to av cc , v ss = av ss = 0 v, ? = 2 mhz to maximum operating frequency, t a = C20 to +75c (normal specification product), t a = C40 to +85c (wide range temperature specification product) condition b: v cc = 4.0 v to 5.5 v, av cc = 4.0 v to 5.5 v, av ref = 4.0 v to av cc , v ss = av ss = 0 v, ? = 2 mhz to maximum operating frequency, t a = C20 to +75c (normal specification product), t a = C40 to +85c (wide range temperature specification product) condition c: v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, av ref = 2.7 v to av cc , v ss = av ss = 0 v, ? = 2 mhz to maximum operating frequency, t a = C20 to +75c condition c condition b condition a 10 mhz 16 mhz 20 mhz item min typ max min typ max min typ max unit resolution 8 8 8 bits conversion time with 20 pf load capacitance 101010s with 2 m w load resistance 2.0 3.0 1.0 1.5 1.0 1.5 absolute accuracy with 4 m w load resistance 2.01.01.0 lsb rev. 2.0, 08/02, page 733 of 788 28.2.6 flash memory characteristics table 28.30 shows the flash memory characteristics. table 28.30 flash memory characteristics (operation range at programming/erasing) 5-v version conditions: v cc = 4.0 v to 5.5 v, v ss = 0 v, t a = C20 to +75c (normal specification product), t a = C40 to +85c (wide range temperature specification product), 3-v version conditions: v cc = 3.0 v to 3.6 v, v ss = 0 v, t a = C20 to +75c item symbol min typ max unit test condition programming time * 1 , * 2 , * 4 t p 10 200 ms/ 128 bytes erase time * 1 , * 3 , * 6 t e 100 1200 ms/ block reprogramming count n wec 100 times wait time after swe-bit setting * 1 x1s wait time after psu-bit setting * 1 y50s z1 28 30 32 s 1 n 6 z2 198 200 202 s 7 n 1000 wait time after p-bit setting * 1 , * 4 z3 8 10 12 s additional write wait time after p-bit clear * 1 a 5s wait time after psu-bit clear * 1 b 5s wait time after pv-bit setting * 1 g 4s wait time after dummy write * 1 e 2s wait time after pv-bit clear * 1 h 2s wait time after swe-bit clear * 1 q 100 s programming maximum programming count * 1 , * 4 , * 5 n 1000 times rev. 2.0, 08/02, page 734 of 788 item symbol min typ max unit test conditions wait time after swe-bit setting * 1 x1s wait time after esu-bit setting * 1 y 100 s wait time after e-bit setting * 1 , * 6 z 10 100 ms wait time after e-bit clear * 1 a 10 s wait time after esu-bit clear * 1 b 10 s wait time after ev-bit setting * 1 g 20 s wait time after dummy write * 1 e 2s wait time after ev-bit clear * 1 h 4s wait time after swe-bit clear * 1 q 100 s erase maximum erase count * 1 , * 6 , * 7 n 120 times notes: 1. set the times according to the program/erase algorithms. 2. programming time per 128 bytes (shows the total period for which the p-bit in flmcr1 is set. it does not include the programming verification time.) 3. block erase time (shows the total period for which the e-bit in flmcr1 is set. it does not include the erase verification time.) 4. maximum programming time (t p (max)) t p (max) = (wait time after p-bit setting (z1) + (z3)) 6 + wait time after p-bit setting (z2) ((n) C 6) 5. the maximun number of writes (n) should be set according to the actual set value of z1, z2 and z3 to allow programming within the maximum programming time (t p (max)). the wait time after p-bit setting (z1, z2, and z3) should be alternated according to the number of writes (n) as follows: 1 n 6 z1 = 30 s, z3 = 10 s 7 n 1000 z2 = 200 s 6. maximum erase time (t e (max)) t e (max) = wait time after e-bit setting (z) maximum erase count (n) 7. the maximum number of erases (n) should be set according to the actual set value of z to allow erasing within the maximum erase time (t e (max)). rev. 2.0, 08/02, page 735 of 788 28.2.7 usage notes 1. both of the f-ztat version and masked-rom version products satisfy the electrical characteristics described in this manual, however, due to the differences in the manufacturing process, on-chip roms, or layout patterns, the actual electrical characteristics, operation margin, and noise margin may be changed. when the f-ztat version was used for system evaluation, and switching from the f-ztat version to the mask-rom version is made, the equivalent evaluation should be performed for the mask-rom version. 2. internal step-down products the h8s/2148 b-masked product (hd64f2148b) includes an internal step-down circuit to step down the microprocessor internal power supply voltage to the appropriate level. one or two (in parallel) internal voltage regulating capacitors (0.47 f) should be inserted between the internal step-down pin (vcl pin) and vss pin. the method of connecting the external capacitor(s) is shown in figure 27-31. for the 5-v and 4-v version products whose power supply (vcc) voltage exceeds 3.6 v, do not connect the vcc power supply to the vcl pin of the internal step-down product. (connect the vcc power supply to the vcc1 pin, as usual.) for the 3-v version product whose power supply (vcc) voltage is 3.6 v or less, connect the system power supply to the vcl pin together with the vcc1 pins. when switching from the f-ztat version product without the internal step-down function to the f-ztat b-masked product with the internal step-down function, note that the vcl pin is allocated to the same location as the vcc2 pin of the product without the internal step-down function. therefore, the difference in the circuits between before and after the switchover should be considered when designing the pc board patterns. rev. 2.0, 08/02, page 736 of 788 external capacitor for power supply regulation 0.47 f (one, or two in parallel) vcl product with internal step-down function vcl product without internal step-down function vcc power supply vss vss 0.01 f bypass capacitor 10 f the vcc power supply should not be connected to the vcl pin of the product with the internal step-down function. (connect the vcc power supply to other vcc1 pins as usual.) be sure to connect power supply regulating capacitor(s) to the vcl pin. one or two (parallel) 0.47-f multilayer capacitors should be used near the vcl pin. for 3-v products used with the voltage of 3.6 v or less, connect the vcc power supply in the same way as the products without the internal step-down function. < product with internal step-down function > hd64f2148b the vcc2 pin of the product without the internal step-down function is allocated at the same location as the vcl pin of the product with the internal step-down function. it is recommended that a bypass capacitor be connected to the power supply pins. (the values are reference values.) < product without internal step-down function > hd64f2145bv hd64f2148bv figure 28.5 connection of vcl capacitor 28.3 timing chart 28.3.1 clock timing the clock timings are shown below. t ch t cyc t cf t cl t cr ? figure 28.6 system clock timing rev. 2.0, 08/02, page 737 of 788 t osc1 t osc1 extal v cc ? t dext t dext figure 28.7 oscillation settling timing ? nmi (i = 0, 1, 2, 6, 7) t osc2 figure 28.8 oscillation setting timing (exiting software standby mode) rev. 2.0, 08/02, page 738 of 788 28.3.2 control signal timing the control signal timings are shown below. t resw t ress ? t ress figure 28.9 reset input timing t irqs ? t nmis t nmih edge input (i = 7 to 0) nmi t irqs t irqh (i = 7 to 0) level input (i = 7 to 0) t nmiw t irqw figure 28.10 interrupt input timing rev. 2.0, 08/02, page 739 of 788 28.3.3 bus timing the bus timings are shown below. t rsd2 ? t 1 t ad t csd * a23 to a0, * note: * and are the same pin. the function is selected by the iose bit in syscr. t asd (read) t 2 t as t asd t acc2 t rsd1 t acc3 t rds t wrd2 t wrd2 t wdd t wsw1 t wdh d15 to d0 (read) , (write) d15 to d0 (write) t ah t ah t as t as t rdh figure 28.11 basic bus timing (two-state access) rev. 2.0, 08/02, page 740 of 788 t rsd2 ? t 2 * a23 to a0, * t asd (read) t 3 t as t asd t acc4 t rsd1 t acc5 t rds t wrd1 t wrd2 t wds t wsw2 t wdh d15 to d0 (read) , (write) d15 to d0 (write) t 1 t wdd t ad t csd note: * and are the same pin. the function is selected by the iose bit in syscr. t ah t ah t as t rdh figure 28.12 basic bus timing (three-state access) rev. 2.0, 08/02, page 741 of 788 ? t w * a23 to a0, * (read) t 3 d15 to d0 (read) , (write) d15 to d0 (write) t 2 t wts t 1 t wth t wts t wth note: * and are the same pin. the function is selected by the iose bit in syscr. figure 28.13 basic bus timing (three-state access with one wait state) rev. 2.0, 08/02, page 742 of 788 t rsd2 ? t 1 * a23 to a0, * t 2 t ah t acc3 t rds d15 to d0 (read) t 2 or t 3 t as t 1 t asd t asd t rdh t ad (read) note: * and are the same pin. the function is selected by the iose bit in syscr. figure 28.14 burst rom access timing (two-state access) t rsd2 ? t 1 * a23 to a0, * t 1 t acc1 d15 to d0 (read) t 2 or t 3 t rdh t ad (read) t rds note: * and are the same pin. the function is selected by the iose bit in syscr. figure 28.15 burst rom access timing (one-state access) rev. 2.0, 08/02, page 743 of 788 28.3.4 on-chip peripheral module timing the on-chip peripheral module timings are shown below. ? ports 1 to 9, a, and b (ports c to g are added in h8s/2160b and h8s/2161b) (read) t 2 t 1 t pwd t prh t prs ports 1 to 6, 8, 9, a, and b (ports c to f are added in h8s/2160b and h8s/2161b) (write) figure 28.16 i/o port input/output timing ? t ftis t ftod ftoa, ftob ftia, ftib, ftic, ftid figure 28.17 frt input/output timing rev. 2.0, 08/02, page 744 of 788 ? t ftcs ftci t ftcwh t ftcwl figure 28.18 frt clock input timing ? tmo0, tmo1 tmox t tmod figure 28.19 8-bit timer output timing ? tmci0, tmci1 tmix, tmiy t tmcs t tmcs t tmcwh t tmcwl figure 28.20 8-bit timer clock input timing ? tmri0, tmri1 tmix, tmiy t tmrs figure 28.21 8-bit timer reset input timing rev. 2.0, 08/02, page 745 of 788 ? pw15 to pw0, pwx1, pwx0 t pwod figure 28.22 pwm, pwmx output timing sck0 to sck2 t sckw t sckr t sckf t scyc figure 28.23 sck clock input timing txd0 to txd2 (transmit data) rxd0 to rxd2 (receive data) sck0 to sck2 t rxs t rxh t txd figure 28.24 sci input/output timing (synchronous mode) ? t trgs figure 28.25 a/d converter external trigger input timing rev. 2.0, 08/02, page 746 of 788 t resow t resd t resd ? figure 28.26 wdt output timing ( 5(62 5(62 5(62 5(62 ) /ha0 hdb7 to hdb0 valid data hirqi * (i = 1, 11, 12, 3, 4) t har t hrpw t hra t hrf t hirq t hrd /ha0 hdb7 to hdb0 ga20 t haw t hwpw t hwa t hwd t hga t hdw host interface (xbs) read timing note: * the rising edge timing is the same as the port 4 and port b output timing. see figure 28.16. host interface (xbs) write timing figure 28.27 host interface (xbs) timing rev. 2.0, 08/02, page 747 of 788 1. reception ? kclk/ kd * kclk/ kd * t kbis t kbih transmission (b) t kbf 2. transmission (a) ? kclk/ kd * t1 t2 t kbod note: ? shown here is the clock scaled by 1/n when the operating mode is active medium-speed mode. * kclk: ps2ac to ps2cc kd: ps2ad to ps2cd figure 28.28 keyboard buffer controller timing rev. 2.0, 08/02, page 748 of 788 sda0, sda1 v il v ih t buf p * p * s * t stah t sclh t sr t scll t scl t sf t sdah sr * t sdas t stas t sp t stos note: * s, p, and sr indicate the following conditions. s: p: sr: start condition stop condition retransmission start condition scl0, scl1 figure 28.29 i 2 c bus interface input/output timing lclk lad3 to lad0, serirq, (transmit signal) lad3 to lad0, serirq, (receive signal) t txd t rxh t rxs t off lad3 to lad0, serirq, (transmit signal) t lcyc t lckh lclk t lckl figure 28.30 host interface (lpc) timing rev. 2.0, 08/02, page 749 of 788 testing voltage: 0.4vcc 50pf figure 28.31 tester measurement condition rev. 2.0, 08/02, page 750 of 788 rev. 2.0, 08/02, page 751 of 788 appendix a i/o port states in each processing state table a.1 i/o port states in each processing state port name pin name mcu operating mode reset hardware standby mode software standby mode watch mode sleep mode sub- sleep mode subactive mode program execution state 1 l a7 to a0 a7 to a0 2, 3 (expe = 1) address output/ input port address output/ input port port 1 a7 to a0 2, 3 (expe = 0) t t kept * kept * kept * kept * i/o port i/o port 1 l a15 to a8 a15 to a8 2, 3 (expe = 1) address output/ input port address output/ input port port 2 a15 to a8 2, 3 (expe = 0) t t kept * kept * kept * kept * i/o port i/o port 1 2, 3 (expe = 1) t t t t d15 to d8 d15 to d8 port 3 d15 to d8 2, 3 (expe = 0) tt kept kept kept kept i/o port i/o port 1 2, 3 (expe = 1) port 4 2, 3 (expe = 0) t t kept kept kept kept i/o port i/o port 1 2, 3 (expe = 1) port 5 2, 3 (expe = 0) t t kept kept kept kept i/o port i/o port 1 2, 3 (expe = 1) port 6 2, 3 (expe = 0) t t kept kept kept kept i/o port i/o port 1 2, 3 (expe = 1) port 7 2, 3 (expe = 0) t t t t t t input port input port 1 2, 3 (expe = 1) port 8 2, 3 (expe = 0) t t kept kept kept kept i/o port i/o port 1 2, 3 (expe = 1) t/kept t/kept t/kept t/kept :$,7 / i/o port :$,7 / i/o port port 97 :$,7 2, 3 (expe = 0) tt kept kept kept kept i/o port i/o port rev. 2.0, 08/02, page 752 of 788 port name pin name mcu operating mode reset hardware standby mode software standby mode watch mode sleep mode sub- sleep mode subactive mode program execution state 1 clock output 2, 3 (expe = 1) port 96 ? excl 2, 3 (expe = 0) t t [ddr = 1] h [ddr = 0] t excl input [ddr = 1] clock output [ddr = 0] t excl input excl input clock output/ excl input/ input port 1h 2, 3 (expe = 1) hhhh $6 , +:5 , 5' $6 , +:5 , 5' ports 95 to 93 $6 , +:5 , 5' 2, 3 (expe = 0) t t kept kept kept kept i/o port i/o port 1 2, 3 (expe = 1) ports 92 to 91 2, 3 (expe = 0) t t kept kept kept kept i/o port i/o port 1 2, 3 (expe = 1) h/kept h/kept h/kept h/kept /:5 / i/o port /:5 / i/o port port 90 /:5 2, 3 (expe = 0) tt kept kept kept kept i/o port i/o port 1 i/o port i/o port 2, 3 (expe = 1) a23 to a16/ i/o port a23 to a16/ i/o port port a a23 to a16 2, 3 (expe = 0) tt kept * kept * kept * kept * i/o port i/o port 1 2, 3 (expe = 1) t/kept t/kept t/kept t/kept d7 to d0/ i/o port d7 to d0/ i/o port port b d7 to d0 2, 3 (expe = 0) tt kept kept kept kept i/o port i/o port 1 2, 3 (expe = 1) ports c to g (h8s/2160b, h8s/2161b) 2, 3 (expe = 0) t t kept kept kept kept i/o port i/o port legend h: high l: low t: high-impedance state kept: input ports are in the high-impedance state (when ddr = 0 and pcr = 1, input pull-up moss remain on). output ports maintain their previous state. depending on the pins, the on-chip peripheral modules may be initialized and the i/o port function determined by ddr and dr used. ddr: data direction register note: * in the case of address output, the last address accessed is retained. rev. 2.0, 08/02, page 753 of 788 appendix b product codes product type product code mark code package (hitachi package code) flash memory version (3-v version) hd64f2161bv f2161bvte10 masked rom version (3-v version) hd6432161bv 2161bv( *** )te h8s/2161b (3-v version with on-chip i 2 c) hd6432161bvw 2161bvw( *** )te flash memory version (3-v version) hd64f2160bv f2160bvte10 masked rom version (3-v version) hd6432160bv 2160bv( *** )te h8s/2160b (3-v version with on-chip i 2 c) hd6432160bvw 2160bvw( *** )te 144-pin tqfp (tfp-144) f2141bvfa10 100-pin qfp (fp-100b) h8s/2141b flash memory version (3-v version) hd64f2141bv f2141bvte10 100-pin tqfp (tfp-100b) f2140bvfa10 100-pin qfp (fp-100b) h8s/2140b flash memory version (3-v version) hd64f2140bv f2140bvte10 100-pin tqfp (tfp-100b) f2145bvfa10 100-pin qfp (fp-100b) h8s/2145b flash memory version (3-v version) hd64f2145bv f2145bvte10 100-pin tqfp (tfp-100b) f2148bvfa10 100-pin qfp (fp-100b) flash memory version (3-v version) hd64f2148bv f2148bvte10 100-pin tqfp (tfp-100b) f2148bfa20 100-pin qfp (fp-100b) h8s/2148b flash memory version (5-v version) hd64f2148b f2148bte20 100-pin tqfp (tfp-100b) legend ( *** ): rom code note: * some products above are in the developing or planning stage. please contact hitachi agency to conform the present state of each product. rev. 2.0, 08/02, page 754 of 788 appendix c package dimensions hitachi code jedec eiaj weight (reference value) fp-100b conforms 1.2 g unit: mm * dimension including the plating thickness base material dimension 0.10 16.0 0.3 1.0 0.5 0.2 16.0 0.3 3.05 max 75 51 50 26 1 25 76 100 14 0? C 8? 0.5 0.08 m * 0.22 0.05 2.70 * 0.17 0.05 0.12 +0.13 C0.12 1.0 0.20 0.04 0.15 0.04 figure c.1 package dimensions (fp-100b) rev. 2.0, 08/02, page 755 of 788 hitachi code jedec jeita mass (reference value) tfp-100b conforms 0.5 g * dimension including the plating thickness base material dimension 16.0 0.2 14 0.08 0.10 0.5 0.1 16.0 0.2 0.5 0.10 0.10 1.20 max * 0.17 0.05 0? C 8? 75 51 125 76 100 26 50 m * 0.22 0.05 1.0 1.00 1.0 0.20 0.04 0.15 0.04 unit: mm figure c.2 package dimensions (tfp-100b) rev. 2.0, 08/02, page 756 of 788 hitachi code jedec eiaj weight (reference value) tfp-144 conforms 0.6 g unit: mm * dimension including the plating thickness base material dimension 108 73 136 0? C 8? 0.08 0.07 m 18.0 0.2 72 144 109 37 18.0 0.2 * 0.18 0.05 0.4 1.20 max 1.0 0.5 0.1 16 1.00 0.10 0.05 * 0.17 0.05 0.16 0.04 0.15 0.04 1.0 figure c.3 package dimensions (tfp-144) rev. 2.0, 08/02, page 757 of 788 main revisions and additions in this edition item page revisions (see manual for details) cover cover the type name hd64f2145b deleted. (error) (correction) model rom remarks model rom remarks hd64f2161bv * 128 kbytes under development hd64f2161bv * 128 kbytes hd64f2160bv * 64 kbytes under development hd64f2160bv * 64 kbytes hd64f2141bv * 128 kbytes under development hd64f2141bv * 128 kbytes hd64f2140bv * 64 kbytes under development hd64f2140bv * 64 kbytes hd64f2148bv * 128 kbytes under development hd64f2148bv * 128 kbytes hd64f2148b 128 kbytes under development hd64f2148b 128 kbytes section 1 overview 1.1 overview on-chip memory 2 note: * 3-v version product 1.2 block diagram figure 1.1 internal block diagram of h8s/2140b, h8s/2141b, h8s/2145b, and h8s/2148b 3 (error) pb7/d7/ pb6/d6/ pb5/d5/ pb4/d4/ pb3/d3/ / pb2/d2/ / pb1/d1/ /hirq4/lsci * pb0/d0/ /hirq3/ * port b note: not supported by the h8s/2148b and h8s/2145b (5-v version). (correction) pb7/d7/ * pb6/d6/ * pb5/d5/ * pb4/d4/ * pb3/d3/ * / pb2/d2/ * / pb1/d1/ * /hirq4/lsci * pb0/d0/ * /hirq3/ * port b the lpc function and the pin function are not supported by the h8s/2148b. note: rev. 2.0, 08/02, page 758 of 788 item page revisions (see manual for details) 1.3 pin arrangement and functions 1.3.1 pin arrangement figure 1.3 pin arrangement of h8s/2140b, h8s/2141b, h8s/2145b, and h8s/2148b 5 (error) 57 pb7/d7/ :8( : , 58 pb6/d6/ :8( 9 , 68 pb5/d5/ :8( 8 , 69 pb4/d4/ :8( 7 , 80 pb3/d3/ :8( 6 , 81 pb2/d2/ :8( 5 , 90 pb1/d1/ :8( 4 , 91 pb0/d0/ :8( 3 note: * not supported by the h8s/2148b. (correction) 57 pb7/d7/ :8( : * , 58 pb6/d6/ :8( 9 * , 68 pb5/d5/ :8( 8 * , 69 pb4/d4/ :8( 7 * , 80 pb3/d3/ :8( 6 * , 81 pb2/d2/ :8( 5 * , 90 pb1/d1/ :8( 4 * , 91 pb0/d0/ :8( 3 * note: * the lpc function and the :8( pin function are not supported by the h8s/2148b. pin name pin no. expanded modes single-chip modes fp-100b tfp-100b mode 1 mode 2, mode 3 (expe = 1) mode 2, mode 3 (expe = 0) 57 pb7/d7/ :8( : * pb7/d7/ :8( : * pb7/ :8( : * 58 pb6/d6/ :8( 9 * pb6/d6/ :8( 9 * pb6/ :8( 9 * 68 pb5/d5/ :8( 8 * pb5/d5/ :8( 8 * pb5/ :8( 8 * 69 pb4/d4/ :8( 7 * pb4/d4/ :8( 7 * pb4/ :8( 7 * 80 pb3/d3/ :8( 6 * pb3/d3/ :8( 6 * pb3/ :8( 6 * / &6 7 81 pb2/d2/ :8( 5 * pb2/d2/ :8( 5 * pb2/ :8( 5 * / &6 6 90 pb1/d1/ :8( 4 * pb1/d1/ :8( 4 * pb1/hirq4/ :8( 4 * /lsci * 91 pb0/d0/ :8( 3 * pb0/d0/ :8( 3 * pb0/hirq3/ # :8( 3 * / /60, * 1.3.2 pin functions in each operating mode table 1.1 pin functions of h8s/2140b, h8s/2141b, h8s/2145b, and h8s/2148b in each operating mode 9 to 11 note: the (b) in pin no. means the vccb drive and the (n) in pin no.means the nmos push-pull/open-drain drive. * the lpc function and the :8( pin function are not supported by the h8s/2148b. rev. 2.0, 08/02, page 759 of 788 item page revisions (see manual for details) table 1.2 pin functions of h8s/2160b and h8s/2161b in each operating mode 17 added. note: the (b) in pin no. means the vccb drive and the (n) in pin no. means the nmos push-pull/open-drain drive. 18 name and function of xtal, extal in clock amended. (error) see section 24, clock pulse generator, for typical connection diagrams. (correction) see section 25, clock pulse generator, for typical connection diagrams. 22 name and function of serirq in host interface (lpc) amended. (error) input/output pin for lpc serialized host interrupts (hirq1, hirq6, hirq9 to hirq12). (correction) input/output pin for lpc serialized host interrupts (hirq1, smi, hirq6, hirq9 to hirq12). (error) (correction) type symbol name and function type symbol name and function p47-p40 eight input/output pins. p47-p40 eight input/output pins. (the output type of p42 is nmos push-pull.) p52-p50 three input/output pins. p52-p50 three input/output pins. (the output type of p52 is nmos push-pull.) p86-p80 seven input/output pins. p86-p80 seven input/output pins. (the output type of p86 is nmos push-pull.) p97-p90 eight input/output pins. p97-p90 eight input/output pins. (the output type of p97 is nmos push-pull.) i/o ports pg7-pg0 eight input/output pins. i/o ports pg7-pg0 eight input/output pins. (the output type of ppg7-pg0 in the h8s/2160b and the h8s/2161b is nmos push-pull.) 1.3.3 pin functions table 1.3 pin functions 24, 25 rev. 2.0, 08/02, page 760 of 788 item page revisions (see manual for details) section 3 mcu operating modes 3.2.2 system control register (syscr) 66 description of bit 1 amended. (error) keyboard buffer controller (correction) keyboard matrix interrupt section 4 exception handling 4.7 usage note figure 4.3 operation when sp value is odd 84 corrected. sp ccr sp sp r1l h'ffeffa h'ffeffb h'ffeffc h'ffeffd h'ffefff pc pc trapa instruction executed sp set to h'ffefff data saved above sp mov.b r1l, @-er7 executed contents of ccr lost address section 5 interrupt controller 5.1 features figure 5.1 block diagram of interrupt controller 86 (error) (correction) kin and wue input kmimr wuemr kin input wue input kim and wue input kmimr wuemr kin input wue input 5.3.1 interrupt control registers a to c (icra to icrc) 88 (error) the icr registers set interrupt control levels for interrupts other than nmi. (correction) the icr registers set interrupt control levels for interrupts other than nmi and address breaks. bits 7 to 0 r/w description r/(w) * 2 when interrupt exception handling is executed when low-level detection is set and ,54q input is high (n = 7 to 0) * 1 when irqn interrupt exception handling is executed when falling- edge, rising-edge, or both-edge detection is set * 1 5.3.6 irq status register (isr) 92 notes: 1. when a product, in which a dtc is incorporated, is used, the corresponding flag bit is not automatically cleared even when exception handing is executed. for details, refer to section 5.8.4, setting on a product incorporating dtc. 2. only 0 can be written, for flag clearing. rev. 2.0, 08/02, page 761 of 788 item page revisions (see manual for details) 92 (error) the kmimr and wuemr registers (correction) the kmimra, kmimr, and wuemr b registers 5.3.7 keyboard matrix interrupt mask registers (kmimra, kmimr) wake-up event interrupt mask register (wuemrb) 93 added. wuemrb * note: * not supported by the h8s/2148b. 5.4 interrupt sources 5.4.1 external interrupts 95 description added to irq7 to irq0 interrupts. interrupt control levels can be specified by the icr settings. table 5.3 interrupt sources, vector addresses, and interrupt priorities 98 (error) origin of interrupt source name vector number vector address normal mode advanced mode ? reserved for system use erri (transfer error) ibf1 (idr1 reception completion) ibf2 (idr2 reception completion) ibf3 (idr3 reception completion) 100 101 102 103 112 113 114 h'00c8 h'00ca h'00cc h'00ce h'00d0 h'00da h'00dc h'00de h'000190 h'000194 h'000198 h'00019c h'0001b0 h'0001b4 h'0001b8 h'0001bc lpc * (correction) origin of interrupt source name vector number vector address normal mode advanced mode ? reserved for system use erri (transfer error) ibf1 (idr1 reception completion) ibf2 (idr2 reception completion) ibf3 (idr3 reception completion) 100 to 107 108 109 110 111 h'00c8 to h'00d6 h'00d8 h'00da h'00dc h'00de h'000190 to h'0001ac h'0001b0 h'0001b4 h'0001b8 h'0001bc lpc * 5.6.1 interrupt control mode 0 99 in interrupt control mode 0, interrupt requests other than nmi and address breaks corrected. object of access external device 8-bit bus 16-bit bus 2-state access 3-state access 2-state access 3-state access 46 + 2m 2 3 + m 5.6.4 interrupt response times table 5.6 number of states in interrupt handling routine execution status 105 rev. 2.0, 08/02, page 762 of 788 item page revisions (see manual for details) 5.6.5 dtc activation by interrupt figure 5.8 dtc and interrupt controller 106 corrected. determination of priority cpu i,ui cpu interrupt request vector number 5.7 address break 107 to 110 added. section 6 bus controller 6.5.4 wait control figure 6.13 example of wait state insertion timing (pin wait mode) 131 corrected. , write data write data bus 6.7 idle cycle figure 6.16 examples of idle cycle operation 133 corrected. t 1 address bus ? bus cycle a data bus t 2 t 3 t 1 t 2 bus cycle b long output floating time data collision (a) no idle cycle insertion t 1 address bus ? bus cycle a data bus t 2 t 3 t i t 1 bus cycle b (b) idle cycle insertion t 2 , , section 7 data transfer controller (dtc) 7.1 features 135 deleted. usable for scan operations of cin7 to cin0 dtc operates in high-speed mode even when the lsi is in medium-speed mode 7.2.2 dtc mode register b (mrb) 138 description of bit 6 (disel) added. when this bit is set to 1, a cpu interrupt request is generated every time data transfer ends (the dtc clears the interrupt source flag for the activation source). when this bit is cleared to 0, a cpu interrupt request is generated only when the specified number of data transfer ends (the dtc does not clear the interrupt source flag for the activation source). rev. 2.0, 08/02, page 763 of 788 item page revisions (see manual for details) corrected. activation source origin vector number dtc vector address iic_1 94 dtced 3 108 dtcee3 109 dtcee2 110 dtcee1 lpc * 2 111 dtcee0 7.4 location of register information and dtc vector table table 7.1 interrupt sources, dtc vector addresses, and corresponding dtces 143 7.8.1 module stop mode setting 154 description amended. (error) for details, refer to section 25, power-down modes. (correction) for details, refer to section 26, power-down modes. 157, 159 i/o status of port 6, port a, and port b description of on-chip input pull-up moss added. mode 2, mode 3 port mode 1 (expe = 1) (expe = 0) port 9 p97/ :$,7 2 sda0 p96/?/excl $6 / ,26 +:5 5' p92/ ,54 3 p91/ ,54 4 p90/ /:5 / ,54 5 / $'75* p97/sda0 p96/?/excl p95/ &6 4 p94/ ,2: p93/ ,25 p92/ ,54 3 p91/ ,54 4 p90/ ,54 5 / $'75* / (&6 5 port b pb7/d7/ :8( : * pb6/d6/ :8( 9 * pb5/d5/ :8( 8 * pb4/d4/ :8( 7 * pb3/d3/ :8( 6 * pb2/d2/ :8( 5 * pb1/d1/ :8( 4 * pb0/d0/ :8( 3 * pb7/ :8( : * pb6/ :8( 9 * pb5/ :8( 8 * pb4/ :8( 7 * pb3/ :8( 6 * / &6 7 pb2/ :8( 5 * / &6 6 pb1/ :8( 4 * /hirq4/lsci * pb0/ :8( 3 * /hirq3/ /60, * section 8 i/o ports table 8.1 port functions of h8s/2140b, h8s/2141b, h8s/2145b, and h8s/2148b 158, 159 note: * not supported by the h8s/2148b. rev. 2.0, 08/02, page 764 of 788 item page revisions (see manual for details) 8.4.4 pin functions 8.9.3 pin functions 8.12.4 pin functions 168 184 to 186 200 to 202 note: not supported by the h8s/2148b. 8.6.1 port 5 data direction register (p5ddr) 174 descriptions of bits 2 to 0 added. the corresponding port 5 pins are output ports when p5ddr bits are set to 1, and input ports when cleared to 0. 8.11 port a 191 (error) port a pin functions are the same in all operating modes. (correction) port a pin functions change according to the operating mode. 8.11.1 port a data direction register (paddr) 192 description added. 8.11.3 port a input data register (papin) 193 description amended. reading papin always returns the pin states. papin has the same address as paddr. if a write is performed, the port a settings will change. 8.13 additional overview for h8s/2160b and h8s/2161b 203 (error) ports c, d, e, and f have a built-in mos input pull-up function. on ports c, d, e, f, and g, whether the mos input pull-up is on or off is controlled by the corresponding ddr and dr. (correction) ports c, d, e, and f have an on-chip input pull-up mos function. on ports c, d, e, and f, whether the input pull-up mos is on or off is controlled by the corresponding ddr and odr. (error) (correction) v ss -side ch. driver n-ch. driver v ss -side n-ch. driver p-ch. driver 8.15.5 pin functions 213 rev. 2.0, 08/02, page 765 of 788 item page revisions (see manual for details) 8.16.4 port g nch-od control register (pgnocr) 216 bit description amended. 1: vss-side n-channel open drain section 9 8-bit pwm timer (pwm) 9.3.2 pwm data registers (pwdr0 to pwdr15) 222 description added. pwdr0 to pwdr15 are initialized to h'00. 9.5 usage note 9.5.1 module stop mode setting 226 added. section 10 14-bit pwm timer (pwmx) 10.3.1 pwm (d/a) counters h and l (dacnth, dacntl) 228 description added. since dacnt consists of 16-bit data, dacnt transfers data to the cpu via the temporary register (temp). 10.3.2 pwm (d/a) data registers a and b (dadra, dadrb) 230 description added. since dadr consists of 16-bit data, dadr transfers data to the cpu via the temporary register (temp). 10.5 operation 237 to 239 description of additional pulse added. 10.6 usage note 10.6.1 module stop mode setting 240 added. section 11 16-bit free- running timer (frt) 11.1 features figure 11.1 block diagram of 16-bit free- running timer 242 legend ocrdm: output compare register dm (16-bit) 11.3.7 timer control/status register (tcsr) 249 description of bit 1 amended. (error) overflow flag (correction) timer overflow rev. 2.0, 08/02, page 766 of 788 item page revisions (see manual for details) 11.7.1 conflict between frc write and clear figure 11.17 frc write- clear conflict 261 corrected. ? address frc address internal write signal counter clear signal frc n h'0000 t 1 t 2 write cycle of frc 11.7.3 conflict between ocr write and compare- match figure 11.20 conflict between ocrar/ocraf write and compare-match (when automatic addition function is used) 264 corrected. ? address ocrar (ocraf) address internal write signal automatic addition is not performed because compare-match signals are disabled. ocra n t1 t2 write cycle of ocrar/ocraf 11.7.5 module stop mode setting 266 added. rev. 2.0, 08/02, page 767 of 788 item page revisions (see manual for details) 267 (error) timer output controlled by two compare-match signals ? the timer output signal in each channel is controlled by two independent compare-match signals, enabling the timer to be used for various applications, such as the generation of pulse output or pwm output with an arbitrary duty cycle. (correction) timer output controlled by two compare-match signals ? the timer output signal in each channel is controlled by two independent compare-match signals, enabling the timer to be used for various applications, such as the generation of pulse output or pwm output with an arbitrary duty cycle. (the tmr_y does not have a timer output pin.) (error) cascading of two channels ? cascading of tmr_0 and tmr_1 (correction) cascading of tmr_0 and tmr_1 ? (tmr_y and tmr_x cannot be cascaded.) section 12 8-bit timer (tmr) 12.1 features 268 (error) figure 12.1 block diagram of 8-bit timers (tmr_0, tmr_1, tmr_x, and tmr_y) (correction) figure 12.1 block diagram of 8-bit timers (tmr_0 and tmr_1) figure 12.2 block diagram of 8-bit timers (tmr_y and tmr_x) 269 added. rev. 2.0, 08/02, page 768 of 788 item page revisions (see manual for details) (error) channel name symbol i/o function timer output tmo0 output output controlled by compare-match tmr_0 timer clock/reset input tmi0/extmi0 input external clock input (tmci0)/external reset input (tmri0) for the counter timer output tmo1 output output controlled by compare-match tmr_1 timer clock/reset input tmi1/extmi1 input external clock input (tmci1)/external reset input (tmri1) for the counter tmr_y timer clock/reset input tmiy/extmiy input external clock input (tmciy)/external reset input (tmriy) for the counter timer output tmox output output controlled by compare-match tmr_x timer clock/reset input tmix/extmix input external clock input (tmcix)/external reset input (tmrix) for the counter (correction) channel name symbol i/o function timer output tmo0 output output controlled by compare-match timer clock input tmci0 input external clock input for the counter tmr_0 timer reset input tmri0 input external reset input for the counter timer output tmo1 output output controlled by compare-match timer clock input tmci1 input external clock input for the counter tmr_1 timer reset input tmri1 input external reset input for the counter tmr_y timer clock/reset input vsynci/tmiy (tmciy/tmriy) input external clock input/external reset input for the counter timer output tmox output output controlled by compare-match tmr_x timer clock/reset input hfbacki/tmix (tmcix/tmrix) input external clock input/external reset input for the counter 12.2 input/output pins table 12.1 pin configuration 270 12.3.5 timer control/status register (tcsr) 278 tcsr_y bit 4 the initial value is amended to 0. rev. 2.0, 08/02, page 769 of 788 item page revisions (see manual for details) 12.3.5 timer control/status register (tcsr) 279 tcsr_y (error) bits 3 and 2 these bits specify how the tmoy pin output level is to be changed by compare-match b of tcorb_y and tcnt_y. bits 1 and 0 these bits specify how the tmoy pin output level is to be changed by compare-match a of tcora_y and tcnt_y. note: * only 0 can be written, for flag clearing. (correction) bits 3 and 2 these bits specify how the tmoy pin * 2 output level is to be changed by compare-match b of tcorb_y and tcnt_y. bits 1 and 0 these bits specify how the tmoy pin * 2 output level is to be changed by compare-match a of tcora_y and tcnt_y. notes: 1. only 0 can be written, for flag clearing. 2. this product does not have a tmoy external output pin. (error) bit bit name description 0 is input select selects an internal synchronization signal (ivg signal) or timer clock/reset input pin (tmiy or extmiy) as the signal source of external clock/reset input for the tmry counter. 0: ivg signal is selected 1: tmiy or extmiy (tmciy/tmriy) is selected (correction) bit bit name description 0 is input select selects an internal synchronization signal (ivg signal) or timer clock/reset input pin vsynci/tmiy (tmciy/tmriy) as the signal source of external clock/reset input for the tmr_y counter. 0: ivg signal is selected 1: vsynci/tmiy (tmciy/tmriy) is selected 12.3.9 timer input select register (tisr) 282 rev. 2.0, 08/02, page 770 of 788 item page revisions (see manual for details) 12.5.1 tcnt count timing 283 (error) figure 12.5 count timing for external clock input (correction) figure 12.5 count timing for external clock input (both edges) 12.7 input capture operation figure 12.13 input capture signal selection 289 (error) tmix pin tmri1 pin tmci1 pin polarity inversion polarity inversion polarity inversion signal selector tmrix tmr_x hfinv, hiinv simod1, simod0 icst (correction) tmix pin tmri1 pin tmci1 pin polarity inversion polarity inversion polarity inversion signal selector tmrix tmr_x hfinv, hiinv simod1, simod0 icst 12.9 usage notes 12.9.7 module stop mode setting 296 added. bit description 7 6 5 4 hoe: 0: the p44/tmo1/hirq1/hsynco pin functions as the p44/tmo1/ hirq1 pin 1: the p44/tmo1/hirq1/hsynco pin functions as the hsynco pin cloe: 0: the p64/ftic/cin4/ .,1 7 / clampo pin functions as the p64/ftic/ cin4/ .,1 7 pin 1: the p64/ftic/cin4/ .,1 7 /clampo pin functions as the clampo pin section 13 timer connection 13.3.2 timer connection register o (tconro) 303 rev. 2.0, 08/02, page 771 of 788 item page revisions (see manual for details) (error) (correction) bit bit name bit bit name 2 predg 2 preqf 13.3.4 edge sense register (sedgr) 308 13.5 usage note 13.5.1 module stop mode setting 323 added. section 14 watchdog timer (wdt) 14.3.2 timer control/status register (tcsr) tcsr_0 329 cks2 to cks0, clock select 2 to 0 (error) selects the clock source to be input to. the overflow frequency for ? = 25 mhz is enclosed in parentheses. (correction) selects the clock source to be input to. the overflow frequency for ? = 10 mhz is enclosed in parentheses. (error) 000: ?/2 (frequency: 20.4 s) 001: ?/64 (frequency: 655.3 s) 010: ?/128 (frequency: 1.3 ms) 011: ?/512 (frequency: 5.2 ms) 100: ?/2048 (frequency: 20.9 ms) 101: ?/8192 (frequency: 83.8 ms) 110: ?/32768 (frequency: 335.5 ms) 111: ?/131072 (frequency: 1.34 s) (correction) 000: ?/2 (frequency: 51.2 s) 001: ?/64 (frequency: 1.64 ms) 010: ?/128 (frequency: 3.28 ms) 011: ?/512 (frequency: 13.1 ms) 100: ?/2048 (frequency: 52.4 ms) 101: ?/8192 (frequency: 209.7 ms) 110: ?/32768 (frequency: 0.84 s) 111: ?/131072 (frequency: 3.36 s) rev. 2.0, 08/02, page 772 of 788 item page revisions (see manual for details) 14.3.2 timer control/status register (tcsr) tcsr_1 331 cks2 to cks0, clock select 2 to 0 (error) selects the clock source to be input to tcnt. the overflow cycle for ? = 25 mhz and ?sub = 32.768 mhz is enclosed in parentheses. (correction) selects the clock source to be input to tcnt. the overflow cycle for ? = 10 mhz and ?sub = 32.768 khz is enclosed in parentheses. when pss = 0: (error) 000: ?/2 (frequency: 20.4 s) 001: ?/64 (frequency: 655.3 s) 010: ?/128 (frequency: 1.3 ms) 011: ?/512 (frequency: 5.2 ms) 100: ?/2048 (frequency: 20.9 ms) 101: ?/8192 (frequency: 83.8 ms) 110: ?/32768 (frequency: 335.5 ms) 111: ?/131072 (frequency: 1.34 s) (correction) 000: ?/2 (frequency: 51.2 s) 001: ?/64 (frequency: 1.64 ms) 010: ?/128 (frequency: 3.28 ms) 011: ?/512 (frequency: 13.1 ms) 100: ?/2048 (frequency: 52.4 ms) 101: ?/8192 (frequency: 209.7 ms) 110: ?/32768 (frequency: 0.84 s) 111: ?/131072 (frequency: 3.36 s) rev. 2.0, 08/02, page 773 of 788 item page revisions (see manual for details) 14.4.1 watchdog timer mode figure 14.2 watchdog timer mode (rst / 10, = 1) operation 333 corrected. tcnt value h'00 time h'ff wt/ = 1 tme = 1 write h'00 to tcnt wt/ = 1 tme = 1 write h'00 to tcnt 518 system clocks 132 system clocks and internal reset signals generated internal reset signal signal wt/ tme ovf overflow ovf = 1 * : timer mode select bit : timer enable bit : overflow flag note * after the ovf bit becomes 1, it is cleared to 0 by an internal reset. the xrst bit is also cleared to 0. 14.6 usage notes 14.6.7 ovf flag clear condition 338 deleted. 339 (error) module stop mode availability (correction) deleted. section 15 serial communication interface (sci and irda) 15.1 features 340 (error) a block diagram of sci_1 is shown in figure 15.1. (correction) a block diagram of the sci is shown in figure 15.1. 15.3.2 receive data register (rdr) 342 description added. after confirming that the rdrf bit in ssr is set to 1, read rdr for only once. rdr cannot be written to by the cpu. rdr is initialized to h'00. 15.3.3 transmit data register (tdr) 342 description added. although tdr can be read from or written to by the cpu at all times, to achieve reliable serial transmission, write transmit data to tdr for only once after confirming that the tdre bit in ssr is set to 1. tdr is initialized to h'ff. 16.3.5 i 2 c bus control register (iccr) 406 (error) assuming that the start condition has been issued. (correction) assuming that the stop condition has been issued. rev. 2.0, 08/02, page 774 of 788 item page revisions (see manual for details) 16.3.8 i 2 c bus extended control register (icxr) 422 [clearing conditions] (error) icdrf is set to 1 again. (correction) icdr e is set to 1 again. section 16 i 2 c bus interface (iic) (optional) 16.4.3 master transmit operation figure 16.9 example of operation timing in master transmit mode (mls = wait = 0) 429 (error) (correction) normal operation note: * data write timing in icdr incorrect operation [4] bbsy set to 1 scp cleared to 0 (start condition issuance) user processing icdrs address + r/ note: data write in icdr prohibited [4] bbsy set to 1 scp cleared to 0 (start condition issuance) user processing icdrs address + r/ 16.4.4 master receive operation 430 (error) the master device transmits data containing the slave address and r/ : (0: read) in the first frame following the start condition issuance in master transmit mode, selects the slave device, and then switches the mode for receive operation. (correction) the master device transmits data containing the slave address and r/ : ( 1: read) in the first frame following the start condition issuance in master transmit mode, selects the slave device, and then switches the mode for receive operation. rev. 2.0, 08/02, page 775 of 788 item page revisions (see manual for details) figure 16.13 example of stop condition issuance operation timing in master receive mode (mls = wait = 0, hnds = 1) 432 (error) sda (master output) sda (slave output) 2 14 3 6 5 8 7 9 9 78 a a bit 7 bit 1 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 iric icdrf icdrr scl (master output) data 3 data 2 data 1 data 2 data 3 [9] iric clear user processing irtr [8] [3] bit 0 [11] set bbsy=0 and scp=0 (stop condition instruction issuance) [4] iric clear [7] icdr read (data 2) [10] icdr read (data 3) [6] set ackb = 1 bit 0 start condition generation scl is fixed low until icdr is read scl is fixed low until icdr is read (correction) sda (master output) sda (slave output) 2 14 3 6 5 8 7 9 9 78 a a bit 7 bit 1 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 iric icdrf icdrr scl (master output) data 3 data 2 data 1 data 2 data 3 [9] iric clear user processing irtr [8] [3] bit 0 [11] set bbsy=0 and scp=0 (stop condition instruction issuance) [4] iric clear [7] icdr read (data 2) [10] icdr read (data 3) [6] set ackb = 1 bit 0 stop condition generation scl is fixed low until icdr is read scl is fixed low until stop condition is issued figure 16.17 example of stop condition issuance timing in master receive mode (mls = ackb = 0, wait = 1) 437 (error) (correction) sda (master output) sda (slave output) 2 14 3 9 8 a bit 7 bit 0 bit 6 bit 5 bit 4 iric irtr icdr scl (master output) data 2 data 1 data 2 data 3 [6] iric clear [8] wait for one clock pulse [11] iric clear user processing [3] [6] icdr read (data 2) [9] set trs=1 [7] set ackb=1 [4] irtr=1 [4] irtr=0 [3] sda (master output) sda (slave output) 2 14 3 9 8 a bit 7 bit 0 bit 6 bit 5 bit 4 iric irtr icdr scl (master output) data 2 data 1 data 2 data 3 [6] iric clear [8] wait for one clock pulse [11] iric clear user processing [3] [6] icdr read (data 2) [9] set trs=1 [7] set ackb=1 [4] irtr=1 [4] irtr=0 [3] 16.6 usage notes 454 1. description amended. rev. 2.0, 08/02, page 776 of 788 item page revisions (see manual for details) (error) (correction) item master transmit mode slave transmit mode item master transmit mode slave transmit mode transfer request processing after last frame processing 1st time: clearing by cpu 2nd time: end condition issuance by cpu automatic clearing on detection of end condition during transmission of dummy data (h'ff) transfer request processing after last frame processing 1st time: clearing by cpu 2nd time: stop condition issuance by cpu automatic clearing on detection of stop condition during transmission of dummy data (h'ff) 16.4.9 operation using dtc table 16.7 examples of operation using dtc 451 (error) (correction) item t cyc indication item t cyc indication t sdaso (slave) 1 t scll * 3 C3 t cyc * 2 (Ct sr )t sdaso (slave) 1 t scll * 3 C 12 t cyc * 2 (Ct sr ) 16.6 usage notes table 16.11 i 2 c bus timing (with maximum influence of tsr/tsf ) 457 notes: 2. value when the iicx bit is set to 1. when the iicx bit is cleared to 0, the value is (t scll C 6t cyc ). 3. calculated using the i 2 c bus specification values (standard mode: 4700 ns min.; high-speed mode: 1300 ns min.). 16.6.1 module stop mode setting 463 added. section 17 keyboard buffer controller 17.3 register descriptions 467 description deleted. the keyboard buffer controller has the following registers for each channel. for details on the module stop control register, refer to section 26.1.3, module stop control registers h and l (mstpcrh, mstpcrl). 17.5 usage notes 17.5.2 module stop mode setting 481 added. section 18 host interface x-bus interface (xbs) 18.1 features 483 (error) module stop mode setting (correction) deleted. 18.6 usage notes 18.6.2 module stop mode setting 501 added. rev. 2.0, 08/02, page 777 of 788 item page revisions (see manual for details) section 19 host interface lpc interface (lpc) 503, 517, 518, 523 (error) two-way register (correction) bidirectional data register 19.3 register descriptions 506 description added. the lpc has the following registers. the settings of xbs related bits do not affect the operation of this lsis lpc. however, for reasons relating to the configuration of the program development tool (emulator), when the lpc is used, bit hi12e in syscr2 should not be set to 1. for details, see section 3.2.2, system control register (syscr), and section 18.3.1, system control register 2 (syscr2). 19.3.4 input data registers (idr1 to idr3) 519 description added. the initial values of idr1 to idr3 are undefined. 19.3.5 output data registers (odr1 to odr3) 519 description added. the initial values of odr1 to odr3 are undefined. 19.3.6 bidirectional data registers (twr0 to twr15) 520 description added. the initial values of twr0 to twr15 are undefined. 19.3.7 status registers (str1 to str3) 520 description added the initial values of str1 to str3 are h'00. 19.6.1 module stop mode setting 551 added. section 20 d/a converter 20.3.1 d/a data registers 0 and 1 (dadr0, dadr1) 554 description added. dadr0 and dadr1 are initialized to h'00. 20.5.1 module stop mode setting 557 added. section 21 a/d converter 21.1 features 559 (error) module stop mode can be set (correction) deleted. rev. 2.0, 08/02, page 778 of 788 item page revisions (see manual for details) 563 description of bit 5 added. setting this bit to 1 starts a/d conversion. clearing this bit to 0 stops a/d conversion. in single mode, this bit is cleared to 0 automatically when conversion on the specified channel ends. 563 bit 4 (error) selects the a/d conversion operating mode. the setting of this bit must be made while conversion is halted. (correction) selects the a/d conversion operating mode. the setting of this bit must be made when conversion is halted (adst = 0). bit 3 (error) sets a/d conversion time. (correction) sets a/d conversion time. the input channel setting must be made when conversion is halted (adst = 0). 21.3.2 a/d control/status register (adcsr) 564 bits 2 to 0 (error) select analog input channels. the input channel setting must be made while conversion is halted. (correction) select analog input channels. the input channel setting must be made when conversion is halted (adst = 0). 21.4.3 input sampling and a/d conversion time figure 21.3 a/d conversion timing 568 (error) (correction) (1) write signal write signal (1) 21.7.6 module stop mode setting 574 added. section 22 ram 575 list added. section 23 rom 23.1 features size 577 list of rom capacitance added. rev. 2.0, 08/02, page 779 of 788 item page revisions (see manual for details) 23.11 programmer mode 604 note amended. note: * for 3-v and 5-v version products, set the programming voltage of the prom programmer to 3.3v. figure 23.13 memory map in programmer mode 604 corrected. h8s/2140b and h8s/2160b on-chip rom area mcu mode h'000000 programmer mode h'00000 h'00ffff undefined value output h'1ffff h'0ffff 23.12 usage notes 604 (error) if a voltage higher than the rated voltage is applied, the product may be fatally damaged. for a 3-v version product, use a prom programmer that supports the hitachi 64/128/256-kbyte flash memory on-chip mcu device at 3.3 v. do not set the programmer to hn28f101 or the programming voltage to 5.0 v. for a 5-v version product, use a prom programmer that supports the hitachi 128-kbyte flash memory on-chip mcu device at 5.0 v. do not set the programmer to hn28f101 or the programming voltage to 3.3 v. (correction) if a voltage higher than the rated voltage is applied, the product may be fatally damaged. for 3-v and 5-v version products, use a prom programmer that supports the hitachi 64/128/256-kbyte flash memory on-chip mcu device at 3.3 v. do not set the programmer to hn28f101 or the programming voltage to 5.0 v. section 24 masked rom 607 added. rev. 2.0, 08/02, page 780 of 788 item page revisions (see manual for details) 651 (error) (correction) register abbreviation bcr wscr icis1 rams icis0 ram0 bit 7 bit 6 register abbreviation bit 7 bit 6 bcr wscr _ _ icis0 _ section 27 list of registers 27.2 register bits 654 (error) (correction) register abbreviation sedgr bit 2 register abbreviation bit 2 sedgr preqf _ 27.3 register states in each operating mode 655, 658, 660 (error) (correction) 27.4 register select conditions 664 to 675 added. (error) item (correction) item input voltage (port c to g are added in the h8s/2160b and h8s/2161b.) input voltage (port c to f are added in the h8s/2160b and h8s/2161b.) input voltage (p97, p86, p52, p42) input voltage(p97, p86, p52, p42) (port g is added in the h8s/2160b and h8s/2161b.) section 28 electrical characteristics 677 rev. 2.0, 08/02, page 781 of 788 item page revisions (see manual for details) (error) (correction) item item input high voltage p97, p86, p52, p42 input high voltage p97, p86, p52, p42 (port g is added in the h8s/2160b and h8s/2161b.) output high voltage p97,p86, p52, and p42 * 4 output high voltage p97,p86, p52, and p42 * 4 (port g is added in the h8s/2160b and h8s/2161b) 28.1.2 dc characteristics table 28.2 dc characteristics (1) 679, 680 notes: 4. p52/sck0/scl0, p97/sda0, p86/sck1/scl1, p42/sck2/sda1, and port g are nmos push-pull outputs. when the scl0, sda0, scl1, or sda1 (ice = 1) pin is used as an output, it is nmos open-drain output. therefore an external pull-up resistor must be connected in order to output high level. p52/sck0, p97, p86/sck1, p42/sck2 (ice = 0), and port g high levels are driven by nmos. when the sck0, sck1 or sck2 pin is used as an output, an external pull-up resistor must be connected in order to output high level. 28.1.2 dc characteristics table 28.2 dc characteristics (3) when lpc function is used 683 table name added. (error) (correction) item max item max input high voltage v cc + 0.5 input high voltage 5.5 28.1.2 dc characteristics table 28.4 bus drive characteristics 685 (error) (correction) item symbol item symbol +:5 delay time 1 t wrd1 +:5 , /:5 delay time 1 t wrd1 +:5 delay time 2 t wrd2 +:5 , /:5 delay time 2 t wrd2 +:5 pulse width 1 t wsw1 +:5 , /:5 pulse width 1 t wsw1 +:5 pulse width 2 t wsw2 +:5 , /:5 pulse width 2 t wsw2 tables 28.7 and 28.22 bus timing (1) (normal mode) 689, 722 rev. 2.0, 08/02, page 782 of 788 item page revisions (see manual for details) 28.2.2 dc characteristics table 28.17 dc characteristics (1) 702 notes: 4. p52/sck0/scl0, p97/sda0, p86/sck1/scl1, p42/sck2/sda1, and port g are nmos push-pull outputs. when the scl0, sda0, scl1, or sda1 (ice = 1) pin is used as an output, it is nmos open- drain output. therefore, an external pull-up resistor must be connected in order to output high level. p52/sck0, p97, p86/sck1, p42/sck2 (ice = 0), and port g high levels are driven by nmos. when the sck0, sck1, or sck2 pin is used as an output, an external pull-up resistor must be connected in order to output high level. 8. the port a characteristics depend on v cc b, and the other pins characteristics depend on v cc in output mode. table 28.17 dc characteristics (3) table 28.17 dc characteristics (5) 706, 707, 711 notes: 4. p52/sck0/scl0, p97/sda0, p86/sck1/scl1, p42/sck2/sda1, and port g are nmos push-pull outputs. when the scl0, sda0, scl1, or sda1 (ice = 1) pin is used as an output, it is nmos open- drain output. therefore, an external pull-up resistor must be connected in order to output high level. p52/sck0, p97, p86/sck1, p42/sck2 (ice = 0), and port g high levels are driven by nmos. when the sck0, sck1, or sck2 pin is used as an output, an external pull-up resistor must be connected in order to output high level. 28.2.2 dc characteristics table 28.17 dc characteristics (7) (3-v version of h8s/2145bv) when lpc function is used 715 table name added. (error) (correction) item max item max input high voltage v cc + 0.5 input high voltage 5.5 28.2.2 dc characteristics table 28.19 bus drive characteristics 718 rev. 2.0, 08/02, page 783 of 788 item page revisions (see manual for details) 28.2.7 usage notes figure 28.5 connection of vcl capacitor 736 (error) (correction) vcc2 bypass capacitor product without internal step-down function bypass capacitor product without internal step-down function vss 0.01 10 vcl vss 0.01 10 28.3.4 on-chip peripheral module timing figure 28.16 i/o port input/output timing 743 corrected. ? ports 1 to 9, a, and b (ports c to g are added in h8s/2160b and h8s/2161b) (read) t 2 t 1 t pwd t prh t prs ports 1 to 6, 8, 9, a, and b (ports c to f are added in h8s/2160b and h8s/2161b) (write) figure 28.27 host interface (xbs) timing 746 (error) note: * the rising edge timing is the same as the port 4 and port b output timing. see figure 27.14. (correction) note: * the rising edge timing is the same as the port 4 and port b output timing. see figure 28.16. appendix a i/o port states in each processing state table a.1 i/o port states in each processing state 752 (error) ports c to g (correction) ports c to g (h8s/2160b, h8s/2161b) rev. 2.0, 08/02, page 784 of 788 item page revisions (see manual for details) 754 figure c.1 package dimensions (fp-100b) (error) (correction) 1.0 0.5 0.2 0 C 8 * 0.17 0.05 0.15 0.04 1.0 0.5 0.2 0 C 8 * 0.17 0.05 0.15 0.04 appendix c package dimensions 756 figure c.3 package dimensions (tfp-144) (error) (correction) 1.0 0.5 0.1 * 0.17 0.05 0.15 0.04 0 C 8 1.0 0.5 0.1 * 0.17 0.05 0.15 0.04 0 C 8 rev. 2.0, 08/02, page 785 of 788 index 14-bit pwm timer (pwmx) .................227 16-bit count mode .................................286 16-bit free-running timer (frt)..........241 2fh modification.....................................314 8-bit pwm timer (pwm) ......................217 8-bit timer (tmr) .................................267 a/d converter.........................................559 a20 gate .........................................495, 539 abrkcr .................. 89, 639, 648, 657, 667 absolute address ......................................53 activation by software ...........................151 adcr ..................... 564, 644, 653, 662, 673 adcsr ................... 563, 644, 653, 661, 673 addr ..................... 562, 643, 652, 661, 673 address map .............................................71 address space ...........................................33 addressing modes.....................................52 adi .........................................................569 analog input channel .............................562 arithmetic operations instructions ...........44 asynchronous mode ...............................357 bar .......................... 89, 639, 648, 657, 667 bcc ............................................................49 bcr......................... 115, 642, 651, 660, 671 bit manipulation instructions ...................47 bit rate .....................................................350 block configuration................................582 block data transfer instructions ..............51 block transfer mode ..............................146 boot mode ..............................................593 branch instructions ...................................49 break .......................................................386 brr......................... 350, 643, 652, 661, 672 buffered input capture input ..................256 burst rom interface...............................131 bus arbitration........................................134 bus controller (bsc) ..............................113 cascaded connection ..............................286 cblank output ....................................322 chain transfer.........................................147 clamp waveform generation..................310 clear timing ...........................................255 clock pulse generator.............................609 clocked synchronous mode....................374 cmi .........................................................290 cmia ......................................................290 cmiay....................................................290 cmib.......................................................290 cmiby....................................................290 compare-match count mode..................287 condition field...........................................51 condition-code register (ccr) ...............36 conversion time .....................................568 cra.........................................................138 crb.........................................................139 crystal resonator ....................................610 d/a converter .........................................553 dacnt ...................228, 641, 650, 659, 670 dacr.....................232, 555, 641, 645, 650, .............................653, 659, 662, 669, 675 dadr0....................554, 645, 653, 662, 675 dadr1....................554, 645, 653, 662, 675 dar ........................................................138 data transfer controller (dtc) ..............135 data transfer instructions .........................43 ddcswi .................................................454 ddcswr................418, 639, 648, 657, 666 direct transitions ....................................632 dtc vector table ...................................141 dtcer....................139, 639, 648, 657, 667 dtvecr .................140, 639, 648, 657, 667 ebr1 .......................588, 639, 649, 658, 667 ebr2 .......................588, 639, 649, 658, 667 rev. 2.0, 08/02, page 786 of 788 eepmov instruction................................62 effective address......................................56 effective address extension.......................51 erase/erase-verify ..................................600 erasing units ............................................582 eri ..........................................................385 erri .......................................................548 error protection.......................................602 exception handling ..................................79 exception vector table ............................80 extended control register (exr) ............36 external trigger ......................................569 flash memory ..........................................577 flmcr1 ................. 587, 639, 649, 657, 667 flmcr2 ................. 588, 639, 649, 657, 667 formatless ...............................................424 fov ........................................................260 framing error ...........................................364 frc......................... 244, 640, 649, 658, 668 general registers ......................................35 hardware protection ...............................602 hardware standby mode ........................628 hicr ....................... 488, 644, 653, 662, 673 hicr0 ..................... 507, 637, 647, 656, 665 hicr1 ..................... 507, 637, 647, 656, 665 hicr2 ..................... 514, 637, 647, 656, 665 hicr3 ..................... 514, 637, 647, 656, 665 hirq.......................................................500 hisel ..................... 535, 637, 647, 656, 665 host interface lpc interface (lpc) .......503 host interface x-bus interface (xbs) ....483 hsynco output ....................................320 i 2 c bus data format ...............................424 i 2 c bus interface (iic) ............................393 ibf ..........................................................499 iccr ....................... 404, 643, 652, 661, 672 icdr ....................... 397, 643, 652, 661, 672 ici ...........................................................260 icix ........................................................290 icmr.......................401, 643, 652, 661, 672 icr ...........................88, 244, 639, 640, 648, .............................650, 657, 658, 666, 668 icsr........................414, 643, 652, 661, 672 icxr .......................420, 638, 648, 657, 666 idle cycle ................................................133 idr..........................491, 636, 647, 655, 665 ier ............................91, 642, 651, 660, 671 ihi signal divided waveform...................312 iici ..........................................................454 immediate..................................................54 increment timing....................................253 input capture input .................................255 instruction set ...........................................41 interrupt control modes............................99 interrupt controller ...................................85 interrupt exception handling....................82 interrupt exception handling vector table ...............................................................96 interrupt mask bit .....................................37 interval timer mode ...............................334 irda operation .......................................382 iscr..........................90, 639, 648, 657, 666 isr.............................92, 639, 648, 657, 666 kbbr......................470, 638, 648, 657, 666 kbcomp ................565, 639, 648, 657, 666 kbcr......................467, 638, 648, 657, 666 keyboard buffer controller ....................465 kmimr.....................92, 644, 653, 662, 673 kmimra ..................92, 644, 653, 662, 674 kmpcr...................177, 644, 653, 662, 674 ladr3....................517, 636, 646, 655, 665 logic operations instructions ...................46 lpwrcr ................620, 640, 649, 658, 667 mark state ...............................................386 mcu operating mode selection...............63 mdcr .......................64, 642, 651, 660, 671 medium-speed mode..............................625 memory indirect........................................55 module stop mode..................................632 rev. 2.0, 08/02, page 787 of 788 mra .......................................................137 mrb........................................................138 mstpcr................. 621, 640, 649, 658, 667 multiprocessor communication function .............................................................368 nmi interrupt ............................................95 noise canceler ........................................451 normal mode ..................................145, 152 oci..........................................................260 ocr ........................ 244, 640, 650, 658, 668 ocrdm ..................................................245 odr ........................ 491, 519, 636, 655, 665 odr1 ......................................................647 on-board programming modes ..............592 operation field ..........................................51 output compare output..........................254 overrun error ...........................................364 ovi .........................................................290 oviy.......................................................290 p1ddr .................... 160, 642, 651, 660, 670 p1dr....................... 161, 642, 651, 660, 670 p1pcr..................... 161, 641, 651, 659, 670 p2ddr .................... 163, 642, 651, 660, 670 p2dr....................... 164, 642, 651, 660, 670 p2pcr..................... 164, 642, 651, 659, 670 p3ddr .................... 167, 642, 651, 660, 670 p3dr....................... 167, 642, 651, 660, 671 p3pcr..................... 168, 642, 651, 660, 670 p4ddr .................... 170, 642, 651, 660, 670 p4dr....................... 170, 642, 651, 660, 671 p5ddr .................... 174, 642, 651, 660, 671 p5dr....................... 175, 642, 651, 660, 671 p6ddr .................... 176, 642, 651, 660, 671 p6dr....................... 177, 642, 651, 660, 671 p7pin...................... 181, 642, 651, 660, 671 p8ddr .................... 182, 642, 651, 660, 671 p8dr....................... 183, 642, 651, 660, 671 p9ddr .................... 187, 642, 651, 660, 671 p9dr....................... 188, 642, 651, 660, 671 paddr ................... 192, 641, 651, 659, 670 paodr ...................192, 641, 650, 659, 670 papin .....................193, 641, 650, 659, 670 parity error...............................................364 pbddr....................198, 642, 651, 660, 671 pbodr....................199, 642, 651, 660, 671 pbpin......................199, 642, 651, 660, 671 pcddr....................205, 637, 647, 656, 666 pcnocr .................208, 636, 646, 655, 664 pcodr....................206, 637, 647, 656, 665 pcpin......................207, 637, 647, 656, 666 pcsr .......................224, 639, 649, 658, 667 pdddr ...................205, 637, 647, 656, 666 pdnocr.................208, 636, 646, 655, 664 pdodr ...................206, 637, 647, 656, 665 pdpin .....................207, 637, 647, 656, 666 peddr....................210, 637, 647, 656, 665 penocr .................213, 636, 646, 655, 664 peodr....................211, 637, 647, 656, 665 pepin......................212, 637, 647, 656, 665 pfddr ....................210, 637, 647, 656, 665 pfnocr .................213, 636, 646, 655, 664 pfodr ....................211, 637, 647, 656, 665 pfpin ......................212, 637, 647, 656, 665 pgddr ...................214, 637, 647, 656, 665 pgnocr.................216, 636, 646, 655, 664 pgodr ...................215, 637, 647, 656, 665 pgpin .....................215, 637, 647, 656, 665 power-down modes................................617 program counter (pc)...............................36 program/erase protection........................602 program/program-verify.........................598 program-counter relative.........................54 programmer mode...................................604 pulse output ............................................253 pwdpr ...................222, 643, 652, 661, 672 pwdr .....................222, 643, 652, 661, 672 pwm decoding.......................................309 pwoer...................223, 643, 652, 661, 672 pwsl ......................220, 643, 652, 661, 672 rdr.........................342, 643, 652, 661, 672 register direct...........................................53 register field .............................................51 rev. 2.0, 08/02, page 788 of 788 register indirect........................................53 register indirect with displacement .........53 register indirect with post-increment ......53 register indirect with pre-decrement.......53 register information ...............................141 repeat mode ...........................................145 reset..........................................................81 reset exception handling.........................81 rsr.........................................................342 rxi..........................................................385 sar......................... 398, 643, 652, 661, 672 sarx...................... 399, 643, 652, 661, 672 sbycr ................... 618, 640, 649, 658, 667 scmr ..................... 349, 643, 652, 661, 672 scr......................... 345, 643, 652, 661, 672 sedgr ................... 307, 645, 654, 663, 675 serial communication interface (sci and irda) ...................................339 serial formats .........................................425 shift instructions.......................................46 shutdown function .................................497 single mode ............................................566 sirqcr .................. 527, 636, 647, 655, 665 sleep mode .............................................626 smi .........................................................550 smr ........................ 343, 643, 652, 661, 672 software activation ..................................153 software protection.................................602 software standby mode..........................627 ssr ......................... 347, 643, 652, 661, 672 stack pointer (sp)......................................35 stack status...............................................83 stcr......................... 67, 642, 651, 660, 671 str ......................... 520, 636, 647, 656, 665 subactive mode ......................................631 subsleep mode........................................630 swdtend .............................................148 syscr...................... 65, 642, 651, 660, 671 syscr2.................. 486, 639, 649, 658, 667 system control instructions ......................50 tcnt .....................271, 327, 641, 643, 650, .............................652, 659, 661, 670, 671 tcnt count timing...............................283 tconri ..................300, 645, 653, 662, 675 tconro ................303, 645, 654, 663, 675 tconrs .................305, 645, 654, 663, 675 tcor ......................271, 643, 652, 660, 671 tcorc ...................281, 645, 653, 662, 674 tcr ........................250, 272, 640, 642, 649, .............................651, 658, 660, 668, 671 tcsr...... 247, 275, 328, 640, 641, 643, 649, ..... 650, 651, 658, 659, 660, 668, 670, 671 tdr.........................342, 643, 652, 661, 672 tei ..........................................................385 ticr........................................................281 ticrf .....................281, 644, 653, 662, 674 ticrr .....................281, 644, 653, 662, 674 tier........................246, 640, 649, 658, 668 timer connection....................................297 tisr ........................282, 645, 653, 662, 674 tocr ......................251, 640, 650, 658, 668 toggle output ..........................................294 trap instruction exception handling ........82 tsr .........................................................342 twr........................520, 636, 646, 655, 664 txi ..........................................................385 user program mode ................................597 vsynco output ....................................321 wait control............................................130 watch mode ............................................629 watchdog timer (wdt) .........................325 watchdog timer mode ...........................332 wovi......................................................335 wscr .....................116, 642, 651, 660, 671 wuemrb.................92, 637, 647, 656, 665 h8s/2140b series hardware manual publication date: 1st edition, march 2002 2nd edition, august 2002 published by: business operation division semiconductor & integrated circuits hitachi, ltd. edited by: technical documentation group hitachi kodaira semiconductor co., ltd. copyright ? hitachi, ltd., 2002. all rights reserved. printed in japan. |
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